12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2b7d861d9SBoojin Kim /* 3b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4b7d861d9SBoojin Kim * http://www.samsung.com 5b3040e40SJassi Brar * 6b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 7b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 8b3040e40SJassi Brar */ 9b3040e40SJassi Brar 10b45aef3aSKatsuhiro Suzuki #include <linux/debugfs.h> 11b7d861d9SBoojin Kim #include <linux/kernel.h> 12b3040e40SJassi Brar #include <linux/io.h> 13b3040e40SJassi Brar #include <linux/init.h> 14b3040e40SJassi Brar #include <linux/slab.h> 15b3040e40SJassi Brar #include <linux/module.h> 16b7d861d9SBoojin Kim #include <linux/string.h> 17b7d861d9SBoojin Kim #include <linux/delay.h> 18b7d861d9SBoojin Kim #include <linux/interrupt.h> 19b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 20b3040e40SJassi Brar #include <linux/dmaengine.h> 21b3040e40SJassi Brar #include <linux/amba/bus.h> 221b9bb715SBoojin Kim #include <linux/scatterlist.h> 2393ed5544SThomas Abraham #include <linux/of.h> 24a80258f9SPadmavathi Venna #include <linux/of_dma.h> 25bcc7fa95SSachin Kamat #include <linux/err.h> 26ae43b328SKrzysztof Kozlowski #include <linux/pm_runtime.h> 271d48745bSFrank Mori Hess #include <linux/bug.h> 28b3040e40SJassi Brar 29d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 30b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 31b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 32b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 3386a8ce7dSShawn Lin #define PL330_MAX_BURST 16 34b7d861d9SBoojin Kim 35271e1b86SAddy Ke #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) 36271e1b86SAddy Ke 37f0564c7eSLars-Peter Clausen enum pl330_cachectrl { 38f0564c7eSLars-Peter Clausen CCTRL0, /* Noncacheable and nonbufferable */ 39f0564c7eSLars-Peter Clausen CCTRL1, /* Bufferable only */ 40f0564c7eSLars-Peter Clausen CCTRL2, /* Cacheable, but do not allocate */ 41f0564c7eSLars-Peter Clausen CCTRL3, /* Cacheable and bufferable, but do not allocate */ 42f0564c7eSLars-Peter Clausen INVALID1, /* AWCACHE = 0x1000 */ 43f0564c7eSLars-Peter Clausen INVALID2, 44f0564c7eSLars-Peter Clausen CCTRL6, /* Cacheable write-through, allocate on writes only */ 45f0564c7eSLars-Peter Clausen CCTRL7, /* Cacheable write-back, allocate on writes only */ 46b7d861d9SBoojin Kim }; 47b7d861d9SBoojin Kim 48b7d861d9SBoojin Kim enum pl330_byteswap { 49b7d861d9SBoojin Kim SWAP_NO, 50b7d861d9SBoojin Kim SWAP_2, 51b7d861d9SBoojin Kim SWAP_4, 52b7d861d9SBoojin Kim SWAP_8, 53b7d861d9SBoojin Kim SWAP_16, 54b7d861d9SBoojin Kim }; 55b7d861d9SBoojin Kim 56b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 57b7d861d9SBoojin Kim #define DS 0x0 58b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 59b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 60b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 61b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 62b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 63b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 64b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 65b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 66b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 67b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 68b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 69b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 70b7d861d9SBoojin Kim 71b7d861d9SBoojin Kim #define DPC 0x4 72b7d861d9SBoojin Kim #define INTEN 0x20 73b7d861d9SBoojin Kim #define ES 0x24 74b7d861d9SBoojin Kim #define INTSTATUS 0x28 75b7d861d9SBoojin Kim #define INTCLR 0x2c 76b7d861d9SBoojin Kim #define FSM 0x30 77b7d861d9SBoojin Kim #define FSC 0x34 78b7d861d9SBoojin Kim #define FTM 0x38 79b7d861d9SBoojin Kim 80b7d861d9SBoojin Kim #define _FTC 0x40 81b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 82b7d861d9SBoojin Kim 83b7d861d9SBoojin Kim #define _CS 0x100 84b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 85b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 86b7d861d9SBoojin Kim 87b7d861d9SBoojin Kim #define _CPC 0x104 88b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 89b7d861d9SBoojin Kim 90b7d861d9SBoojin Kim #define _SA 0x400 91b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 92b7d861d9SBoojin Kim 93b7d861d9SBoojin Kim #define _DA 0x404 94b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 95b7d861d9SBoojin Kim 96b7d861d9SBoojin Kim #define _CC 0x408 97b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 98b7d861d9SBoojin Kim 99b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 100b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 101b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 102b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 103b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 104b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 105b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 106b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 107b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 108b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 109b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 110b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 111b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 112b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 113b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 114b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 115b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 116b7d861d9SBoojin Kim 117b7d861d9SBoojin Kim #define _LC0 0x40c 118b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 119b7d861d9SBoojin Kim 120b7d861d9SBoojin Kim #define _LC1 0x410 121b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 122b7d861d9SBoojin Kim 123b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 124b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 125b7d861d9SBoojin Kim 126b7d861d9SBoojin Kim #define DBGCMD 0xd04 127b7d861d9SBoojin Kim #define DBGINST0 0xd08 128b7d861d9SBoojin Kim #define DBGINST1 0xd0c 129b7d861d9SBoojin Kim 130b7d861d9SBoojin Kim #define CR0 0xe00 131b7d861d9SBoojin Kim #define CR1 0xe04 132b7d861d9SBoojin Kim #define CR2 0xe08 133b7d861d9SBoojin Kim #define CR3 0xe0c 134b7d861d9SBoojin Kim #define CR4 0xe10 135b7d861d9SBoojin Kim #define CRD 0xe14 136b7d861d9SBoojin Kim 137b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1383ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1393ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1403ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1413ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1423ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 143b7d861d9SBoojin Kim 144b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 145b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 146b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 147b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 148b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 149b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 150b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 151b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 152b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 153b7d861d9SBoojin Kim 154b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 155b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 156b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 157b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 158b7d861d9SBoojin Kim 159b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 160b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 161b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 162b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 163b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 164b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 165b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 166b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 167b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 168b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 169b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 170b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 171b7d861d9SBoojin Kim 172b7d861d9SBoojin Kim #define PART 0x330 173b7d861d9SBoojin Kim #define DESIGNER 0x41 174b7d861d9SBoojin Kim #define REVISION 0x0 175b7d861d9SBoojin Kim #define INTEG_CFG 0x0 176b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 177b7d861d9SBoojin Kim 178b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 179b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 180b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 181b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 182b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 183b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 184b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 185b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 186b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 187b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 188b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 189b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 190b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 191b7d861d9SBoojin Kim 192b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 193b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 194b7d861d9SBoojin Kim 195b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 196b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 197b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 198b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 199b7d861d9SBoojin Kim #define CMD_DMALD 0x04 200b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 201b7d861d9SBoojin Kim #define CMD_DMALP 0x20 202b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 203b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 204b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 205b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 206b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 207b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 208b7d861d9SBoojin Kim #define CMD_DMAST 0x08 209b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 210b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 211b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 212b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 213b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 214b7d861d9SBoojin Kim 215b7d861d9SBoojin Kim #define SZ_DMAADDH 3 216b7d861d9SBoojin Kim #define SZ_DMAEND 1 217b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 218b7d861d9SBoojin Kim #define SZ_DMALD 1 219b7d861d9SBoojin Kim #define SZ_DMALDP 2 220b7d861d9SBoojin Kim #define SZ_DMALP 2 221b7d861d9SBoojin Kim #define SZ_DMALPEND 2 222b7d861d9SBoojin Kim #define SZ_DMAKILL 1 223b7d861d9SBoojin Kim #define SZ_DMAMOV 6 224b7d861d9SBoojin Kim #define SZ_DMANOP 1 225b7d861d9SBoojin Kim #define SZ_DMARMB 1 226b7d861d9SBoojin Kim #define SZ_DMASEV 2 227b7d861d9SBoojin Kim #define SZ_DMAST 1 228b7d861d9SBoojin Kim #define SZ_DMASTP 2 229b7d861d9SBoojin Kim #define SZ_DMASTZ 1 230b7d861d9SBoojin Kim #define SZ_DMAWFE 2 231b7d861d9SBoojin Kim #define SZ_DMAWFP 2 232b7d861d9SBoojin Kim #define SZ_DMAWMB 1 233b7d861d9SBoojin Kim #define SZ_DMAGO 6 234b7d861d9SBoojin Kim 235b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 236b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 237b7d861d9SBoojin Kim 238b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 239b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 240b7d861d9SBoojin Kim 241b7d861d9SBoojin Kim /* 242b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 243b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 244b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 245b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 246b7d861d9SBoojin Kim */ 247b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 248b7d861d9SBoojin Kim 249b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 250b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 251b7d861d9SBoojin Kim 252b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 253b7d861d9SBoojin Kim static unsigned cmd_line; 254b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 255b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 256b7d861d9SBoojin Kim printk(x); \ 257b7d861d9SBoojin Kim cmd_line += off; \ 258b7d861d9SBoojin Kim } while (0) 259b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 260b7d861d9SBoojin Kim #else 261b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 262b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 263b7d861d9SBoojin Kim #endif 264b7d861d9SBoojin Kim 265b7d861d9SBoojin Kim /* The number of default descriptors */ 266d2ebfb33SRussell King - ARM Linux 267b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 268b3040e40SJassi Brar 269ae43b328SKrzysztof Kozlowski /* Delay for runtime PM autosuspend, ms */ 270ae43b328SKrzysztof Kozlowski #define PL330_AUTOSUSPEND_DELAY 20 271ae43b328SKrzysztof Kozlowski 272b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 273b7d861d9SBoojin Kim struct pl330_config { 274b7d861d9SBoojin Kim u32 periph_id; 275b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 276b7d861d9SBoojin Kim unsigned int mode; 277b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 2781f0a5cbfSLiviu Dudau unsigned int data_buf_dep:11; 279b7d861d9SBoojin Kim unsigned int num_chan:4; 280b7d861d9SBoojin Kim unsigned int num_peri:6; 281b7d861d9SBoojin Kim u32 peri_ns; 282b7d861d9SBoojin Kim unsigned int num_events:6; 283b7d861d9SBoojin Kim u32 irq_ns; 284b7d861d9SBoojin Kim }; 285b7d861d9SBoojin Kim 286b7d861d9SBoojin Kim /** 287b7d861d9SBoojin Kim * Request Configuration. 288b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 289b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 290b7d861d9SBoojin Kim * 291b7d861d9SBoojin Kim * The Client may want to provide this info only for the 292b7d861d9SBoojin Kim * first request and a request with new settings. 293b7d861d9SBoojin Kim */ 294b7d861d9SBoojin Kim struct pl330_reqcfg { 295b7d861d9SBoojin Kim /* Address Incrementing */ 296b7d861d9SBoojin Kim unsigned dst_inc:1; 297b7d861d9SBoojin Kim unsigned src_inc:1; 298b7d861d9SBoojin Kim 299b7d861d9SBoojin Kim /* 300b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 301b7d861d9SBoojin Kim * and burst size/length are assumed same. 302b7d861d9SBoojin Kim */ 303b7d861d9SBoojin Kim bool nonsecure; 304b7d861d9SBoojin Kim bool privileged; 305b7d861d9SBoojin Kim bool insnaccess; 306b7d861d9SBoojin Kim unsigned brst_len:5; 307b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 308b7d861d9SBoojin Kim 309f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 310f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 311b7d861d9SBoojin Kim enum pl330_byteswap swap; 3123ecf51a4SBoojin Kim struct pl330_config *pcfg; 313b7d861d9SBoojin Kim }; 314b7d861d9SBoojin Kim 315b7d861d9SBoojin Kim /* 316b7d861d9SBoojin Kim * One cycle of DMAC operation. 317b7d861d9SBoojin Kim * There may be more than one xfer in a request. 318b7d861d9SBoojin Kim */ 319b7d861d9SBoojin Kim struct pl330_xfer { 320b7d861d9SBoojin Kim u32 src_addr; 321b7d861d9SBoojin Kim u32 dst_addr; 322b7d861d9SBoojin Kim /* Size to xfer */ 323b7d861d9SBoojin Kim u32 bytes; 324b7d861d9SBoojin Kim }; 325b7d861d9SBoojin Kim 326b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 327b7d861d9SBoojin Kim enum pl330_op_err { 328b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 329b7d861d9SBoojin Kim PL330_ERR_NONE, 330b7d861d9SBoojin Kim /* If req aborted due to global error. */ 331b7d861d9SBoojin Kim PL330_ERR_ABORT, 332b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 333b7d861d9SBoojin Kim PL330_ERR_FAIL, 334b7d861d9SBoojin Kim }; 335b7d861d9SBoojin Kim 336b7d861d9SBoojin Kim enum dmamov_dst { 337b7d861d9SBoojin Kim SAR = 0, 338b7d861d9SBoojin Kim CCR, 339b7d861d9SBoojin Kim DAR, 340b7d861d9SBoojin Kim }; 341b7d861d9SBoojin Kim 342b7d861d9SBoojin Kim enum pl330_dst { 343b7d861d9SBoojin Kim SRC = 0, 344b7d861d9SBoojin Kim DST, 345b7d861d9SBoojin Kim }; 346b7d861d9SBoojin Kim 347b7d861d9SBoojin Kim enum pl330_cond { 348b7d861d9SBoojin Kim SINGLE, 349b7d861d9SBoojin Kim BURST, 350b7d861d9SBoojin Kim ALWAYS, 351b7d861d9SBoojin Kim }; 352b7d861d9SBoojin Kim 3539dc5a315SLars-Peter Clausen struct dma_pl330_desc; 3549dc5a315SLars-Peter Clausen 355b7d861d9SBoojin Kim struct _pl330_req { 356b7d861d9SBoojin Kim u32 mc_bus; 357b7d861d9SBoojin Kim void *mc_cpu; 3589dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 359b7d861d9SBoojin Kim }; 360b7d861d9SBoojin Kim 361b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 362b7d861d9SBoojin Kim struct _pl330_tbd { 363b7d861d9SBoojin Kim bool reset_dmac; 364b7d861d9SBoojin Kim bool reset_mngr; 365b7d861d9SBoojin Kim u8 reset_chan; 366b7d861d9SBoojin Kim }; 367b7d861d9SBoojin Kim 368b7d861d9SBoojin Kim /* A DMAC Thread */ 369b7d861d9SBoojin Kim struct pl330_thread { 370b7d861d9SBoojin Kim u8 id; 371b7d861d9SBoojin Kim int ev; 372b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 373b7d861d9SBoojin Kim bool free; 374b7d861d9SBoojin Kim /* Parent DMAC */ 375b7d861d9SBoojin Kim struct pl330_dmac *dmac; 376b7d861d9SBoojin Kim /* Only two at a time */ 377b7d861d9SBoojin Kim struct _pl330_req req[2]; 378b7d861d9SBoojin Kim /* Index of the last enqueued request */ 379b7d861d9SBoojin Kim unsigned lstenq; 380b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 381b7d861d9SBoojin Kim int req_running; 382b7d861d9SBoojin Kim }; 383b7d861d9SBoojin Kim 384b7d861d9SBoojin Kim enum pl330_dmac_state { 385b7d861d9SBoojin Kim UNINIT, 386b7d861d9SBoojin Kim INIT, 387b7d861d9SBoojin Kim DYING, 388b7d861d9SBoojin Kim }; 389b7d861d9SBoojin Kim 390b3040e40SJassi Brar enum desc_status { 391b3040e40SJassi Brar /* In the DMAC pool */ 392b3040e40SJassi Brar FREE, 393b3040e40SJassi Brar /* 394d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 395b3040e40SJassi Brar * Also may be sitting on the work_list. 396b3040e40SJassi Brar */ 397b3040e40SJassi Brar PREP, 398b3040e40SJassi Brar /* 399b3040e40SJassi Brar * Sitting on the work_list and already submitted 400b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 401b3040e40SJassi Brar * of a channel can be BUSY at any time. 402b3040e40SJassi Brar */ 403b3040e40SJassi Brar BUSY, 404b3040e40SJassi Brar /* 405b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 406b3040e40SJassi Brar * by PL330 core 407b3040e40SJassi Brar */ 408b3040e40SJassi Brar DONE, 409b3040e40SJassi Brar }; 410b3040e40SJassi Brar 411b3040e40SJassi Brar struct dma_pl330_chan { 412b3040e40SJassi Brar /* Schedule desc completion */ 413b3040e40SJassi Brar struct tasklet_struct task; 414b3040e40SJassi Brar 415b3040e40SJassi Brar /* DMA-Engine Channel */ 416b3040e40SJassi Brar struct dma_chan chan; 417b3040e40SJassi Brar 41804abf5daSLars-Peter Clausen /* List of submitted descriptors */ 41904abf5daSLars-Peter Clausen struct list_head submitted_list; 42004abf5daSLars-Peter Clausen /* List of issued descriptors */ 421b3040e40SJassi Brar struct list_head work_list; 42239ff8613SLars-Peter Clausen /* List of completed descriptors */ 42339ff8613SLars-Peter Clausen struct list_head completed_list; 424b3040e40SJassi Brar 425b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 426b3040e40SJassi Brar * NULL if the channel is available to be acquired. 427b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 428b3040e40SJassi Brar * to the channel. 429b3040e40SJassi Brar */ 430f6f2421cSLars-Peter Clausen struct pl330_dmac *dmac; 431b3040e40SJassi Brar 432b3040e40SJassi Brar /* To protect channel manipulation */ 433b3040e40SJassi Brar spinlock_t lock; 434b3040e40SJassi Brar 43565ad6060SLars-Peter Clausen /* 43665ad6060SLars-Peter Clausen * Hardware channel thread of PL330 DMAC. NULL if the channel is 43765ad6060SLars-Peter Clausen * available. 438b3040e40SJassi Brar */ 43965ad6060SLars-Peter Clausen struct pl330_thread *thread; 4401b9bb715SBoojin Kim 4411b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 4421b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 4431d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 4444d6d74e2SRobin Murphy phys_addr_t fifo_addr; 4454d6d74e2SRobin Murphy /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */ 4464d6d74e2SRobin Murphy dma_addr_t fifo_dma; 4474d6d74e2SRobin Murphy enum dma_data_direction dir; 448445897cbSVinod Koul struct dma_slave_config slave_config; 44942bc9cf4SBoojin Kim 45042bc9cf4SBoojin Kim /* for cyclic capability */ 45142bc9cf4SBoojin Kim bool cyclic; 4525c9e6c2bSMarek Szyprowski 4535c9e6c2bSMarek Szyprowski /* for runtime pm tracking */ 4545c9e6c2bSMarek Szyprowski bool active; 455b3040e40SJassi Brar }; 456b3040e40SJassi Brar 457f6f2421cSLars-Peter Clausen struct pl330_dmac { 458b3040e40SJassi Brar /* DMA-Engine Device */ 459b3040e40SJassi Brar struct dma_device ddma; 460b3040e40SJassi Brar 461b714b84eSLars-Peter Clausen /* Holds info about sg limitations */ 462b714b84eSLars-Peter Clausen struct device_dma_parameters dma_parms; 463b714b84eSLars-Peter Clausen 464b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 465b3040e40SJassi Brar struct list_head desc_pool; 466b3040e40SJassi Brar /* To protect desc_pool manipulation */ 467b3040e40SJassi Brar spinlock_t pool_lock; 468b3040e40SJassi Brar 469f6f2421cSLars-Peter Clausen /* Size of MicroCode buffers for each channel. */ 470f6f2421cSLars-Peter Clausen unsigned mcbufsz; 471f6f2421cSLars-Peter Clausen /* ioremap'ed address of PL330 registers. */ 472f6f2421cSLars-Peter Clausen void __iomem *base; 473f6f2421cSLars-Peter Clausen /* Populated by the PL330 core driver during pl330_add */ 474f6f2421cSLars-Peter Clausen struct pl330_config pcfg; 475f6f2421cSLars-Peter Clausen 476f6f2421cSLars-Peter Clausen spinlock_t lock; 477f6f2421cSLars-Peter Clausen /* Maximum possible events/irqs */ 478f6f2421cSLars-Peter Clausen int events[32]; 479f6f2421cSLars-Peter Clausen /* BUS address of MicroCode buffer */ 480f6f2421cSLars-Peter Clausen dma_addr_t mcode_bus; 481f6f2421cSLars-Peter Clausen /* CPU address of MicroCode buffer */ 482f6f2421cSLars-Peter Clausen void *mcode_cpu; 483f6f2421cSLars-Peter Clausen /* List of all Channel threads */ 484f6f2421cSLars-Peter Clausen struct pl330_thread *channels; 485f6f2421cSLars-Peter Clausen /* Pointer to the MANAGER thread */ 486f6f2421cSLars-Peter Clausen struct pl330_thread *manager; 487f6f2421cSLars-Peter Clausen /* To handle bad news in interrupt */ 488f6f2421cSLars-Peter Clausen struct tasklet_struct tasks; 489f6f2421cSLars-Peter Clausen struct _pl330_tbd dmac_tbd; 490f6f2421cSLars-Peter Clausen /* State of DMAC operation */ 491f6f2421cSLars-Peter Clausen enum pl330_dmac_state state; 492f6f2421cSLars-Peter Clausen /* Holds list of reqs with due callbacks */ 493f6f2421cSLars-Peter Clausen struct list_head req_done; 494f6f2421cSLars-Peter Clausen 495b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 49670cbb163SLars-Peter Clausen unsigned int num_peripherals; 4974e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 498271e1b86SAddy Ke int quirks; 499271e1b86SAddy Ke }; 500271e1b86SAddy Ke 501271e1b86SAddy Ke static struct pl330_of_quirks { 502271e1b86SAddy Ke char *quirk; 503271e1b86SAddy Ke int id; 504271e1b86SAddy Ke } of_quirks[] = { 505271e1b86SAddy Ke { 506271e1b86SAddy Ke .quirk = "arm,pl330-broken-no-flushp", 507271e1b86SAddy Ke .id = PL330_QUIRK_BROKEN_NO_FLUSHP, 508271e1b86SAddy Ke } 509b3040e40SJassi Brar }; 510b3040e40SJassi Brar 511b3040e40SJassi Brar struct dma_pl330_desc { 512b3040e40SJassi Brar /* To attach to a queue as child */ 513b3040e40SJassi Brar struct list_head node; 514b3040e40SJassi Brar 515b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 516b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 517b3040e40SJassi Brar 518b3040e40SJassi Brar /* Xfer for PL330 core */ 519b3040e40SJassi Brar struct pl330_xfer px; 520b3040e40SJassi Brar 521b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 522b3040e40SJassi Brar 523b3040e40SJassi Brar enum desc_status status; 524b3040e40SJassi Brar 525aee4d1faSRobert Baldyga int bytes_requested; 526aee4d1faSRobert Baldyga bool last; 527aee4d1faSRobert Baldyga 528b3040e40SJassi Brar /* The channel which currently holds this desc */ 529b3040e40SJassi Brar struct dma_pl330_chan *pchan; 5309dc5a315SLars-Peter Clausen 5319dc5a315SLars-Peter Clausen enum dma_transfer_direction rqtype; 5329dc5a315SLars-Peter Clausen /* Index of peripheral for the xfer. */ 5339dc5a315SLars-Peter Clausen unsigned peri:5; 5349dc5a315SLars-Peter Clausen /* Hook to attach to DMAC's list of reqs with due callback */ 5359dc5a315SLars-Peter Clausen struct list_head rqd; 5369dc5a315SLars-Peter Clausen }; 5379dc5a315SLars-Peter Clausen 5389dc5a315SLars-Peter Clausen struct _xfer_spec { 5399dc5a315SLars-Peter Clausen u32 ccr; 5409dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 541b3040e40SJassi Brar }; 542b3040e40SJassi Brar 543445897cbSVinod Koul static int pl330_config_write(struct dma_chan *chan, 544445897cbSVinod Koul struct dma_slave_config *slave_config, 545445897cbSVinod Koul enum dma_transfer_direction direction); 546445897cbSVinod Koul 547b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 548b7d861d9SBoojin Kim { 5498ed30a14SLars-Peter Clausen return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; 550b7d861d9SBoojin Kim } 551b7d861d9SBoojin Kim 552b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 553b7d861d9SBoojin Kim { 554fbbcd9beSLars-Peter Clausen return thrd->dmac->manager == thrd; 555b7d861d9SBoojin Kim } 556b7d861d9SBoojin Kim 557b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 558b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 559b7d861d9SBoojin Kim { 560f6f2421cSLars-Peter Clausen return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 561b7d861d9SBoojin Kim } 562b7d861d9SBoojin Kim 5633ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 5643ecf51a4SBoojin Kim { 5653ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 5663ecf51a4SBoojin Kim } 5673ecf51a4SBoojin Kim 568b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 569b7d861d9SBoojin Kim { 570b7d861d9SBoojin Kim if (dry_run) 571b7d861d9SBoojin Kim return SZ_DMAEND; 572b7d861d9SBoojin Kim 573b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 574b7d861d9SBoojin Kim 575b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 576b7d861d9SBoojin Kim 577b7d861d9SBoojin Kim return SZ_DMAEND; 578b7d861d9SBoojin Kim } 579b7d861d9SBoojin Kim 580b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 581b7d861d9SBoojin Kim { 582b7d861d9SBoojin Kim if (dry_run) 583b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 584b7d861d9SBoojin Kim 585b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 586b7d861d9SBoojin Kim 587b7d861d9SBoojin Kim peri &= 0x1f; 588b7d861d9SBoojin Kim peri <<= 3; 589b7d861d9SBoojin Kim buf[1] = peri; 590b7d861d9SBoojin Kim 591b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 592b7d861d9SBoojin Kim 593b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 594b7d861d9SBoojin Kim } 595b7d861d9SBoojin Kim 596b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 597b7d861d9SBoojin Kim { 598b7d861d9SBoojin Kim if (dry_run) 599b7d861d9SBoojin Kim return SZ_DMALD; 600b7d861d9SBoojin Kim 601b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 602b7d861d9SBoojin Kim 603b7d861d9SBoojin Kim if (cond == SINGLE) 604b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 605b7d861d9SBoojin Kim else if (cond == BURST) 606b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 607b7d861d9SBoojin Kim 608b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 609b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 610b7d861d9SBoojin Kim 611b7d861d9SBoojin Kim return SZ_DMALD; 612b7d861d9SBoojin Kim } 613b7d861d9SBoojin Kim 614b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 615b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 616b7d861d9SBoojin Kim { 617b7d861d9SBoojin Kim if (dry_run) 618b7d861d9SBoojin Kim return SZ_DMALDP; 619b7d861d9SBoojin Kim 620b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 621b7d861d9SBoojin Kim 622b7d861d9SBoojin Kim if (cond == BURST) 623b7d861d9SBoojin Kim buf[0] |= (1 << 1); 624b7d861d9SBoojin Kim 625b7d861d9SBoojin Kim peri &= 0x1f; 626b7d861d9SBoojin Kim peri <<= 3; 627b7d861d9SBoojin Kim buf[1] = peri; 628b7d861d9SBoojin Kim 629b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 630b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 631b7d861d9SBoojin Kim 632b7d861d9SBoojin Kim return SZ_DMALDP; 633b7d861d9SBoojin Kim } 634b7d861d9SBoojin Kim 635b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 636b7d861d9SBoojin Kim unsigned loop, u8 cnt) 637b7d861d9SBoojin Kim { 638b7d861d9SBoojin Kim if (dry_run) 639b7d861d9SBoojin Kim return SZ_DMALP; 640b7d861d9SBoojin Kim 641b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 642b7d861d9SBoojin Kim 643b7d861d9SBoojin Kim if (loop) 644b7d861d9SBoojin Kim buf[0] |= (1 << 1); 645b7d861d9SBoojin Kim 646b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 647b7d861d9SBoojin Kim buf[1] = cnt; 648b7d861d9SBoojin Kim 649b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 650b7d861d9SBoojin Kim 651b7d861d9SBoojin Kim return SZ_DMALP; 652b7d861d9SBoojin Kim } 653b7d861d9SBoojin Kim 654b7d861d9SBoojin Kim struct _arg_LPEND { 655b7d861d9SBoojin Kim enum pl330_cond cond; 656b7d861d9SBoojin Kim bool forever; 657b7d861d9SBoojin Kim unsigned loop; 658b7d861d9SBoojin Kim u8 bjump; 659b7d861d9SBoojin Kim }; 660b7d861d9SBoojin Kim 661b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 662b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 663b7d861d9SBoojin Kim { 664b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 665b7d861d9SBoojin Kim bool forever = arg->forever; 666b7d861d9SBoojin Kim unsigned loop = arg->loop; 667b7d861d9SBoojin Kim u8 bjump = arg->bjump; 668b7d861d9SBoojin Kim 669b7d861d9SBoojin Kim if (dry_run) 670b7d861d9SBoojin Kim return SZ_DMALPEND; 671b7d861d9SBoojin Kim 672b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 673b7d861d9SBoojin Kim 674b7d861d9SBoojin Kim if (loop) 675b7d861d9SBoojin Kim buf[0] |= (1 << 2); 676b7d861d9SBoojin Kim 677b7d861d9SBoojin Kim if (!forever) 678b7d861d9SBoojin Kim buf[0] |= (1 << 4); 679b7d861d9SBoojin Kim 680b7d861d9SBoojin Kim if (cond == SINGLE) 681b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 682b7d861d9SBoojin Kim else if (cond == BURST) 683b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 684b7d861d9SBoojin Kim 685b7d861d9SBoojin Kim buf[1] = bjump; 686b7d861d9SBoojin Kim 687b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 688b7d861d9SBoojin Kim forever ? "FE" : "END", 689b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 690b7d861d9SBoojin Kim loop ? '1' : '0', 691b7d861d9SBoojin Kim bjump); 692b7d861d9SBoojin Kim 693b7d861d9SBoojin Kim return SZ_DMALPEND; 694b7d861d9SBoojin Kim } 695b7d861d9SBoojin Kim 696b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 697b7d861d9SBoojin Kim { 698b7d861d9SBoojin Kim if (dry_run) 699b7d861d9SBoojin Kim return SZ_DMAKILL; 700b7d861d9SBoojin Kim 701b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 702b7d861d9SBoojin Kim 703b7d861d9SBoojin Kim return SZ_DMAKILL; 704b7d861d9SBoojin Kim } 705b7d861d9SBoojin Kim 706b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 707b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 708b7d861d9SBoojin Kim { 709b7d861d9SBoojin Kim if (dry_run) 710b7d861d9SBoojin Kim return SZ_DMAMOV; 711b7d861d9SBoojin Kim 712b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 713b7d861d9SBoojin Kim buf[1] = dst; 714d07c9e1eSVladimir Murzin buf[2] = val; 715d07c9e1eSVladimir Murzin buf[3] = val >> 8; 716d07c9e1eSVladimir Murzin buf[4] = val >> 16; 717d07c9e1eSVladimir Murzin buf[5] = val >> 24; 718b7d861d9SBoojin Kim 719b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 720b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 721b7d861d9SBoojin Kim 722b7d861d9SBoojin Kim return SZ_DMAMOV; 723b7d861d9SBoojin Kim } 724b7d861d9SBoojin Kim 725b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 726b7d861d9SBoojin Kim { 727b7d861d9SBoojin Kim if (dry_run) 728b7d861d9SBoojin Kim return SZ_DMARMB; 729b7d861d9SBoojin Kim 730b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 731b7d861d9SBoojin Kim 732b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 733b7d861d9SBoojin Kim 734b7d861d9SBoojin Kim return SZ_DMARMB; 735b7d861d9SBoojin Kim } 736b7d861d9SBoojin Kim 737b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 738b7d861d9SBoojin Kim { 739b7d861d9SBoojin Kim if (dry_run) 740b7d861d9SBoojin Kim return SZ_DMASEV; 741b7d861d9SBoojin Kim 742b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 743b7d861d9SBoojin Kim 744b7d861d9SBoojin Kim ev &= 0x1f; 745b7d861d9SBoojin Kim ev <<= 3; 746b7d861d9SBoojin Kim buf[1] = ev; 747b7d861d9SBoojin Kim 748b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 749b7d861d9SBoojin Kim 750b7d861d9SBoojin Kim return SZ_DMASEV; 751b7d861d9SBoojin Kim } 752b7d861d9SBoojin Kim 753b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 754b7d861d9SBoojin Kim { 755b7d861d9SBoojin Kim if (dry_run) 756b7d861d9SBoojin Kim return SZ_DMAST; 757b7d861d9SBoojin Kim 758b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 759b7d861d9SBoojin Kim 760b7d861d9SBoojin Kim if (cond == SINGLE) 761b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 762b7d861d9SBoojin Kim else if (cond == BURST) 763b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 764b7d861d9SBoojin Kim 765b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 766b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 767b7d861d9SBoojin Kim 768b7d861d9SBoojin Kim return SZ_DMAST; 769b7d861d9SBoojin Kim } 770b7d861d9SBoojin Kim 771b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 772b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 773b7d861d9SBoojin Kim { 774b7d861d9SBoojin Kim if (dry_run) 775b7d861d9SBoojin Kim return SZ_DMASTP; 776b7d861d9SBoojin Kim 777b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 778b7d861d9SBoojin Kim 779b7d861d9SBoojin Kim if (cond == BURST) 780b7d861d9SBoojin Kim buf[0] |= (1 << 1); 781b7d861d9SBoojin Kim 782b7d861d9SBoojin Kim peri &= 0x1f; 783b7d861d9SBoojin Kim peri <<= 3; 784b7d861d9SBoojin Kim buf[1] = peri; 785b7d861d9SBoojin Kim 786b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 787b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 788b7d861d9SBoojin Kim 789b7d861d9SBoojin Kim return SZ_DMASTP; 790b7d861d9SBoojin Kim } 791b7d861d9SBoojin Kim 792b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 793b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 794b7d861d9SBoojin Kim { 795b7d861d9SBoojin Kim if (dry_run) 796b7d861d9SBoojin Kim return SZ_DMAWFP; 797b7d861d9SBoojin Kim 798b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 799b7d861d9SBoojin Kim 800b7d861d9SBoojin Kim if (cond == SINGLE) 801b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 802b7d861d9SBoojin Kim else if (cond == BURST) 803b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 804b7d861d9SBoojin Kim else 805b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 806b7d861d9SBoojin Kim 807b7d861d9SBoojin Kim peri &= 0x1f; 808b7d861d9SBoojin Kim peri <<= 3; 809b7d861d9SBoojin Kim buf[1] = peri; 810b7d861d9SBoojin Kim 811b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 812b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 813b7d861d9SBoojin Kim 814b7d861d9SBoojin Kim return SZ_DMAWFP; 815b7d861d9SBoojin Kim } 816b7d861d9SBoojin Kim 817b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 818b7d861d9SBoojin Kim { 819b7d861d9SBoojin Kim if (dry_run) 820b7d861d9SBoojin Kim return SZ_DMAWMB; 821b7d861d9SBoojin Kim 822b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 823b7d861d9SBoojin Kim 824b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 825b7d861d9SBoojin Kim 826b7d861d9SBoojin Kim return SZ_DMAWMB; 827b7d861d9SBoojin Kim } 828b7d861d9SBoojin Kim 829b7d861d9SBoojin Kim struct _arg_GO { 830b7d861d9SBoojin Kim u8 chan; 831b7d861d9SBoojin Kim u32 addr; 832b7d861d9SBoojin Kim unsigned ns; 833b7d861d9SBoojin Kim }; 834b7d861d9SBoojin Kim 835b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 836b7d861d9SBoojin Kim const struct _arg_GO *arg) 837b7d861d9SBoojin Kim { 838b7d861d9SBoojin Kim u8 chan = arg->chan; 839b7d861d9SBoojin Kim u32 addr = arg->addr; 840b7d861d9SBoojin Kim unsigned ns = arg->ns; 841b7d861d9SBoojin Kim 842b7d861d9SBoojin Kim if (dry_run) 843b7d861d9SBoojin Kim return SZ_DMAGO; 844b7d861d9SBoojin Kim 845b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 846b7d861d9SBoojin Kim buf[0] |= (ns << 1); 847b7d861d9SBoojin Kim buf[1] = chan & 0x7; 848d07c9e1eSVladimir Murzin buf[2] = addr; 849d07c9e1eSVladimir Murzin buf[3] = addr >> 8; 850d07c9e1eSVladimir Murzin buf[4] = addr >> 16; 851d07c9e1eSVladimir Murzin buf[5] = addr >> 24; 852b7d861d9SBoojin Kim 853b7d861d9SBoojin Kim return SZ_DMAGO; 854b7d861d9SBoojin Kim } 855b7d861d9SBoojin Kim 856b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 857b7d861d9SBoojin Kim 858b7d861d9SBoojin Kim /* Returns Time-Out */ 859b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 860b7d861d9SBoojin Kim { 861f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 862b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 863b7d861d9SBoojin Kim 864b7d861d9SBoojin Kim do { 865b7d861d9SBoojin Kim /* Until Manager is Idle */ 866b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 867b7d861d9SBoojin Kim break; 868b7d861d9SBoojin Kim 869b7d861d9SBoojin Kim cpu_relax(); 870b7d861d9SBoojin Kim } while (--loops); 871b7d861d9SBoojin Kim 872b7d861d9SBoojin Kim if (!loops) 873b7d861d9SBoojin Kim return true; 874b7d861d9SBoojin Kim 875b7d861d9SBoojin Kim return false; 876b7d861d9SBoojin Kim } 877b7d861d9SBoojin Kim 878b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 879b7d861d9SBoojin Kim u8 insn[], bool as_manager) 880b7d861d9SBoojin Kim { 881f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 882b7d861d9SBoojin Kim u32 val; 883b7d861d9SBoojin Kim 884b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 885b7d861d9SBoojin Kim if (!as_manager) { 886b7d861d9SBoojin Kim val |= (1 << 0); 887b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 888b7d861d9SBoojin Kim } 889b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 890b7d861d9SBoojin Kim 8913a2307f7SBen Dooks val = le32_to_cpu(*((__le32 *)&insn[2])); 892b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 893b7d861d9SBoojin Kim 894b7d861d9SBoojin Kim /* If timed out due to halted state-machine */ 895b7d861d9SBoojin Kim if (_until_dmac_idle(thrd)) { 896f6f2421cSLars-Peter Clausen dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 897b7d861d9SBoojin Kim return; 898b7d861d9SBoojin Kim } 899b7d861d9SBoojin Kim 900b7d861d9SBoojin Kim /* Get going */ 901b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 902b7d861d9SBoojin Kim } 903b7d861d9SBoojin Kim 904b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 905b7d861d9SBoojin Kim { 906f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 907b7d861d9SBoojin Kim u32 val; 908b7d861d9SBoojin Kim 909b7d861d9SBoojin Kim if (is_manager(thrd)) 910b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 911b7d861d9SBoojin Kim else 912b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 913b7d861d9SBoojin Kim 914b7d861d9SBoojin Kim switch (val) { 915b7d861d9SBoojin Kim case DS_ST_STOP: 916b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 917b7d861d9SBoojin Kim case DS_ST_EXEC: 918b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 919b7d861d9SBoojin Kim case DS_ST_CMISS: 920b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 921b7d861d9SBoojin Kim case DS_ST_UPDTPC: 922b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 923b7d861d9SBoojin Kim case DS_ST_WFE: 924b7d861d9SBoojin Kim return PL330_STATE_WFE; 925b7d861d9SBoojin Kim case DS_ST_FAULT: 926b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 927b7d861d9SBoojin Kim case DS_ST_ATBRR: 928b7d861d9SBoojin Kim if (is_manager(thrd)) 929b7d861d9SBoojin Kim return PL330_STATE_INVALID; 930b7d861d9SBoojin Kim else 931b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 932b7d861d9SBoojin Kim case DS_ST_QBUSY: 933b7d861d9SBoojin Kim if (is_manager(thrd)) 934b7d861d9SBoojin Kim return PL330_STATE_INVALID; 935b7d861d9SBoojin Kim else 936b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 937b7d861d9SBoojin Kim case DS_ST_WFP: 938b7d861d9SBoojin Kim if (is_manager(thrd)) 939b7d861d9SBoojin Kim return PL330_STATE_INVALID; 940b7d861d9SBoojin Kim else 941b7d861d9SBoojin Kim return PL330_STATE_WFP; 942b7d861d9SBoojin Kim case DS_ST_KILL: 943b7d861d9SBoojin Kim if (is_manager(thrd)) 944b7d861d9SBoojin Kim return PL330_STATE_INVALID; 945b7d861d9SBoojin Kim else 946b7d861d9SBoojin Kim return PL330_STATE_KILLING; 947b7d861d9SBoojin Kim case DS_ST_CMPLT: 948b7d861d9SBoojin Kim if (is_manager(thrd)) 949b7d861d9SBoojin Kim return PL330_STATE_INVALID; 950b7d861d9SBoojin Kim else 951b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 952b7d861d9SBoojin Kim case DS_ST_FLTCMP: 953b7d861d9SBoojin Kim if (is_manager(thrd)) 954b7d861d9SBoojin Kim return PL330_STATE_INVALID; 955b7d861d9SBoojin Kim else 956b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 957b7d861d9SBoojin Kim default: 958b7d861d9SBoojin Kim return PL330_STATE_INVALID; 959b7d861d9SBoojin Kim } 960b7d861d9SBoojin Kim } 961b7d861d9SBoojin Kim 962b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 963b7d861d9SBoojin Kim { 964f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 965b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 9662da254ccSSugar Zhang u32 inten = readl(regs + INTEN); 967b7d861d9SBoojin Kim 968b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 969b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 970b7d861d9SBoojin Kim 971b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 972b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 973b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 974b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 975b7d861d9SBoojin Kim return; 976b7d861d9SBoojin Kim 977b7d861d9SBoojin Kim _emit_KILL(0, insn); 978b7d861d9SBoojin Kim 979b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 9802da254ccSSugar Zhang 9812da254ccSSugar Zhang /* clear the event */ 9822da254ccSSugar Zhang if (inten & (1 << thrd->ev)) 9832da254ccSSugar Zhang writel(1 << thrd->ev, regs + INTCLR); 9842da254ccSSugar Zhang /* Stop generating interrupts for SEV */ 9852da254ccSSugar Zhang writel(inten & ~(1 << thrd->ev), regs + INTEN); 986b7d861d9SBoojin Kim } 987b7d861d9SBoojin Kim 988b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 989b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 990b7d861d9SBoojin Kim { 991f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 992b7d861d9SBoojin Kim struct _pl330_req *req; 9939dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 994b7d861d9SBoojin Kim struct _arg_GO go; 995b7d861d9SBoojin Kim unsigned ns; 996b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 997b7d861d9SBoojin Kim int idx; 998b7d861d9SBoojin Kim 999b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1000b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1001b7d861d9SBoojin Kim return true; 1002b7d861d9SBoojin Kim 1003b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 10048ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) { 1005b7d861d9SBoojin Kim req = &thrd->req[idx]; 10068ed30a14SLars-Peter Clausen } else { 1007b7d861d9SBoojin Kim idx = thrd->lstenq; 10088ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) 1009b7d861d9SBoojin Kim req = &thrd->req[idx]; 1010b7d861d9SBoojin Kim else 1011b7d861d9SBoojin Kim req = NULL; 1012b7d861d9SBoojin Kim } 1013b7d861d9SBoojin Kim 1014b7d861d9SBoojin Kim /* Return if no request */ 10158ed30a14SLars-Peter Clausen if (!req) 1016b7d861d9SBoojin Kim return true; 1017b7d861d9SBoojin Kim 10180091b9d6SAddy Ke /* Return if req is running */ 10190091b9d6SAddy Ke if (idx == thrd->req_running) 10200091b9d6SAddy Ke return true; 10210091b9d6SAddy Ke 10229dc5a315SLars-Peter Clausen desc = req->desc; 1023b7d861d9SBoojin Kim 10249dc5a315SLars-Peter Clausen ns = desc->rqcfg.nonsecure ? 1 : 0; 1025b7d861d9SBoojin Kim 1026b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1027b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1028f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1029b7d861d9SBoojin Kim __func__, __LINE__); 1030b7d861d9SBoojin Kim 1031b7d861d9SBoojin Kim go.chan = thrd->id; 1032b7d861d9SBoojin Kim go.addr = req->mc_bus; 1033b7d861d9SBoojin Kim go.ns = ns; 1034b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1035b7d861d9SBoojin Kim 1036b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1037b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1038b7d861d9SBoojin Kim 1039b7d861d9SBoojin Kim /* Only manager can execute GO */ 1040b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1041b7d861d9SBoojin Kim 1042b7d861d9SBoojin Kim thrd->req_running = idx; 1043b7d861d9SBoojin Kim 1044b7d861d9SBoojin Kim return true; 1045b7d861d9SBoojin Kim } 1046b7d861d9SBoojin Kim 1047b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1048b7d861d9SBoojin Kim { 1049b7d861d9SBoojin Kim switch (_state(thrd)) { 1050b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1051b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1052b7d861d9SBoojin Kim 1053b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1054b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1055bbcb8755SVinod Koul /* fall through */ 1056b7d861d9SBoojin Kim 1057b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1058b7d861d9SBoojin Kim _stop(thrd); 1059bbcb8755SVinod Koul /* fall through */ 1060b7d861d9SBoojin Kim 1061b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1062b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1063b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1064bbcb8755SVinod Koul /* fall through */ 1065b7d861d9SBoojin Kim 1066b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1067b7d861d9SBoojin Kim return _trigger(thrd); 1068b7d861d9SBoojin Kim 1069b7d861d9SBoojin Kim case PL330_STATE_WFP: 1070b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1071b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1072b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1073b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1074b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1075b7d861d9SBoojin Kim return true; 1076b7d861d9SBoojin Kim 1077b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1078b7d861d9SBoojin Kim default: 1079b7d861d9SBoojin Kim return false; 1080b7d861d9SBoojin Kim } 1081b7d861d9SBoojin Kim } 1082b7d861d9SBoojin Kim 1083b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1084b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1085b7d861d9SBoojin Kim { 1086b7d861d9SBoojin Kim int off = 0; 10879dc5a315SLars-Peter Clausen struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; 1088b7d861d9SBoojin Kim 10893ecf51a4SBoojin Kim /* check lock-up free version */ 10903ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 10913ecf51a4SBoojin Kim while (cyc--) { 10923ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 10933ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 10943ecf51a4SBoojin Kim } 10953ecf51a4SBoojin Kim } else { 1096b7d861d9SBoojin Kim while (cyc--) { 1097b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1098b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1099b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1100b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1101b7d861d9SBoojin Kim } 11023ecf51a4SBoojin Kim } 1103b7d861d9SBoojin Kim 1104b7d861d9SBoojin Kim return off; 1105b7d861d9SBoojin Kim } 1106b7d861d9SBoojin Kim 11071d48745bSFrank Mori Hess static u32 _emit_load(unsigned int dry_run, u8 buf[], 11081d48745bSFrank Mori Hess enum pl330_cond cond, enum dma_transfer_direction direction, 11091d48745bSFrank Mori Hess u8 peri) 1110b7d861d9SBoojin Kim { 1111b7d861d9SBoojin Kim int off = 0; 1112848e9776SBoojin Kim 11131d48745bSFrank Mori Hess switch (direction) { 11141d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 11151d48745bSFrank Mori Hess /* fall through */ 11161d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 11171d48745bSFrank Mori Hess off += _emit_LD(dry_run, &buf[off], cond); 11181d48745bSFrank Mori Hess break; 1119b7d861d9SBoojin Kim 11201d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 11211d48745bSFrank Mori Hess if (cond == ALWAYS) { 11221d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], SINGLE, 11231d48745bSFrank Mori Hess peri); 11241d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], BURST, 11251d48745bSFrank Mori Hess peri); 11261d48745bSFrank Mori Hess } else { 11271d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], cond, 11281d48745bSFrank Mori Hess peri); 11291d48745bSFrank Mori Hess } 11301d48745bSFrank Mori Hess break; 1131271e1b86SAddy Ke 11321d48745bSFrank Mori Hess default: 11331d48745bSFrank Mori Hess /* this code should be unreachable */ 11341d48745bSFrank Mori Hess WARN_ON(1); 11351d48745bSFrank Mori Hess break; 1136b7d861d9SBoojin Kim } 1137b7d861d9SBoojin Kim 1138b7d861d9SBoojin Kim return off; 1139b7d861d9SBoojin Kim } 1140b7d861d9SBoojin Kim 11411d48745bSFrank Mori Hess static inline u32 _emit_store(unsigned int dry_run, u8 buf[], 11421d48745bSFrank Mori Hess enum pl330_cond cond, enum dma_transfer_direction direction, 11431d48745bSFrank Mori Hess u8 peri) 1144b7d861d9SBoojin Kim { 1145b7d861d9SBoojin Kim int off = 0; 11461d48745bSFrank Mori Hess 11471d48745bSFrank Mori Hess switch (direction) { 11481d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 11491d48745bSFrank Mori Hess /* fall through */ 11501d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 11511d48745bSFrank Mori Hess off += _emit_ST(dry_run, &buf[off], cond); 11521d48745bSFrank Mori Hess break; 11531d48745bSFrank Mori Hess 11541d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 11551d48745bSFrank Mori Hess if (cond == ALWAYS) { 11561d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], SINGLE, 11571d48745bSFrank Mori Hess peri); 11581d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], BURST, 11591d48745bSFrank Mori Hess peri); 11601d48745bSFrank Mori Hess } else { 11611d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], cond, 11621d48745bSFrank Mori Hess peri); 11631d48745bSFrank Mori Hess } 11641d48745bSFrank Mori Hess break; 11651d48745bSFrank Mori Hess 11661d48745bSFrank Mori Hess default: 11671d48745bSFrank Mori Hess /* this code should be unreachable */ 11681d48745bSFrank Mori Hess WARN_ON(1); 11691d48745bSFrank Mori Hess break; 11701d48745bSFrank Mori Hess } 11711d48745bSFrank Mori Hess 11721d48745bSFrank Mori Hess return off; 11731d48745bSFrank Mori Hess } 11741d48745bSFrank Mori Hess 11751d48745bSFrank Mori Hess static inline int _ldst_peripheral(struct pl330_dmac *pl330, 11761d48745bSFrank Mori Hess unsigned dry_run, u8 buf[], 11771d48745bSFrank Mori Hess const struct _xfer_spec *pxs, int cyc, 11781d48745bSFrank Mori Hess enum pl330_cond cond) 11791d48745bSFrank Mori Hess { 11801d48745bSFrank Mori Hess int off = 0; 1181848e9776SBoojin Kim 1182271e1b86SAddy Ke if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) 1183271e1b86SAddy Ke cond = BURST; 1184271e1b86SAddy Ke 11851d48745bSFrank Mori Hess /* 11861d48745bSFrank Mori Hess * do FLUSHP at beginning to clear any stale dma requests before the 11871d48745bSFrank Mori Hess * first WFP. 11881d48745bSFrank Mori Hess */ 11891d48745bSFrank Mori Hess if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) 11901d48745bSFrank Mori Hess off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); 1191b7d861d9SBoojin Kim while (cyc--) { 1192848e9776SBoojin Kim off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); 11931d48745bSFrank Mori Hess off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype, 11941d48745bSFrank Mori Hess pxs->desc->peri); 11951d48745bSFrank Mori Hess off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype, 1196271e1b86SAddy Ke pxs->desc->peri); 1197b7d861d9SBoojin Kim } 1198b7d861d9SBoojin Kim 1199b7d861d9SBoojin Kim return off; 1200b7d861d9SBoojin Kim } 1201b7d861d9SBoojin Kim 1202271e1b86SAddy Ke static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1203b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1204b7d861d9SBoojin Kim { 1205b7d861d9SBoojin Kim int off = 0; 12061d48745bSFrank Mori Hess enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; 1207b7d861d9SBoojin Kim 12089dc5a315SLars-Peter Clausen switch (pxs->desc->rqtype) { 1209585a9d0bSLars-Peter Clausen case DMA_MEM_TO_DEV: 12101d48745bSFrank Mori Hess /* fall through */ 1211585a9d0bSLars-Peter Clausen case DMA_DEV_TO_MEM: 12121d48745bSFrank Mori Hess off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc, 12131d48745bSFrank Mori Hess cond); 1214b7d861d9SBoojin Kim break; 12151d48745bSFrank Mori Hess 1216585a9d0bSLars-Peter Clausen case DMA_MEM_TO_MEM: 1217b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1218b7d861d9SBoojin Kim break; 12191d48745bSFrank Mori Hess 1220b7d861d9SBoojin Kim default: 12211d48745bSFrank Mori Hess /* this code should be unreachable */ 12221d48745bSFrank Mori Hess WARN_ON(1); 12231d48745bSFrank Mori Hess break; 12241d48745bSFrank Mori Hess } 12251d48745bSFrank Mori Hess 12261d48745bSFrank Mori Hess return off; 12271d48745bSFrank Mori Hess } 12281d48745bSFrank Mori Hess 12291d48745bSFrank Mori Hess /* 12301d48745bSFrank Mori Hess * transfer dregs with single transfers to peripheral, or a reduced size burst 12311d48745bSFrank Mori Hess * for mem-to-mem. 12321d48745bSFrank Mori Hess */ 12331d48745bSFrank Mori Hess static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], 12341d48745bSFrank Mori Hess const struct _xfer_spec *pxs, int transfer_length) 12351d48745bSFrank Mori Hess { 12361d48745bSFrank Mori Hess int off = 0; 12371d48745bSFrank Mori Hess int dregs_ccr; 12381d48745bSFrank Mori Hess 12391d48745bSFrank Mori Hess if (transfer_length == 0) 12401d48745bSFrank Mori Hess return off; 12411d48745bSFrank Mori Hess 12421d48745bSFrank Mori Hess switch (pxs->desc->rqtype) { 12431d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 12441d48745bSFrank Mori Hess /* fall through */ 12451d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 12461d48745bSFrank Mori Hess off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 12471d48745bSFrank Mori Hess transfer_length, SINGLE); 12481d48745bSFrank Mori Hess break; 12491d48745bSFrank Mori Hess 12501d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 12511d48745bSFrank Mori Hess dregs_ccr = pxs->ccr; 12521d48745bSFrank Mori Hess dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) | 12531d48745bSFrank Mori Hess (0xf << CC_DSTBRSTLEN_SHFT)); 12541d48745bSFrank Mori Hess dregs_ccr |= (((transfer_length - 1) & 0xf) << 12551d48745bSFrank Mori Hess CC_SRCBRSTLEN_SHFT); 12561d48745bSFrank Mori Hess dregs_ccr |= (((transfer_length - 1) & 0xf) << 12571d48745bSFrank Mori Hess CC_DSTBRSTLEN_SHFT); 12581d48745bSFrank Mori Hess off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); 12591d48745bSFrank Mori Hess off += _ldst_memtomem(dry_run, &buf[off], pxs, 1); 12601d48745bSFrank Mori Hess break; 12611d48745bSFrank Mori Hess 12621d48745bSFrank Mori Hess default: 12631d48745bSFrank Mori Hess /* this code should be unreachable */ 12641d48745bSFrank Mori Hess WARN_ON(1); 1265b7d861d9SBoojin Kim break; 1266b7d861d9SBoojin Kim } 1267b7d861d9SBoojin Kim 1268b7d861d9SBoojin Kim return off; 1269b7d861d9SBoojin Kim } 1270b7d861d9SBoojin Kim 1271b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1272271e1b86SAddy Ke static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1273b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1274b7d861d9SBoojin Kim { 1275b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1276b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1277b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1278b7d861d9SBoojin Kim 127931495d60SMichal Suchanek if (*bursts == 1) 1280848e9776SBoojin Kim return _bursts(pl330, dry_run, buf, pxs, 1); 128131495d60SMichal Suchanek 1282b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1283b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1284b7d861d9SBoojin Kim lcnt1 = 256; 1285b7d861d9SBoojin Kim lcnt0 = 256; 1286b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1287b7d861d9SBoojin Kim } else if (*bursts > 256) { 1288b7d861d9SBoojin Kim lcnt1 = 256; 1289b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1290b7d861d9SBoojin Kim cyc = 1; 1291b7d861d9SBoojin Kim } else { 1292b7d861d9SBoojin Kim lcnt1 = *bursts; 1293b7d861d9SBoojin Kim lcnt0 = 0; 1294b7d861d9SBoojin Kim cyc = 1; 1295b7d861d9SBoojin Kim } 1296b7d861d9SBoojin Kim 1297b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1298271e1b86SAddy Ke szbrst = _bursts(pl330, 1, buf, pxs, 1); 1299b7d861d9SBoojin Kim 1300b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1301b7d861d9SBoojin Kim lpend.forever = false; 1302b7d861d9SBoojin Kim lpend.loop = 0; 1303b7d861d9SBoojin Kim lpend.bjump = 0; 1304b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1305b7d861d9SBoojin Kim 1306b7d861d9SBoojin Kim if (lcnt0) { 1307b7d861d9SBoojin Kim szlp *= 2; 1308b7d861d9SBoojin Kim szlpend *= 2; 1309b7d861d9SBoojin Kim } 1310b7d861d9SBoojin Kim 1311b7d861d9SBoojin Kim /* 1312b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1313b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1314b7d861d9SBoojin Kim * which is 8-bits and hence 255 1315b7d861d9SBoojin Kim */ 1316b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1317b7d861d9SBoojin Kim 1318b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1319b7d861d9SBoojin Kim 1320b7d861d9SBoojin Kim off = 0; 1321b7d861d9SBoojin Kim 1322b7d861d9SBoojin Kim if (lcnt0) { 1323b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1324b7d861d9SBoojin Kim ljmp0 = off; 1325b7d861d9SBoojin Kim } 1326b7d861d9SBoojin Kim 1327b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1328b7d861d9SBoojin Kim ljmp1 = off; 1329b7d861d9SBoojin Kim 1330271e1b86SAddy Ke off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); 1331b7d861d9SBoojin Kim 1332b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1333b7d861d9SBoojin Kim lpend.forever = false; 1334b7d861d9SBoojin Kim lpend.loop = 1; 1335b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1336b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1337b7d861d9SBoojin Kim 1338b7d861d9SBoojin Kim if (lcnt0) { 1339b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1340b7d861d9SBoojin Kim lpend.forever = false; 1341b7d861d9SBoojin Kim lpend.loop = 0; 1342b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1343b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1344b7d861d9SBoojin Kim } 1345b7d861d9SBoojin Kim 1346b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1347b7d861d9SBoojin Kim if (lcnt0) 1348b7d861d9SBoojin Kim *bursts *= lcnt0; 1349b7d861d9SBoojin Kim 1350b7d861d9SBoojin Kim return off; 1351b7d861d9SBoojin Kim } 1352b7d861d9SBoojin Kim 1353271e1b86SAddy Ke static inline int _setup_loops(struct pl330_dmac *pl330, 1354271e1b86SAddy Ke unsigned dry_run, u8 buf[], 1355b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1356b7d861d9SBoojin Kim { 13579dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1358b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1359b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 13601d48745bSFrank Mori Hess int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / 13611d48745bSFrank Mori Hess BRST_SIZE(ccr); 1362b7d861d9SBoojin Kim int off = 0; 1363b7d861d9SBoojin Kim 1364b7d861d9SBoojin Kim while (bursts) { 1365b7d861d9SBoojin Kim c = bursts; 1366271e1b86SAddy Ke off += _loop(pl330, dry_run, &buf[off], &c, pxs); 1367b7d861d9SBoojin Kim bursts -= c; 1368b7d861d9SBoojin Kim } 13691d48745bSFrank Mori Hess off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs); 1370b7d861d9SBoojin Kim 1371b7d861d9SBoojin Kim return off; 1372b7d861d9SBoojin Kim } 1373b7d861d9SBoojin Kim 1374271e1b86SAddy Ke static inline int _setup_xfer(struct pl330_dmac *pl330, 1375271e1b86SAddy Ke unsigned dry_run, u8 buf[], 1376b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1377b7d861d9SBoojin Kim { 13789dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1379b7d861d9SBoojin Kim int off = 0; 1380b7d861d9SBoojin Kim 1381b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1382b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1383b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1384b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1385b7d861d9SBoojin Kim 1386b7d861d9SBoojin Kim /* Setup Loop(s) */ 1387271e1b86SAddy Ke off += _setup_loops(pl330, dry_run, &buf[off], pxs); 1388b7d861d9SBoojin Kim 1389b7d861d9SBoojin Kim return off; 1390b7d861d9SBoojin Kim } 1391b7d861d9SBoojin Kim 1392b7d861d9SBoojin Kim /* 1393b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1394b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1395b7d861d9SBoojin Kim */ 1396271e1b86SAddy Ke static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, 1397271e1b86SAddy Ke struct pl330_thread *thrd, unsigned index, 1398271e1b86SAddy Ke struct _xfer_spec *pxs) 1399b7d861d9SBoojin Kim { 1400b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1401b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1402b7d861d9SBoojin Kim int off = 0; 1403b7d861d9SBoojin Kim 1404b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1405b7d861d9SBoojin Kim 1406b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1407b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1408b7d861d9SBoojin Kim 1409271e1b86SAddy Ke off += _setup_xfer(pl330, dry_run, &buf[off], pxs); 1410b7d861d9SBoojin Kim 1411b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1412b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1413b7d861d9SBoojin Kim /* DMAEND */ 1414b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1415b7d861d9SBoojin Kim 1416b7d861d9SBoojin Kim return off; 1417b7d861d9SBoojin Kim } 1418b7d861d9SBoojin Kim 1419b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1420b7d861d9SBoojin Kim { 1421b7d861d9SBoojin Kim u32 ccr = 0; 1422b7d861d9SBoojin Kim 1423b7d861d9SBoojin Kim if (rqc->src_inc) 1424b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1425b7d861d9SBoojin Kim 1426b7d861d9SBoojin Kim if (rqc->dst_inc) 1427b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1428b7d861d9SBoojin Kim 1429b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1430b7d861d9SBoojin Kim if (rqc->privileged) 1431b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1432b7d861d9SBoojin Kim if (rqc->nonsecure) 1433b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1434b7d861d9SBoojin Kim if (rqc->insnaccess) 1435b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1436b7d861d9SBoojin Kim 1437b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1438b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1439b7d861d9SBoojin Kim 1440b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1441b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1442b7d861d9SBoojin Kim 1443b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1444b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1445b7d861d9SBoojin Kim 1446b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1447b7d861d9SBoojin Kim 1448b7d861d9SBoojin Kim return ccr; 1449b7d861d9SBoojin Kim } 1450b7d861d9SBoojin Kim 1451b7d861d9SBoojin Kim /* 1452b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1453b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1454b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1455b7d861d9SBoojin Kim */ 14569dc5a315SLars-Peter Clausen static int pl330_submit_req(struct pl330_thread *thrd, 14579dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc) 1458b7d861d9SBoojin Kim { 1459f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = thrd->dmac; 1460b7d861d9SBoojin Kim struct _xfer_spec xs; 1461b7d861d9SBoojin Kim unsigned long flags; 1462b7d861d9SBoojin Kim unsigned idx; 1463b7d861d9SBoojin Kim u32 ccr; 1464b7d861d9SBoojin Kim int ret = 0; 1465b7d861d9SBoojin Kim 14661d48745bSFrank Mori Hess switch (desc->rqtype) { 14671d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 14681d48745bSFrank Mori Hess break; 14691d48745bSFrank Mori Hess 14701d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 14711d48745bSFrank Mori Hess break; 14721d48745bSFrank Mori Hess 14731d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 14741d48745bSFrank Mori Hess break; 14751d48745bSFrank Mori Hess 14761d48745bSFrank Mori Hess default: 14771d48745bSFrank Mori Hess return -ENOTSUPP; 14781d48745bSFrank Mori Hess } 14791d48745bSFrank Mori Hess 1480b7d861d9SBoojin Kim if (pl330->state == DYING 1481b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1482f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1483b7d861d9SBoojin Kim __func__, __LINE__); 1484b7d861d9SBoojin Kim return -EAGAIN; 1485b7d861d9SBoojin Kim } 1486b7d861d9SBoojin Kim 1487b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 14889dc5a315SLars-Peter Clausen if (desc->rqtype != DMA_MEM_TO_MEM && 14899dc5a315SLars-Peter Clausen desc->peri >= pl330->pcfg.num_peri) { 1490f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, 1491b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 14929dc5a315SLars-Peter Clausen __func__, __LINE__, desc->peri); 1493b7d861d9SBoojin Kim return -EINVAL; 1494b7d861d9SBoojin Kim } 1495b7d861d9SBoojin Kim 1496b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1497b7d861d9SBoojin Kim 1498b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1499b7d861d9SBoojin Kim ret = -EAGAIN; 1500b7d861d9SBoojin Kim goto xfer_exit; 1501b7d861d9SBoojin Kim } 1502b7d861d9SBoojin Kim 1503b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1504b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 15059dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 0; 1506b7d861d9SBoojin Kim else 15079dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 1; 1508b7d861d9SBoojin Kim 15099dc5a315SLars-Peter Clausen ccr = _prepare_ccr(&desc->rqcfg); 1510b7d861d9SBoojin Kim 15118ed30a14SLars-Peter Clausen idx = thrd->req[0].desc == NULL ? 0 : 1; 1512b7d861d9SBoojin Kim 1513b7d861d9SBoojin Kim xs.ccr = ccr; 15149dc5a315SLars-Peter Clausen xs.desc = desc; 1515b7d861d9SBoojin Kim 1516b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1517271e1b86SAddy Ke ret = _setup_req(pl330, 1, thrd, idx, &xs); 1518b7d861d9SBoojin Kim if (ret < 0) 1519b7d861d9SBoojin Kim goto xfer_exit; 1520b7d861d9SBoojin Kim 1521f6f2421cSLars-Peter Clausen if (ret > pl330->mcbufsz / 2) { 1522e5489d5eSMichal Suchanek dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", 1523e5489d5eSMichal Suchanek __func__, __LINE__, ret, pl330->mcbufsz / 2); 1524b7d861d9SBoojin Kim ret = -ENOMEM; 1525b7d861d9SBoojin Kim goto xfer_exit; 1526b7d861d9SBoojin Kim } 1527b7d861d9SBoojin Kim 1528b7d861d9SBoojin Kim /* Hook the request */ 1529b7d861d9SBoojin Kim thrd->lstenq = idx; 15309dc5a315SLars-Peter Clausen thrd->req[idx].desc = desc; 1531271e1b86SAddy Ke _setup_req(pl330, 0, thrd, idx, &xs); 1532b7d861d9SBoojin Kim 1533b7d861d9SBoojin Kim ret = 0; 1534b7d861d9SBoojin Kim 1535b7d861d9SBoojin Kim xfer_exit: 1536b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1537b7d861d9SBoojin Kim 1538b7d861d9SBoojin Kim return ret; 1539b7d861d9SBoojin Kim } 1540b7d861d9SBoojin Kim 15419dc5a315SLars-Peter Clausen static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) 15426079d38cSLars-Peter Clausen { 1543b1e51d77SJavier Martinez Canillas struct dma_pl330_chan *pch; 15446079d38cSLars-Peter Clausen unsigned long flags; 15456079d38cSLars-Peter Clausen 1546b1e51d77SJavier Martinez Canillas if (!desc) 1547b1e51d77SJavier Martinez Canillas return; 1548b1e51d77SJavier Martinez Canillas 1549b1e51d77SJavier Martinez Canillas pch = desc->pchan; 1550b1e51d77SJavier Martinez Canillas 15516079d38cSLars-Peter Clausen /* If desc aborted */ 15526079d38cSLars-Peter Clausen if (!pch) 15536079d38cSLars-Peter Clausen return; 15546079d38cSLars-Peter Clausen 15556079d38cSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 15566079d38cSLars-Peter Clausen 15576079d38cSLars-Peter Clausen desc->status = DONE; 15586079d38cSLars-Peter Clausen 15596079d38cSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 15606079d38cSLars-Peter Clausen 15616079d38cSLars-Peter Clausen tasklet_schedule(&pch->task); 15626079d38cSLars-Peter Clausen } 15636079d38cSLars-Peter Clausen 1564b7d861d9SBoojin Kim static void pl330_dotask(unsigned long data) 1565b7d861d9SBoojin Kim { 1566b7d861d9SBoojin Kim struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1567b7d861d9SBoojin Kim unsigned long flags; 1568b7d861d9SBoojin Kim int i; 1569b7d861d9SBoojin Kim 1570b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1571b7d861d9SBoojin Kim 1572b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1573b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1574b7d861d9SBoojin Kim pl330->state = DYING; 1575b7d861d9SBoojin Kim /* Reset the manager too */ 1576b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1577b7d861d9SBoojin Kim /* Clear the reset flag */ 1578b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1579b7d861d9SBoojin Kim } 1580b7d861d9SBoojin Kim 1581b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1582b7d861d9SBoojin Kim _stop(pl330->manager); 1583b7d861d9SBoojin Kim /* Reset all channels */ 1584f6f2421cSLars-Peter Clausen pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1585b7d861d9SBoojin Kim /* Clear the reset flag */ 1586b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1587b7d861d9SBoojin Kim } 1588b7d861d9SBoojin Kim 1589f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1590b7d861d9SBoojin Kim 1591b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1592b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1593f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1594b7d861d9SBoojin Kim enum pl330_op_err err; 1595b7d861d9SBoojin Kim 1596b7d861d9SBoojin Kim _stop(thrd); 1597b7d861d9SBoojin Kim 1598b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1599b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1600b7d861d9SBoojin Kim else 1601b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1602b7d861d9SBoojin Kim 1603b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 16049dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); 16059dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); 1606b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1607b7d861d9SBoojin Kim 16089dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 16099dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 16108ed30a14SLars-Peter Clausen thrd->req_running = -1; 1611b7d861d9SBoojin Kim 1612b7d861d9SBoojin Kim /* Clear the reset flag */ 1613b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1614b7d861d9SBoojin Kim } 1615b7d861d9SBoojin Kim } 1616b7d861d9SBoojin Kim 1617b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1618b7d861d9SBoojin Kim 1619b7d861d9SBoojin Kim return; 1620b7d861d9SBoojin Kim } 1621b7d861d9SBoojin Kim 1622b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1623f6f2421cSLars-Peter Clausen static int pl330_update(struct pl330_dmac *pl330) 1624b7d861d9SBoojin Kim { 1625a3ca8312SQi Hou struct dma_pl330_desc *descdone; 1626b7d861d9SBoojin Kim unsigned long flags; 1627b7d861d9SBoojin Kim void __iomem *regs; 1628b7d861d9SBoojin Kim u32 val; 1629b7d861d9SBoojin Kim int id, ev, ret = 0; 1630b7d861d9SBoojin Kim 1631f6f2421cSLars-Peter Clausen regs = pl330->base; 1632b7d861d9SBoojin Kim 1633b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1634b7d861d9SBoojin Kim 1635b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1636b7d861d9SBoojin Kim if (val) 1637b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1638b7d861d9SBoojin Kim else 1639b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1640b7d861d9SBoojin Kim 1641f6f2421cSLars-Peter Clausen val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1642b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1643b7d861d9SBoojin Kim if (val) { 1644b7d861d9SBoojin Kim int i = 0; 1645f6f2421cSLars-Peter Clausen while (i < pl330->pcfg.num_chan) { 1646b7d861d9SBoojin Kim if (val & (1 << i)) { 1647f6f2421cSLars-Peter Clausen dev_info(pl330->ddma.dev, 1648b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1649b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1650b7d861d9SBoojin Kim readl(regs + FTC(i))); 1651b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1652b7d861d9SBoojin Kim } 1653b7d861d9SBoojin Kim i++; 1654b7d861d9SBoojin Kim } 1655b7d861d9SBoojin Kim } 1656b7d861d9SBoojin Kim 1657b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1658b7d861d9SBoojin Kim val = readl(regs + ES); 1659f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events < 32 1660f6f2421cSLars-Peter Clausen && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1661b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1662f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1663f6f2421cSLars-Peter Clausen __LINE__); 1664b7d861d9SBoojin Kim ret = 1; 1665b7d861d9SBoojin Kim goto updt_exit; 1666b7d861d9SBoojin Kim } 1667b7d861d9SBoojin Kim 1668f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1669b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1670b7d861d9SBoojin Kim struct pl330_thread *thrd; 1671b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1672b7d861d9SBoojin Kim int active; 1673b7d861d9SBoojin Kim 1674b7d861d9SBoojin Kim /* Clear the event */ 1675b7d861d9SBoojin Kim if (inten & (1 << ev)) 1676b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1677b7d861d9SBoojin Kim 1678b7d861d9SBoojin Kim ret = 1; 1679b7d861d9SBoojin Kim 1680b7d861d9SBoojin Kim id = pl330->events[ev]; 1681b7d861d9SBoojin Kim 1682b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1683b7d861d9SBoojin Kim 1684b7d861d9SBoojin Kim active = thrd->req_running; 1685b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1686b7d861d9SBoojin Kim continue; 1687b7d861d9SBoojin Kim 1688fdec53d5SJavi Merino /* Detach the req */ 16899dc5a315SLars-Peter Clausen descdone = thrd->req[active].desc; 16909dc5a315SLars-Peter Clausen thrd->req[active].desc = NULL; 1691fdec53d5SJavi Merino 16920091b9d6SAddy Ke thrd->req_running = -1; 16930091b9d6SAddy Ke 1694b7d861d9SBoojin Kim /* Get going again ASAP */ 1695b7d861d9SBoojin Kim _start(thrd); 1696b7d861d9SBoojin Kim 1697b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 16989dc5a315SLars-Peter Clausen list_add_tail(&descdone->rqd, &pl330->req_done); 1699b7d861d9SBoojin Kim } 1700b7d861d9SBoojin Kim } 1701b7d861d9SBoojin Kim 1702b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 1703a3ca8312SQi Hou while (!list_empty(&pl330->req_done)) { 1704a3ca8312SQi Hou descdone = list_first_entry(&pl330->req_done, 1705a3ca8312SQi Hou struct dma_pl330_desc, rqd); 17069dc5a315SLars-Peter Clausen list_del(&descdone->rqd); 1707b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 17089dc5a315SLars-Peter Clausen dma_pl330_rqcb(descdone, PL330_ERR_NONE); 1709b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1710b7d861d9SBoojin Kim } 1711b7d861d9SBoojin Kim 1712b7d861d9SBoojin Kim updt_exit: 1713b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1714b7d861d9SBoojin Kim 1715b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1716b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1717b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1718b7d861d9SBoojin Kim ret = 1; 1719b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1720b7d861d9SBoojin Kim } 1721b7d861d9SBoojin Kim 1722b7d861d9SBoojin Kim return ret; 1723b7d861d9SBoojin Kim } 1724b7d861d9SBoojin Kim 1725b7d861d9SBoojin Kim /* Reserve an event */ 1726b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1727b7d861d9SBoojin Kim { 1728b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1729b7d861d9SBoojin Kim int ev; 1730b7d861d9SBoojin Kim 1731f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1732b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1733b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1734b7d861d9SBoojin Kim return ev; 1735b7d861d9SBoojin Kim } 1736b7d861d9SBoojin Kim 1737b7d861d9SBoojin Kim return -1; 1738b7d861d9SBoojin Kim } 1739b7d861d9SBoojin Kim 1740f6f2421cSLars-Peter Clausen static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1741b7d861d9SBoojin Kim { 1742f6f2421cSLars-Peter Clausen return pl330->pcfg.irq_ns & (1 << i); 1743b7d861d9SBoojin Kim } 1744b7d861d9SBoojin Kim 1745b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1746b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1747b7d861d9SBoojin Kim */ 1748f6f2421cSLars-Peter Clausen static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1749b7d861d9SBoojin Kim { 1750b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1751b7d861d9SBoojin Kim int chans, i; 1752b7d861d9SBoojin Kim 1753b7d861d9SBoojin Kim if (pl330->state == DYING) 1754b7d861d9SBoojin Kim return NULL; 1755b7d861d9SBoojin Kim 1756f6f2421cSLars-Peter Clausen chans = pl330->pcfg.num_chan; 1757b7d861d9SBoojin Kim 1758b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1759b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1760b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1761f6f2421cSLars-Peter Clausen _chan_ns(pl330, i))) { 1762b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1763b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1764b7d861d9SBoojin Kim thrd->free = false; 1765b7d861d9SBoojin Kim thrd->lstenq = 1; 17669dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 17679dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 17688ed30a14SLars-Peter Clausen thrd->req_running = -1; 1769b7d861d9SBoojin Kim break; 1770b7d861d9SBoojin Kim } 1771b7d861d9SBoojin Kim } 1772b7d861d9SBoojin Kim thrd = NULL; 1773b7d861d9SBoojin Kim } 1774b7d861d9SBoojin Kim 1775b7d861d9SBoojin Kim return thrd; 1776b7d861d9SBoojin Kim } 1777b7d861d9SBoojin Kim 1778b7d861d9SBoojin Kim /* Release an event */ 1779b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1780b7d861d9SBoojin Kim { 1781b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1782b7d861d9SBoojin Kim 1783b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1784f6f2421cSLars-Peter Clausen if (ev >= 0 && ev < pl330->pcfg.num_events 1785b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1786b7d861d9SBoojin Kim pl330->events[ev] = -1; 1787b7d861d9SBoojin Kim } 1788b7d861d9SBoojin Kim 178965ad6060SLars-Peter Clausen static void pl330_release_channel(struct pl330_thread *thrd) 1790b7d861d9SBoojin Kim { 1791b7d861d9SBoojin Kim if (!thrd || thrd->free) 1792b7d861d9SBoojin Kim return; 1793b7d861d9SBoojin Kim 1794b7d861d9SBoojin Kim _stop(thrd); 1795b7d861d9SBoojin Kim 17969dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); 17979dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); 1798b7d861d9SBoojin Kim 1799b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1800b7d861d9SBoojin Kim thrd->free = true; 1801b7d861d9SBoojin Kim } 1802b7d861d9SBoojin Kim 1803b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1804b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1805b7d861d9SBoojin Kim */ 1806f6f2421cSLars-Peter Clausen static void read_dmac_config(struct pl330_dmac *pl330) 1807b7d861d9SBoojin Kim { 1808f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1809b7d861d9SBoojin Kim u32 val; 1810b7d861d9SBoojin Kim 1811b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1812b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1813f6f2421cSLars-Peter Clausen pl330->pcfg.data_bus_width = 8 * (1 << val); 1814b7d861d9SBoojin Kim 1815b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1816b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1817f6f2421cSLars-Peter Clausen pl330->pcfg.data_buf_dep = val + 1; 1818b7d861d9SBoojin Kim 1819b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1820b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1821b7d861d9SBoojin Kim val += 1; 1822f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan = val; 1823b7d861d9SBoojin Kim 1824b7d861d9SBoojin Kim val = readl(regs + CR0); 1825b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1826b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1827b7d861d9SBoojin Kim val += 1; 1828f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = val; 1829f6f2421cSLars-Peter Clausen pl330->pcfg.peri_ns = readl(regs + CR4); 1830b7d861d9SBoojin Kim } else { 1831f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = 0; 1832b7d861d9SBoojin Kim } 1833b7d861d9SBoojin Kim 1834b7d861d9SBoojin Kim val = readl(regs + CR0); 1835b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1836f6f2421cSLars-Peter Clausen pl330->pcfg.mode |= DMAC_MODE_NS; 1837b7d861d9SBoojin Kim else 1838f6f2421cSLars-Peter Clausen pl330->pcfg.mode &= ~DMAC_MODE_NS; 1839b7d861d9SBoojin Kim 1840b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1841b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1842b7d861d9SBoojin Kim val += 1; 1843f6f2421cSLars-Peter Clausen pl330->pcfg.num_events = val; 1844b7d861d9SBoojin Kim 1845f6f2421cSLars-Peter Clausen pl330->pcfg.irq_ns = readl(regs + CR3); 1846b7d861d9SBoojin Kim } 1847b7d861d9SBoojin Kim 1848b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1849b7d861d9SBoojin Kim { 1850b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1851b7d861d9SBoojin Kim 1852b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 1853f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 1854b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 1855f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 18569dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 1857b7d861d9SBoojin Kim 1858b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1859f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 1860b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 1861f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 18629dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 18638ed30a14SLars-Peter Clausen 18648ed30a14SLars-Peter Clausen thrd->req_running = -1; 1865b7d861d9SBoojin Kim } 1866b7d861d9SBoojin Kim 1867b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 1868b7d861d9SBoojin Kim { 1869f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1870b7d861d9SBoojin Kim struct pl330_thread *thrd; 1871b7d861d9SBoojin Kim int i; 1872b7d861d9SBoojin Kim 1873b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 18746396bb22SKees Cook pl330->channels = kcalloc(1 + chans, sizeof(*thrd), 1875b7d861d9SBoojin Kim GFP_KERNEL); 1876b7d861d9SBoojin Kim if (!pl330->channels) 1877b7d861d9SBoojin Kim return -ENOMEM; 1878b7d861d9SBoojin Kim 1879b7d861d9SBoojin Kim /* Init Channel threads */ 1880b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1881b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1882b7d861d9SBoojin Kim thrd->id = i; 1883b7d861d9SBoojin Kim thrd->dmac = pl330; 1884b7d861d9SBoojin Kim _reset_thread(thrd); 1885b7d861d9SBoojin Kim thrd->free = true; 1886b7d861d9SBoojin Kim } 1887b7d861d9SBoojin Kim 1888b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 1889b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 1890b7d861d9SBoojin Kim thrd->id = chans; 1891b7d861d9SBoojin Kim thrd->dmac = pl330; 1892b7d861d9SBoojin Kim thrd->free = false; 1893b7d861d9SBoojin Kim pl330->manager = thrd; 1894b7d861d9SBoojin Kim 1895b7d861d9SBoojin Kim return 0; 1896b7d861d9SBoojin Kim } 1897b7d861d9SBoojin Kim 1898b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 1899b7d861d9SBoojin Kim { 1900f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1901b7d861d9SBoojin Kim int ret; 1902b7d861d9SBoojin Kim 1903b7d861d9SBoojin Kim /* 1904b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 1905b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1906b7d861d9SBoojin Kim */ 19071b2354dbSMitchel Humpherys pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, 1908f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 19091b2354dbSMitchel Humpherys &pl330->mcode_bus, GFP_KERNEL, 19101b2354dbSMitchel Humpherys DMA_ATTR_PRIVILEGED); 1911b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 1912f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1913b7d861d9SBoojin Kim __func__, __LINE__); 1914b7d861d9SBoojin Kim return -ENOMEM; 1915b7d861d9SBoojin Kim } 1916b7d861d9SBoojin Kim 1917b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 1918b7d861d9SBoojin Kim if (ret) { 1919f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1920b7d861d9SBoojin Kim __func__, __LINE__); 1921f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 1922f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1923b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 1924b7d861d9SBoojin Kim return ret; 1925b7d861d9SBoojin Kim } 1926b7d861d9SBoojin Kim 1927b7d861d9SBoojin Kim return 0; 1928b7d861d9SBoojin Kim } 1929b7d861d9SBoojin Kim 1930f6f2421cSLars-Peter Clausen static int pl330_add(struct pl330_dmac *pl330) 1931b7d861d9SBoojin Kim { 1932b7d861d9SBoojin Kim int i, ret; 1933b7d861d9SBoojin Kim 1934b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 1935f6f2421cSLars-Peter Clausen if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1936f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1937f6f2421cSLars-Peter Clausen pl330->pcfg.periph_id); 1938b7d861d9SBoojin Kim return -EINVAL; 1939b7d861d9SBoojin Kim } 1940b7d861d9SBoojin Kim 1941b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 1942f6f2421cSLars-Peter Clausen read_dmac_config(pl330); 1943b7d861d9SBoojin Kim 1944f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events == 0) { 1945f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1946b7d861d9SBoojin Kim __func__, __LINE__); 1947b7d861d9SBoojin Kim return -EINVAL; 1948b7d861d9SBoojin Kim } 1949b7d861d9SBoojin Kim 1950b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 1951b7d861d9SBoojin Kim 1952b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 1953b7d861d9SBoojin Kim 1954b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 1955f6f2421cSLars-Peter Clausen if (!pl330->mcbufsz) 1956f6f2421cSLars-Peter Clausen pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1957b7d861d9SBoojin Kim 1958b7d861d9SBoojin Kim /* Mark all events as free */ 1959f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_events; i++) 1960b7d861d9SBoojin Kim pl330->events[i] = -1; 1961b7d861d9SBoojin Kim 1962b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 1963b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 1964b7d861d9SBoojin Kim if (ret) { 1965f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1966b7d861d9SBoojin Kim return ret; 1967b7d861d9SBoojin Kim } 1968b7d861d9SBoojin Kim 1969b7d861d9SBoojin Kim tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 1970b7d861d9SBoojin Kim 1971b7d861d9SBoojin Kim pl330->state = INIT; 1972b7d861d9SBoojin Kim 1973b7d861d9SBoojin Kim return 0; 1974b7d861d9SBoojin Kim } 1975b7d861d9SBoojin Kim 1976b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 1977b7d861d9SBoojin Kim { 1978b7d861d9SBoojin Kim struct pl330_thread *thrd; 1979b7d861d9SBoojin Kim int i; 1980b7d861d9SBoojin Kim 1981b7d861d9SBoojin Kim /* Release Channel threads */ 1982f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1983b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 198465ad6060SLars-Peter Clausen pl330_release_channel(thrd); 1985b7d861d9SBoojin Kim } 1986b7d861d9SBoojin Kim 1987b7d861d9SBoojin Kim /* Free memory */ 1988b7d861d9SBoojin Kim kfree(pl330->channels); 1989b7d861d9SBoojin Kim 1990b7d861d9SBoojin Kim return 0; 1991b7d861d9SBoojin Kim } 1992b7d861d9SBoojin Kim 1993f6f2421cSLars-Peter Clausen static void pl330_del(struct pl330_dmac *pl330) 1994b7d861d9SBoojin Kim { 1995b7d861d9SBoojin Kim pl330->state = UNINIT; 1996b7d861d9SBoojin Kim 1997b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 1998b7d861d9SBoojin Kim 1999b7d861d9SBoojin Kim /* Free DMAC resources */ 2000f6f2421cSLars-Peter Clausen dmac_free_threads(pl330); 2001b7d861d9SBoojin Kim 2002f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 2003f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 2004f6f2421cSLars-Peter Clausen pl330->mcode_bus); 2005b7d861d9SBoojin Kim } 2006b7d861d9SBoojin Kim 20073e2ec13aSThomas Abraham /* forward declaration */ 20083e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 20093e2ec13aSThomas Abraham 2010b3040e40SJassi Brar static inline struct dma_pl330_chan * 2011b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 2012b3040e40SJassi Brar { 2013b3040e40SJassi Brar if (!ch) 2014b3040e40SJassi Brar return NULL; 2015b3040e40SJassi Brar 2016b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 2017b3040e40SJassi Brar } 2018b3040e40SJassi Brar 2019b3040e40SJassi Brar static inline struct dma_pl330_desc * 2020b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 2021b3040e40SJassi Brar { 2022b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 2023b3040e40SJassi Brar } 2024b3040e40SJassi Brar 2025b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 2026b3040e40SJassi Brar { 2027b3040e40SJassi Brar struct dma_pl330_desc *desc; 2028b3040e40SJassi Brar int ret; 2029b3040e40SJassi Brar 2030b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 2031b3040e40SJassi Brar 2032b3040e40SJassi Brar /* If already submitted */ 2033b3040e40SJassi Brar if (desc->status == BUSY) 203430fb980bSJassi Brar continue; 2035b3040e40SJassi Brar 20369dc5a315SLars-Peter Clausen ret = pl330_submit_req(pch->thread, desc); 2037b3040e40SJassi Brar if (!ret) { 2038b3040e40SJassi Brar desc->status = BUSY; 2039b3040e40SJassi Brar } else if (ret == -EAGAIN) { 2040b3040e40SJassi Brar /* QFull or DMAC Dying */ 2041b3040e40SJassi Brar break; 2042b3040e40SJassi Brar } else { 2043b3040e40SJassi Brar /* Unacceptable request */ 2044b3040e40SJassi Brar desc->status = DONE; 2045f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 2046b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 2047b3040e40SJassi Brar tasklet_schedule(&pch->task); 2048b3040e40SJassi Brar } 2049b3040e40SJassi Brar } 2050b3040e40SJassi Brar } 2051b3040e40SJassi Brar 2052b3040e40SJassi Brar static void pl330_tasklet(unsigned long data) 2053b3040e40SJassi Brar { 2054b3040e40SJassi Brar struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 2055b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 2056b3040e40SJassi Brar unsigned long flags; 2057ae43b328SKrzysztof Kozlowski bool power_down = false; 2058b3040e40SJassi Brar 2059b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2060b3040e40SJassi Brar 2061b3040e40SJassi Brar /* Pick up ripe tomatoes */ 2062b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2063b3040e40SJassi Brar if (desc->status == DONE) { 206430c1dc0fSTushar Behera if (!pch->cyclic) 2065f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 206639ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->completed_list); 2067b3040e40SJassi Brar } 2068b3040e40SJassi Brar 2069b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 2070b3040e40SJassi Brar fill_queue(pch); 2071b3040e40SJassi Brar 2072ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 2073ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 2074ae43b328SKrzysztof Kozlowski _stop(pch->thread); 2075ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 2076ae43b328SKrzysztof Kozlowski power_down = true; 20775c9e6c2bSMarek Szyprowski pch->active = false; 2078ae43b328SKrzysztof Kozlowski } else { 2079b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 2080c26939e5SLars-Peter Clausen spin_lock(&pch->thread->dmac->lock); 2081c26939e5SLars-Peter Clausen _start(pch->thread); 2082c26939e5SLars-Peter Clausen spin_unlock(&pch->thread->dmac->lock); 2083ae43b328SKrzysztof Kozlowski } 2084b3040e40SJassi Brar 208539ff8613SLars-Peter Clausen while (!list_empty(&pch->completed_list)) { 2086f08462c6SDave Jiang struct dmaengine_desc_callback cb; 2087b3040e40SJassi Brar 208839ff8613SLars-Peter Clausen desc = list_first_entry(&pch->completed_list, 208939ff8613SLars-Peter Clausen struct dma_pl330_desc, node); 209039ff8613SLars-Peter Clausen 2091f08462c6SDave Jiang dmaengine_desc_get_callback(&desc->txd, &cb); 209239ff8613SLars-Peter Clausen 209339ff8613SLars-Peter Clausen if (pch->cyclic) { 209439ff8613SLars-Peter Clausen desc->status = PREP; 209539ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->work_list); 2096ae43b328SKrzysztof Kozlowski if (power_down) { 20975c9e6c2bSMarek Szyprowski pch->active = true; 2098ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 2099ae43b328SKrzysztof Kozlowski _start(pch->thread); 2100ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 2101ae43b328SKrzysztof Kozlowski power_down = false; 2102ae43b328SKrzysztof Kozlowski } 210339ff8613SLars-Peter Clausen } else { 210439ff8613SLars-Peter Clausen desc->status = FREE; 210539ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->dmac->desc_pool); 210639ff8613SLars-Peter Clausen } 210739ff8613SLars-Peter Clausen 2108d38a8c62SDan Williams dma_descriptor_unmap(&desc->txd); 2109d38a8c62SDan Williams 2110f08462c6SDave Jiang if (dmaengine_desc_callback_valid(&cb)) { 211139ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2112f08462c6SDave Jiang dmaengine_desc_callback_invoke(&cb, NULL); 211339ff8613SLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 211439ff8613SLars-Peter Clausen } 211539ff8613SLars-Peter Clausen } 211639ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2117ae43b328SKrzysztof Kozlowski 2118ae43b328SKrzysztof Kozlowski /* If work list empty, power down */ 2119ae43b328SKrzysztof Kozlowski if (power_down) { 2120ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2121ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2122ae43b328SKrzysztof Kozlowski } 2123b3040e40SJassi Brar } 2124b3040e40SJassi Brar 2125a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2126a80258f9SPadmavathi Venna struct of_dma *ofdma) 2127a80258f9SPadmavathi Venna { 2128a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2129f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = ofdma->of_dma_data; 213070cbb163SLars-Peter Clausen unsigned int chan_id; 2131a80258f9SPadmavathi Venna 2132f6f2421cSLars-Peter Clausen if (!pl330) 2133f6f2421cSLars-Peter Clausen return NULL; 2134f6f2421cSLars-Peter Clausen 2135a80258f9SPadmavathi Venna if (count != 1) 2136a80258f9SPadmavathi Venna return NULL; 2137a80258f9SPadmavathi Venna 213870cbb163SLars-Peter Clausen chan_id = dma_spec->args[0]; 2139f6f2421cSLars-Peter Clausen if (chan_id >= pl330->num_peripherals) 214070cbb163SLars-Peter Clausen return NULL; 2141a80258f9SPadmavathi Venna 2142f6f2421cSLars-Peter Clausen return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2143a80258f9SPadmavathi Venna } 2144a80258f9SPadmavathi Venna 2145b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2146b3040e40SJassi Brar { 2147b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2148f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2149b3040e40SJassi Brar unsigned long flags; 2150b3040e40SJassi Brar 215191539eb1SIago Abal spin_lock_irqsave(&pl330->lock, flags); 2152b3040e40SJassi Brar 2153d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 215442bc9cf4SBoojin Kim pch->cyclic = false; 2155b3040e40SJassi Brar 2156f6f2421cSLars-Peter Clausen pch->thread = pl330_request_channel(pl330); 215765ad6060SLars-Peter Clausen if (!pch->thread) { 215891539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 215902747885SInderpal Singh return -ENOMEM; 2160b3040e40SJassi Brar } 2161b3040e40SJassi Brar 2162b3040e40SJassi Brar tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2163b3040e40SJassi Brar 216491539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 2165b3040e40SJassi Brar 2166b3040e40SJassi Brar return 1; 2167b3040e40SJassi Brar } 2168b3040e40SJassi Brar 21694d6d74e2SRobin Murphy /* 21704d6d74e2SRobin Murphy * We need the data direction between the DMAC (the dma-mapping "device") and 21714d6d74e2SRobin Murphy * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing! 21724d6d74e2SRobin Murphy */ 21734d6d74e2SRobin Murphy static enum dma_data_direction 21744d6d74e2SRobin Murphy pl330_dma_slave_map_dir(enum dma_transfer_direction dir) 21754d6d74e2SRobin Murphy { 21764d6d74e2SRobin Murphy switch (dir) { 21774d6d74e2SRobin Murphy case DMA_MEM_TO_DEV: 21784d6d74e2SRobin Murphy return DMA_FROM_DEVICE; 21794d6d74e2SRobin Murphy case DMA_DEV_TO_MEM: 21804d6d74e2SRobin Murphy return DMA_TO_DEVICE; 21814d6d74e2SRobin Murphy case DMA_DEV_TO_DEV: 21824d6d74e2SRobin Murphy return DMA_BIDIRECTIONAL; 21834d6d74e2SRobin Murphy default: 21844d6d74e2SRobin Murphy return DMA_NONE; 21854d6d74e2SRobin Murphy } 21864d6d74e2SRobin Murphy } 21874d6d74e2SRobin Murphy 21884d6d74e2SRobin Murphy static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch) 21894d6d74e2SRobin Murphy { 21904d6d74e2SRobin Murphy if (pch->dir != DMA_NONE) 21914d6d74e2SRobin Murphy dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma, 21924d6d74e2SRobin Murphy 1 << pch->burst_sz, pch->dir, 0); 21934d6d74e2SRobin Murphy pch->dir = DMA_NONE; 21944d6d74e2SRobin Murphy } 21954d6d74e2SRobin Murphy 21964d6d74e2SRobin Murphy 21974d6d74e2SRobin Murphy static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch, 21984d6d74e2SRobin Murphy enum dma_transfer_direction dir) 21994d6d74e2SRobin Murphy { 22004d6d74e2SRobin Murphy struct device *dev = pch->chan.device->dev; 22014d6d74e2SRobin Murphy enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir); 22024d6d74e2SRobin Murphy 22034d6d74e2SRobin Murphy /* Already mapped for this config? */ 22044d6d74e2SRobin Murphy if (pch->dir == dma_dir) 22054d6d74e2SRobin Murphy return true; 22064d6d74e2SRobin Murphy 22074d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 22084d6d74e2SRobin Murphy pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr, 22094d6d74e2SRobin Murphy 1 << pch->burst_sz, dma_dir, 0); 22104d6d74e2SRobin Murphy if (dma_mapping_error(dev, pch->fifo_dma)) 22114d6d74e2SRobin Murphy return false; 22124d6d74e2SRobin Murphy 22134d6d74e2SRobin Murphy pch->dir = dma_dir; 22144d6d74e2SRobin Murphy return true; 22154d6d74e2SRobin Murphy } 22164d6d74e2SRobin Murphy 22171d48745bSFrank Mori Hess static int fixup_burst_len(int max_burst_len, int quirks) 22181d48745bSFrank Mori Hess { 22191d48745bSFrank Mori Hess if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) 22201d48745bSFrank Mori Hess return 1; 22211d48745bSFrank Mori Hess else if (max_burst_len > PL330_MAX_BURST) 22221d48745bSFrank Mori Hess return PL330_MAX_BURST; 22231d48745bSFrank Mori Hess else if (max_burst_len < 1) 22241d48745bSFrank Mori Hess return 1; 22251d48745bSFrank Mori Hess else 22261d48745bSFrank Mori Hess return max_burst_len; 22271d48745bSFrank Mori Hess } 22281d48745bSFrank Mori Hess 2229445897cbSVinod Koul static int pl330_config_write(struct dma_chan *chan, 2230445897cbSVinod Koul struct dma_slave_config *slave_config, 2231445897cbSVinod Koul enum dma_transfer_direction direction) 2232740aa957SMaxime Ripard { 2233740aa957SMaxime Ripard struct dma_pl330_chan *pch = to_pchan(chan); 2234740aa957SMaxime Ripard 22354d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 2236445897cbSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2237740aa957SMaxime Ripard if (slave_config->dst_addr) 2238740aa957SMaxime Ripard pch->fifo_addr = slave_config->dst_addr; 2239740aa957SMaxime Ripard if (slave_config->dst_addr_width) 2240740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->dst_addr_width); 22411d48745bSFrank Mori Hess pch->burst_len = fixup_burst_len(slave_config->dst_maxburst, 22421d48745bSFrank Mori Hess pch->dmac->quirks); 2243445897cbSVinod Koul } else if (direction == DMA_DEV_TO_MEM) { 2244740aa957SMaxime Ripard if (slave_config->src_addr) 2245740aa957SMaxime Ripard pch->fifo_addr = slave_config->src_addr; 2246740aa957SMaxime Ripard if (slave_config->src_addr_width) 2247740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->src_addr_width); 22481d48745bSFrank Mori Hess pch->burst_len = fixup_burst_len(slave_config->src_maxburst, 22491d48745bSFrank Mori Hess pch->dmac->quirks); 2250740aa957SMaxime Ripard } 2251740aa957SMaxime Ripard 2252740aa957SMaxime Ripard return 0; 2253740aa957SMaxime Ripard } 2254740aa957SMaxime Ripard 2255445897cbSVinod Koul static int pl330_config(struct dma_chan *chan, 2256445897cbSVinod Koul struct dma_slave_config *slave_config) 2257445897cbSVinod Koul { 2258445897cbSVinod Koul struct dma_pl330_chan *pch = to_pchan(chan); 2259445897cbSVinod Koul 2260445897cbSVinod Koul memcpy(&pch->slave_config, slave_config, sizeof(*slave_config)); 2261445897cbSVinod Koul 2262445897cbSVinod Koul return 0; 2263445897cbSVinod Koul } 2264445897cbSVinod Koul 2265740aa957SMaxime Ripard static int pl330_terminate_all(struct dma_chan *chan) 2266b3040e40SJassi Brar { 2267b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 226839ff8613SLars-Peter Clausen struct dma_pl330_desc *desc; 2269b3040e40SJassi Brar unsigned long flags; 2270f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 22715c9e6c2bSMarek Szyprowski bool power_down = false; 2272b3040e40SJassi Brar 227381cc6edcSKrzysztof Kozlowski pm_runtime_get_sync(pl330->ddma.dev); 2274b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2275e4975654SJohn Keeping 2276c26939e5SLars-Peter Clausen spin_lock(&pl330->lock); 2277c26939e5SLars-Peter Clausen _stop(pch->thread); 2278c26939e5SLars-Peter Clausen pch->thread->req[0].desc = NULL; 2279c26939e5SLars-Peter Clausen pch->thread->req[1].desc = NULL; 2280c26939e5SLars-Peter Clausen pch->thread->req_running = -1; 2281e4975654SJohn Keeping spin_unlock(&pl330->lock); 2282e4975654SJohn Keeping 22835c9e6c2bSMarek Szyprowski power_down = pch->active; 22845c9e6c2bSMarek Szyprowski pch->active = false; 2285b3040e40SJassi Brar 2286b3040e40SJassi Brar /* Mark all desc done */ 228704abf5daSLars-Peter Clausen list_for_each_entry(desc, &pch->submitted_list, node) { 228804abf5daSLars-Peter Clausen desc->status = FREE; 228904abf5daSLars-Peter Clausen dma_cookie_complete(&desc->txd); 229004abf5daSLars-Peter Clausen } 229104abf5daSLars-Peter Clausen 229239ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->work_list , node) { 229339ff8613SLars-Peter Clausen desc->status = FREE; 229439ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 2295ae43b886SBoojin Kim } 2296b3040e40SJassi Brar 2297f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2298f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2299f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2300b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 230181cc6edcSKrzysztof Kozlowski pm_runtime_mark_last_busy(pl330->ddma.dev); 23025c9e6c2bSMarek Szyprowski if (power_down) 23035c9e6c2bSMarek Szyprowski pm_runtime_put_autosuspend(pl330->ddma.dev); 230481cc6edcSKrzysztof Kozlowski pm_runtime_put_autosuspend(pl330->ddma.dev); 2305b3040e40SJassi Brar 2306b3040e40SJassi Brar return 0; 2307b3040e40SJassi Brar } 2308b3040e40SJassi Brar 230988987d2cSRobert Baldyga /* 231088987d2cSRobert Baldyga * We don't support DMA_RESUME command because of hardware 231188987d2cSRobert Baldyga * limitations, so after pausing the channel we cannot restore 231288987d2cSRobert Baldyga * it to active state. We have to terminate channel and setup 231388987d2cSRobert Baldyga * DMA transfer again. This pause feature was implemented to 231488987d2cSRobert Baldyga * allow safely read residue before channel termination. 231588987d2cSRobert Baldyga */ 23165503aed8SBen Dooks static int pl330_pause(struct dma_chan *chan) 231788987d2cSRobert Baldyga { 231888987d2cSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 231988987d2cSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 232088987d2cSRobert Baldyga unsigned long flags; 232188987d2cSRobert Baldyga 232288987d2cSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 232388987d2cSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 232488987d2cSRobert Baldyga 232588987d2cSRobert Baldyga spin_lock(&pl330->lock); 232688987d2cSRobert Baldyga _stop(pch->thread); 232788987d2cSRobert Baldyga spin_unlock(&pl330->lock); 232888987d2cSRobert Baldyga 232988987d2cSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 233088987d2cSRobert Baldyga pm_runtime_mark_last_busy(pl330->ddma.dev); 233188987d2cSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 233288987d2cSRobert Baldyga 233388987d2cSRobert Baldyga return 0; 233488987d2cSRobert Baldyga } 233588987d2cSRobert Baldyga 2336b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2337b3040e40SJassi Brar { 2338b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 233991539eb1SIago Abal struct pl330_dmac *pl330 = pch->dmac; 2340b3040e40SJassi Brar unsigned long flags; 2341b3040e40SJassi Brar 2342b3040e40SJassi Brar tasklet_kill(&pch->task); 2343b3040e40SJassi Brar 2344ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 234591539eb1SIago Abal spin_lock_irqsave(&pl330->lock, flags); 2346da331ba8SBartlomiej Zolnierkiewicz 234765ad6060SLars-Peter Clausen pl330_release_channel(pch->thread); 234865ad6060SLars-Peter Clausen pch->thread = NULL; 2349b3040e40SJassi Brar 235042bc9cf4SBoojin Kim if (pch->cyclic) 235142bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 235242bc9cf4SBoojin Kim 235391539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 2354ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2355ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 23564d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 2357b3040e40SJassi Brar } 2358b3040e40SJassi Brar 23595503aed8SBen Dooks static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, 2360aee4d1faSRobert Baldyga struct dma_pl330_desc *desc) 2361aee4d1faSRobert Baldyga { 2362aee4d1faSRobert Baldyga struct pl330_thread *thrd = pch->thread; 2363aee4d1faSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 2364aee4d1faSRobert Baldyga void __iomem *regs = thrd->dmac->base; 2365aee4d1faSRobert Baldyga u32 val, addr; 2366aee4d1faSRobert Baldyga 2367aee4d1faSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 2368aee4d1faSRobert Baldyga val = addr = 0; 2369aee4d1faSRobert Baldyga if (desc->rqcfg.src_inc) { 2370aee4d1faSRobert Baldyga val = readl(regs + SA(thrd->id)); 2371aee4d1faSRobert Baldyga addr = desc->px.src_addr; 2372aee4d1faSRobert Baldyga } else { 2373aee4d1faSRobert Baldyga val = readl(regs + DA(thrd->id)); 2374aee4d1faSRobert Baldyga addr = desc->px.dst_addr; 2375aee4d1faSRobert Baldyga } 2376aee4d1faSRobert Baldyga pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2377aee4d1faSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 2378c44da03dSStephen Barber 2379c44da03dSStephen Barber /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ 2380c44da03dSStephen Barber if (!val) 2381c44da03dSStephen Barber return 0; 2382c44da03dSStephen Barber 2383aee4d1faSRobert Baldyga return val - addr; 2384aee4d1faSRobert Baldyga } 2385aee4d1faSRobert Baldyga 2386b3040e40SJassi Brar static enum dma_status 2387b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2388b3040e40SJassi Brar struct dma_tx_state *txstate) 2389b3040e40SJassi Brar { 2390aee4d1faSRobert Baldyga enum dma_status ret; 2391aee4d1faSRobert Baldyga unsigned long flags; 2392d64e9a2cSStephen Barber struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; 2393aee4d1faSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 2394aee4d1faSRobert Baldyga unsigned int transferred, residual = 0; 2395aee4d1faSRobert Baldyga 2396aee4d1faSRobert Baldyga ret = dma_cookie_status(chan, cookie, txstate); 2397aee4d1faSRobert Baldyga 2398aee4d1faSRobert Baldyga if (!txstate) 2399aee4d1faSRobert Baldyga return ret; 2400aee4d1faSRobert Baldyga 2401aee4d1faSRobert Baldyga if (ret == DMA_COMPLETE) 2402aee4d1faSRobert Baldyga goto out; 2403aee4d1faSRobert Baldyga 2404aee4d1faSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 2405a40235a2SHsin-Yu Chao spin_lock(&pch->thread->dmac->lock); 2406aee4d1faSRobert Baldyga 2407aee4d1faSRobert Baldyga if (pch->thread->req_running != -1) 2408aee4d1faSRobert Baldyga running = pch->thread->req[pch->thread->req_running].desc; 2409aee4d1faSRobert Baldyga 2410d64e9a2cSStephen Barber last_enq = pch->thread->req[pch->thread->lstenq].desc; 2411d64e9a2cSStephen Barber 2412aee4d1faSRobert Baldyga /* Check in pending list */ 2413aee4d1faSRobert Baldyga list_for_each_entry(desc, &pch->work_list, node) { 2414aee4d1faSRobert Baldyga if (desc->status == DONE) 2415aee4d1faSRobert Baldyga transferred = desc->bytes_requested; 2416aee4d1faSRobert Baldyga else if (running && desc == running) 2417aee4d1faSRobert Baldyga transferred = 2418aee4d1faSRobert Baldyga pl330_get_current_xferred_count(pch, desc); 2419d64e9a2cSStephen Barber else if (desc->status == BUSY) 2420d64e9a2cSStephen Barber /* 2421d64e9a2cSStephen Barber * Busy but not running means either just enqueued, 2422d64e9a2cSStephen Barber * or finished and not yet marked done 2423d64e9a2cSStephen Barber */ 2424d64e9a2cSStephen Barber if (desc == last_enq) 2425d64e9a2cSStephen Barber transferred = 0; 2426d64e9a2cSStephen Barber else 2427d64e9a2cSStephen Barber transferred = desc->bytes_requested; 2428aee4d1faSRobert Baldyga else 2429aee4d1faSRobert Baldyga transferred = 0; 2430aee4d1faSRobert Baldyga residual += desc->bytes_requested - transferred; 2431aee4d1faSRobert Baldyga if (desc->txd.cookie == cookie) { 243275967b78SBen Dooks switch (desc->status) { 243375967b78SBen Dooks case DONE: 243475967b78SBen Dooks ret = DMA_COMPLETE; 243575967b78SBen Dooks break; 243675967b78SBen Dooks case PREP: 243775967b78SBen Dooks case BUSY: 243875967b78SBen Dooks ret = DMA_IN_PROGRESS; 243975967b78SBen Dooks break; 244075967b78SBen Dooks default: 244175967b78SBen Dooks WARN_ON(1); 244275967b78SBen Dooks } 2443aee4d1faSRobert Baldyga break; 2444aee4d1faSRobert Baldyga } 2445aee4d1faSRobert Baldyga if (desc->last) 2446aee4d1faSRobert Baldyga residual = 0; 2447aee4d1faSRobert Baldyga } 2448a40235a2SHsin-Yu Chao spin_unlock(&pch->thread->dmac->lock); 2449aee4d1faSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 2450aee4d1faSRobert Baldyga 2451aee4d1faSRobert Baldyga out: 2452aee4d1faSRobert Baldyga dma_set_residue(txstate, residual); 2453aee4d1faSRobert Baldyga 2454aee4d1faSRobert Baldyga return ret; 2455b3040e40SJassi Brar } 2456b3040e40SJassi Brar 2457b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2458b3040e40SJassi Brar { 245904abf5daSLars-Peter Clausen struct dma_pl330_chan *pch = to_pchan(chan); 246004abf5daSLars-Peter Clausen unsigned long flags; 246104abf5daSLars-Peter Clausen 246204abf5daSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 2463ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 2464ae43b328SKrzysztof Kozlowski /* 2465ae43b328SKrzysztof Kozlowski * Warn on nothing pending. Empty submitted_list may 2466ae43b328SKrzysztof Kozlowski * break our pm_runtime usage counter as it is 2467ae43b328SKrzysztof Kozlowski * updated on work_list emptiness status. 2468ae43b328SKrzysztof Kozlowski */ 2469ae43b328SKrzysztof Kozlowski WARN_ON(list_empty(&pch->submitted_list)); 24705c9e6c2bSMarek Szyprowski pch->active = true; 2471ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 2472ae43b328SKrzysztof Kozlowski } 247304abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pch->work_list); 247404abf5daSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 247504abf5daSLars-Peter Clausen 247604abf5daSLars-Peter Clausen pl330_tasklet((unsigned long)pch); 2477b3040e40SJassi Brar } 2478b3040e40SJassi Brar 2479b3040e40SJassi Brar /* 2480b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2481b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2482b3040e40SJassi Brar * descriptor of the list. 2483b3040e40SJassi Brar */ 2484b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2485b3040e40SJassi Brar { 2486b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2487b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2488b3040e40SJassi Brar dma_cookie_t cookie; 2489b3040e40SJassi Brar unsigned long flags; 2490b3040e40SJassi Brar 2491b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2492b3040e40SJassi Brar 2493b3040e40SJassi Brar /* Assign cookies to all nodes */ 2494b3040e40SJassi Brar while (!list_empty(&last->node)) { 2495b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2496fc514460SLars-Peter Clausen if (pch->cyclic) { 2497fc514460SLars-Peter Clausen desc->txd.callback = last->txd.callback; 2498fc514460SLars-Peter Clausen desc->txd.callback_param = last->txd.callback_param; 2499fc514460SLars-Peter Clausen } 25005dd90e5bSKrzysztof Kozlowski desc->last = false; 2501b3040e40SJassi Brar 2502884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2503b3040e40SJassi Brar 250404abf5daSLars-Peter Clausen list_move_tail(&desc->node, &pch->submitted_list); 2505b3040e40SJassi Brar } 2506b3040e40SJassi Brar 2507aee4d1faSRobert Baldyga last->last = true; 2508884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 250904abf5daSLars-Peter Clausen list_add_tail(&last->node, &pch->submitted_list); 2510b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2511b3040e40SJassi Brar 2512b3040e40SJassi Brar return cookie; 2513b3040e40SJassi Brar } 2514b3040e40SJassi Brar 2515b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2516b3040e40SJassi Brar { 2517b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2518f0564c7eSLars-Peter Clausen desc->rqcfg.scctl = CCTRL0; 2519f0564c7eSLars-Peter Clausen desc->rqcfg.dcctl = CCTRL0; 2520b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2521b3040e40SJassi Brar 2522b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2523b3040e40SJassi Brar } 2524b3040e40SJassi Brar 2525b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 2526e5887103SAlexander Kochetkov static int add_desc(struct list_head *pool, spinlock_t *lock, 2527e5887103SAlexander Kochetkov gfp_t flg, int count) 2528b3040e40SJassi Brar { 2529b3040e40SJassi Brar struct dma_pl330_desc *desc; 2530b3040e40SJassi Brar unsigned long flags; 2531b3040e40SJassi Brar int i; 2532b3040e40SJassi Brar 25330baf8f6aSWill Deacon desc = kcalloc(count, sizeof(*desc), flg); 2534b3040e40SJassi Brar if (!desc) 2535b3040e40SJassi Brar return 0; 2536b3040e40SJassi Brar 2537e5887103SAlexander Kochetkov spin_lock_irqsave(lock, flags); 2538b3040e40SJassi Brar 2539b3040e40SJassi Brar for (i = 0; i < count; i++) { 2540b3040e40SJassi Brar _init_desc(&desc[i]); 2541e5887103SAlexander Kochetkov list_add_tail(&desc[i].node, pool); 2542b3040e40SJassi Brar } 2543b3040e40SJassi Brar 2544e5887103SAlexander Kochetkov spin_unlock_irqrestore(lock, flags); 2545b3040e40SJassi Brar 2546b3040e40SJassi Brar return count; 2547b3040e40SJassi Brar } 2548b3040e40SJassi Brar 2549e5887103SAlexander Kochetkov static struct dma_pl330_desc *pluck_desc(struct list_head *pool, 2550e5887103SAlexander Kochetkov spinlock_t *lock) 2551b3040e40SJassi Brar { 2552b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2553b3040e40SJassi Brar unsigned long flags; 2554b3040e40SJassi Brar 2555e5887103SAlexander Kochetkov spin_lock_irqsave(lock, flags); 2556b3040e40SJassi Brar 2557e5887103SAlexander Kochetkov if (!list_empty(pool)) { 2558e5887103SAlexander Kochetkov desc = list_entry(pool->next, 2559b3040e40SJassi Brar struct dma_pl330_desc, node); 2560b3040e40SJassi Brar 2561b3040e40SJassi Brar list_del_init(&desc->node); 2562b3040e40SJassi Brar 2563b3040e40SJassi Brar desc->status = PREP; 2564b3040e40SJassi Brar desc->txd.callback = NULL; 2565b3040e40SJassi Brar } 2566b3040e40SJassi Brar 2567e5887103SAlexander Kochetkov spin_unlock_irqrestore(lock, flags); 2568b3040e40SJassi Brar 2569b3040e40SJassi Brar return desc; 2570b3040e40SJassi Brar } 2571b3040e40SJassi Brar 2572b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2573b3040e40SJassi Brar { 2574f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2575cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2576b3040e40SJassi Brar struct dma_pl330_desc *desc; 2577b3040e40SJassi Brar 2578b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2579e5887103SAlexander Kochetkov desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock); 2580b3040e40SJassi Brar 2581b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2582b3040e40SJassi Brar if (!desc) { 2583e5887103SAlexander Kochetkov DEFINE_SPINLOCK(lock); 2584e5887103SAlexander Kochetkov LIST_HEAD(pool); 2585e5887103SAlexander Kochetkov 2586e5887103SAlexander Kochetkov if (!add_desc(&pool, &lock, GFP_ATOMIC, 1)) 2587b3040e40SJassi Brar return NULL; 2588b3040e40SJassi Brar 2589e5887103SAlexander Kochetkov desc = pluck_desc(&pool, &lock); 2590e5887103SAlexander Kochetkov WARN_ON(!desc || !list_empty(&pool)); 2591b3040e40SJassi Brar } 2592b3040e40SJassi Brar 2593b3040e40SJassi Brar /* Initialize the descriptor */ 2594b3040e40SJassi Brar desc->pchan = pch; 2595b3040e40SJassi Brar desc->txd.cookie = 0; 2596b3040e40SJassi Brar async_tx_ack(&desc->txd); 2597b3040e40SJassi Brar 25989dc5a315SLars-Peter Clausen desc->peri = peri_id ? pch->chan.chan_id : 0; 2599f6f2421cSLars-Peter Clausen desc->rqcfg.pcfg = &pch->dmac->pcfg; 2600b3040e40SJassi Brar 2601b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2602b3040e40SJassi Brar 2603b3040e40SJassi Brar return desc; 2604b3040e40SJassi Brar } 2605b3040e40SJassi Brar 2606b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2607b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2608b3040e40SJassi Brar { 2609b3040e40SJassi Brar px->bytes = len; 2610b3040e40SJassi Brar px->dst_addr = dst; 2611b3040e40SJassi Brar px->src_addr = src; 2612b3040e40SJassi Brar } 2613b3040e40SJassi Brar 2614b3040e40SJassi Brar static struct dma_pl330_desc * 2615b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2616b3040e40SJassi Brar dma_addr_t src, size_t len) 2617b3040e40SJassi Brar { 2618b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2619b3040e40SJassi Brar 2620b3040e40SJassi Brar if (!desc) { 2621f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2622b3040e40SJassi Brar __func__, __LINE__); 2623b3040e40SJassi Brar return NULL; 2624b3040e40SJassi Brar } 2625b3040e40SJassi Brar 2626b3040e40SJassi Brar /* 2627b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2628b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2629b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2630b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2631b3040e40SJassi Brar * we take it easy. 2632b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2633b3040e40SJassi Brar * have the platform increase MC buffer size than 2634b3040e40SJassi Brar * complicating this API driver. 2635b3040e40SJassi Brar */ 2636b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2637b3040e40SJassi Brar 2638b3040e40SJassi Brar return desc; 2639b3040e40SJassi Brar } 2640b3040e40SJassi Brar 2641b3040e40SJassi Brar /* Call after fixing burst size */ 2642b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2643b3040e40SJassi Brar { 2644b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2645f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2646b3040e40SJassi Brar int burst_len; 2647b3040e40SJassi Brar 2648f6f2421cSLars-Peter Clausen burst_len = pl330->pcfg.data_bus_width / 8; 2649c27f9556SJon Medhurst burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; 2650b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2651b3040e40SJassi Brar 2652b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 26531d48745bSFrank Mori Hess if (burst_len > PL330_MAX_BURST) 26541d48745bSFrank Mori Hess burst_len = PL330_MAX_BURST; 2655b3040e40SJassi Brar 2656b3040e40SJassi Brar return burst_len; 2657b3040e40SJassi Brar } 2658b3040e40SJassi Brar 265942bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 266042bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2661185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 266231c1e5a1SLaurent Pinchart unsigned long flags) 266342bc9cf4SBoojin Kim { 2664fc514460SLars-Peter Clausen struct dma_pl330_desc *desc = NULL, *first = NULL; 266542bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 2666f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2667fc514460SLars-Peter Clausen unsigned int i; 266842bc9cf4SBoojin Kim dma_addr_t dst; 266942bc9cf4SBoojin Kim dma_addr_t src; 267042bc9cf4SBoojin Kim 2671fc514460SLars-Peter Clausen if (len % period_len != 0) 2672fc514460SLars-Peter Clausen return NULL; 2673fc514460SLars-Peter Clausen 2674fc514460SLars-Peter Clausen if (!is_slave_direction(direction)) { 2675f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2676fc514460SLars-Peter Clausen __func__, __LINE__); 2677fc514460SLars-Peter Clausen return NULL; 2678fc514460SLars-Peter Clausen } 2679fc514460SLars-Peter Clausen 2680445897cbSVinod Koul pl330_config_write(chan, &pch->slave_config, direction); 2681445897cbSVinod Koul 26824d6d74e2SRobin Murphy if (!pl330_prep_slave_fifo(pch, direction)) 26834d6d74e2SRobin Murphy return NULL; 26844d6d74e2SRobin Murphy 2685fc514460SLars-Peter Clausen for (i = 0; i < len / period_len; i++) { 268642bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 268742bc9cf4SBoojin Kim if (!desc) { 2688f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 268942bc9cf4SBoojin Kim __func__, __LINE__); 2690fc514460SLars-Peter Clausen 2691fc514460SLars-Peter Clausen if (!first) 2692fc514460SLars-Peter Clausen return NULL; 2693fc514460SLars-Peter Clausen 2694f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2695fc514460SLars-Peter Clausen 2696fc514460SLars-Peter Clausen while (!list_empty(&first->node)) { 2697fc514460SLars-Peter Clausen desc = list_entry(first->node.next, 2698fc514460SLars-Peter Clausen struct dma_pl330_desc, node); 2699f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 2700fc514460SLars-Peter Clausen } 2701fc514460SLars-Peter Clausen 2702f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 2703fc514460SLars-Peter Clausen 2704f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2705fc514460SLars-Peter Clausen 270642bc9cf4SBoojin Kim return NULL; 270742bc9cf4SBoojin Kim } 270842bc9cf4SBoojin Kim 270942bc9cf4SBoojin Kim switch (direction) { 2710db8196dfSVinod Koul case DMA_MEM_TO_DEV: 271142bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 271242bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 271342bc9cf4SBoojin Kim src = dma_addr; 27144d6d74e2SRobin Murphy dst = pch->fifo_dma; 271542bc9cf4SBoojin Kim break; 2716db8196dfSVinod Koul case DMA_DEV_TO_MEM: 271742bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 271842bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 27194d6d74e2SRobin Murphy src = pch->fifo_dma; 272042bc9cf4SBoojin Kim dst = dma_addr; 272142bc9cf4SBoojin Kim break; 272242bc9cf4SBoojin Kim default: 2723fc514460SLars-Peter Clausen break; 272442bc9cf4SBoojin Kim } 272542bc9cf4SBoojin Kim 27269dc5a315SLars-Peter Clausen desc->rqtype = direction; 272742bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 27281d48745bSFrank Mori Hess desc->rqcfg.brst_len = pch->burst_len; 2729aee4d1faSRobert Baldyga desc->bytes_requested = period_len; 2730fc514460SLars-Peter Clausen fill_px(&desc->px, dst, src, period_len); 2731fc514460SLars-Peter Clausen 2732fc514460SLars-Peter Clausen if (!first) 2733fc514460SLars-Peter Clausen first = desc; 2734fc514460SLars-Peter Clausen else 2735fc514460SLars-Peter Clausen list_add_tail(&desc->node, &first->node); 2736fc514460SLars-Peter Clausen 2737fc514460SLars-Peter Clausen dma_addr += period_len; 2738fc514460SLars-Peter Clausen } 2739fc514460SLars-Peter Clausen 2740fc514460SLars-Peter Clausen if (!desc) 2741fc514460SLars-Peter Clausen return NULL; 274242bc9cf4SBoojin Kim 274342bc9cf4SBoojin Kim pch->cyclic = true; 2744fc514460SLars-Peter Clausen desc->txd.flags = flags; 274542bc9cf4SBoojin Kim 274642bc9cf4SBoojin Kim return &desc->txd; 274742bc9cf4SBoojin Kim } 274842bc9cf4SBoojin Kim 2749b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2750b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2751b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2752b3040e40SJassi Brar { 2753b3040e40SJassi Brar struct dma_pl330_desc *desc; 2754b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2755f5636854SManinder Singh struct pl330_dmac *pl330; 2756b3040e40SJassi Brar int burst; 2757b3040e40SJassi Brar 27584e0e6109SRob Herring if (unlikely(!pch || !len)) 2759b3040e40SJassi Brar return NULL; 2760b3040e40SJassi Brar 2761f5636854SManinder Singh pl330 = pch->dmac; 2762f5636854SManinder Singh 2763b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2764b3040e40SJassi Brar if (!desc) 2765b3040e40SJassi Brar return NULL; 2766b3040e40SJassi Brar 2767b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2768b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 27699dc5a315SLars-Peter Clausen desc->rqtype = DMA_MEM_TO_MEM; 2770b3040e40SJassi Brar 2771b3040e40SJassi Brar /* Select max possible burst size */ 2772f6f2421cSLars-Peter Clausen burst = pl330->pcfg.data_bus_width / 8; 2773b3040e40SJassi Brar 2774137bd110SJon Medhurst /* 2775137bd110SJon Medhurst * Make sure we use a burst size that aligns with all the memcpy 2776137bd110SJon Medhurst * parameters because our DMA programming algorithm doesn't cope with 2777137bd110SJon Medhurst * transfers which straddle an entry in the DMA device's MFIFO. 2778137bd110SJon Medhurst */ 2779137bd110SJon Medhurst while ((src | dst | len) & (burst - 1)) 2780b3040e40SJassi Brar burst /= 2; 2781b3040e40SJassi Brar 2782b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2783b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2784b3040e40SJassi Brar desc->rqcfg.brst_size++; 2785b3040e40SJassi Brar 2786137bd110SJon Medhurst /* 2787137bd110SJon Medhurst * If burst size is smaller than bus width then make sure we only 2788137bd110SJon Medhurst * transfer one at a time to avoid a burst stradling an MFIFO entry. 2789137bd110SJon Medhurst */ 2790137bd110SJon Medhurst if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) 2791137bd110SJon Medhurst desc->rqcfg.brst_len = 1; 2792137bd110SJon Medhurst 2793b3040e40SJassi Brar desc->rqcfg.brst_len = get_burst_len(desc, len); 2794ae128293SKrzysztof Kozlowski desc->bytes_requested = len; 2795b3040e40SJassi Brar 2796b3040e40SJassi Brar desc->txd.flags = flags; 2797b3040e40SJassi Brar 2798b3040e40SJassi Brar return &desc->txd; 2799b3040e40SJassi Brar } 2800b3040e40SJassi Brar 2801f6f2421cSLars-Peter Clausen static void __pl330_giveback_desc(struct pl330_dmac *pl330, 280252a9d179SChanho Park struct dma_pl330_desc *first) 280352a9d179SChanho Park { 280452a9d179SChanho Park unsigned long flags; 280552a9d179SChanho Park struct dma_pl330_desc *desc; 280652a9d179SChanho Park 280752a9d179SChanho Park if (!first) 280852a9d179SChanho Park return; 280952a9d179SChanho Park 2810f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 281152a9d179SChanho Park 281252a9d179SChanho Park while (!list_empty(&first->node)) { 281352a9d179SChanho Park desc = list_entry(first->node.next, 281452a9d179SChanho Park struct dma_pl330_desc, node); 2815f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 281652a9d179SChanho Park } 281752a9d179SChanho Park 2818f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 281952a9d179SChanho Park 2820f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 282152a9d179SChanho Park } 282252a9d179SChanho Park 2823b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2824b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2825db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2826185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2827b3040e40SJassi Brar { 2828b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2829b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2830b3040e40SJassi Brar struct scatterlist *sg; 28311b9bb715SBoojin Kim int i; 2832b3040e40SJassi Brar 2833cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2834b3040e40SJassi Brar return NULL; 2835b3040e40SJassi Brar 2836445897cbSVinod Koul pl330_config_write(chan, &pch->slave_config, direction); 2837445897cbSVinod Koul 28384d6d74e2SRobin Murphy if (!pl330_prep_slave_fifo(pch, direction)) 28394d6d74e2SRobin Murphy return NULL; 2840b3040e40SJassi Brar 2841b3040e40SJassi Brar first = NULL; 2842b3040e40SJassi Brar 2843b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2844b3040e40SJassi Brar 2845b3040e40SJassi Brar desc = pl330_get_desc(pch); 2846b3040e40SJassi Brar if (!desc) { 2847f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2848b3040e40SJassi Brar 2849f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2850b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2851b3040e40SJassi Brar __func__, __LINE__); 2852f6f2421cSLars-Peter Clausen __pl330_giveback_desc(pl330, first); 2853b3040e40SJassi Brar 2854b3040e40SJassi Brar return NULL; 2855b3040e40SJassi Brar } 2856b3040e40SJassi Brar 2857b3040e40SJassi Brar if (!first) 2858b3040e40SJassi Brar first = desc; 2859b3040e40SJassi Brar else 2860b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2861b3040e40SJassi Brar 2862db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2863b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2864b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 28654d6d74e2SRobin Murphy fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg), 28664d6d74e2SRobin Murphy sg_dma_len(sg)); 2867b3040e40SJassi Brar } else { 2868b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2869b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 28704d6d74e2SRobin Murphy fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma, 28714d6d74e2SRobin Murphy sg_dma_len(sg)); 2872b3040e40SJassi Brar } 2873b3040e40SJassi Brar 28741b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 28751d48745bSFrank Mori Hess desc->rqcfg.brst_len = pch->burst_len; 28769dc5a315SLars-Peter Clausen desc->rqtype = direction; 2877aee4d1faSRobert Baldyga desc->bytes_requested = sg_dma_len(sg); 2878b3040e40SJassi Brar } 2879b3040e40SJassi Brar 2880b3040e40SJassi Brar /* Return the last desc in the chain */ 2881b3040e40SJassi Brar desc->txd.flags = flg; 2882b3040e40SJassi Brar return &desc->txd; 2883b3040e40SJassi Brar } 2884b3040e40SJassi Brar 2885b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2886b3040e40SJassi Brar { 2887b3040e40SJassi Brar if (pl330_update(data)) 2888b3040e40SJassi Brar return IRQ_HANDLED; 2889b3040e40SJassi Brar else 2890b3040e40SJassi Brar return IRQ_NONE; 2891b3040e40SJassi Brar } 2892b3040e40SJassi Brar 2893ca38ff13SLars-Peter Clausen #define PL330_DMA_BUSWIDTHS \ 2894ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2895ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2896ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2897ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2898ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2899ca38ff13SLars-Peter Clausen 2900b45aef3aSKatsuhiro Suzuki #ifdef CONFIG_DEBUG_FS 2901b45aef3aSKatsuhiro Suzuki static int pl330_debugfs_show(struct seq_file *s, void *data) 2902b45aef3aSKatsuhiro Suzuki { 2903b45aef3aSKatsuhiro Suzuki struct pl330_dmac *pl330 = s->private; 2904b45aef3aSKatsuhiro Suzuki int chans, pchs, ch, pr; 2905b45aef3aSKatsuhiro Suzuki 2906b45aef3aSKatsuhiro Suzuki chans = pl330->pcfg.num_chan; 2907b45aef3aSKatsuhiro Suzuki pchs = pl330->num_peripherals; 2908b45aef3aSKatsuhiro Suzuki 2909b45aef3aSKatsuhiro Suzuki seq_puts(s, "PL330 physical channels:\n"); 2910b45aef3aSKatsuhiro Suzuki seq_puts(s, "THREAD:\t\tCHANNEL:\n"); 2911b45aef3aSKatsuhiro Suzuki seq_puts(s, "--------\t-----\n"); 2912b45aef3aSKatsuhiro Suzuki for (ch = 0; ch < chans; ch++) { 2913b45aef3aSKatsuhiro Suzuki struct pl330_thread *thrd = &pl330->channels[ch]; 2914b45aef3aSKatsuhiro Suzuki int found = -1; 2915b45aef3aSKatsuhiro Suzuki 2916b45aef3aSKatsuhiro Suzuki for (pr = 0; pr < pchs; pr++) { 2917b45aef3aSKatsuhiro Suzuki struct dma_pl330_chan *pch = &pl330->peripherals[pr]; 2918b45aef3aSKatsuhiro Suzuki 2919b45aef3aSKatsuhiro Suzuki if (!pch->thread || thrd->id != pch->thread->id) 2920b45aef3aSKatsuhiro Suzuki continue; 2921b45aef3aSKatsuhiro Suzuki 2922b45aef3aSKatsuhiro Suzuki found = pr; 2923b45aef3aSKatsuhiro Suzuki } 2924b45aef3aSKatsuhiro Suzuki 2925b45aef3aSKatsuhiro Suzuki seq_printf(s, "%d\t\t", thrd->id); 2926b45aef3aSKatsuhiro Suzuki if (found == -1) 2927b45aef3aSKatsuhiro Suzuki seq_puts(s, "--\n"); 2928b45aef3aSKatsuhiro Suzuki else 2929b45aef3aSKatsuhiro Suzuki seq_printf(s, "%d\n", found); 2930b45aef3aSKatsuhiro Suzuki } 2931b45aef3aSKatsuhiro Suzuki 2932b45aef3aSKatsuhiro Suzuki return 0; 2933b45aef3aSKatsuhiro Suzuki } 2934b45aef3aSKatsuhiro Suzuki 2935b45aef3aSKatsuhiro Suzuki DEFINE_SHOW_ATTRIBUTE(pl330_debugfs); 2936b45aef3aSKatsuhiro Suzuki 2937b45aef3aSKatsuhiro Suzuki static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2938b45aef3aSKatsuhiro Suzuki { 2939b45aef3aSKatsuhiro Suzuki debugfs_create_file(dev_name(pl330->ddma.dev), 2940b45aef3aSKatsuhiro Suzuki S_IFREG | 0444, NULL, pl330, 2941b45aef3aSKatsuhiro Suzuki &pl330_debugfs_fops); 2942b45aef3aSKatsuhiro Suzuki } 2943b45aef3aSKatsuhiro Suzuki #else 2944b45aef3aSKatsuhiro Suzuki static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2945b45aef3aSKatsuhiro Suzuki { 2946b45aef3aSKatsuhiro Suzuki } 2947b45aef3aSKatsuhiro Suzuki #endif 2948b45aef3aSKatsuhiro Suzuki 2949b816ccc5SKrzysztof Kozlowski /* 2950b816ccc5SKrzysztof Kozlowski * Runtime PM callbacks are provided by amba/bus.c driver. 2951b816ccc5SKrzysztof Kozlowski * 2952b816ccc5SKrzysztof Kozlowski * It is assumed here that IRQ safe runtime PM is chosen in probe and amba 2953b816ccc5SKrzysztof Kozlowski * bus driver will only disable/enable the clock in runtime PM callbacks. 2954b816ccc5SKrzysztof Kozlowski */ 2955b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_suspend(struct device *dev) 2956b816ccc5SKrzysztof Kozlowski { 2957b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2958b816ccc5SKrzysztof Kozlowski 2959b816ccc5SKrzysztof Kozlowski pm_runtime_disable(dev); 2960b816ccc5SKrzysztof Kozlowski 2961b816ccc5SKrzysztof Kozlowski if (!pm_runtime_status_suspended(dev)) { 2962b816ccc5SKrzysztof Kozlowski /* amba did not disable the clock */ 2963b816ccc5SKrzysztof Kozlowski amba_pclk_disable(pcdev); 2964b816ccc5SKrzysztof Kozlowski } 2965b816ccc5SKrzysztof Kozlowski amba_pclk_unprepare(pcdev); 2966b816ccc5SKrzysztof Kozlowski 2967b816ccc5SKrzysztof Kozlowski return 0; 2968b816ccc5SKrzysztof Kozlowski } 2969b816ccc5SKrzysztof Kozlowski 2970b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_resume(struct device *dev) 2971b816ccc5SKrzysztof Kozlowski { 2972b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2973b816ccc5SKrzysztof Kozlowski int ret; 2974b816ccc5SKrzysztof Kozlowski 2975b816ccc5SKrzysztof Kozlowski ret = amba_pclk_prepare(pcdev); 2976b816ccc5SKrzysztof Kozlowski if (ret) 2977b816ccc5SKrzysztof Kozlowski return ret; 2978b816ccc5SKrzysztof Kozlowski 2979b816ccc5SKrzysztof Kozlowski if (!pm_runtime_status_suspended(dev)) 2980b816ccc5SKrzysztof Kozlowski ret = amba_pclk_enable(pcdev); 2981b816ccc5SKrzysztof Kozlowski 2982b816ccc5SKrzysztof Kozlowski pm_runtime_enable(dev); 2983b816ccc5SKrzysztof Kozlowski 2984b816ccc5SKrzysztof Kozlowski return ret; 2985b816ccc5SKrzysztof Kozlowski } 2986b816ccc5SKrzysztof Kozlowski 2987b816ccc5SKrzysztof Kozlowski static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); 2988b816ccc5SKrzysztof Kozlowski 2989463a1f8bSBill Pemberton static int 2990aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2991b3040e40SJassi Brar { 2992f6f2421cSLars-Peter Clausen struct pl330_config *pcfg; 2993f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330; 29940b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 2995b3040e40SJassi Brar struct dma_device *pd; 2996b3040e40SJassi Brar struct resource *res; 2997b3040e40SJassi Brar int i, ret, irq; 29984e0e6109SRob Herring int num_chan; 2999271e1b86SAddy Ke struct device_node *np = adev->dev.of_node; 3000b3040e40SJassi Brar 300164113016SRussell King ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 300264113016SRussell King if (ret) 300364113016SRussell King return ret; 300464113016SRussell King 3005b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 3006f6f2421cSLars-Peter Clausen pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 3007aef94feaSPeter Griffin if (!pl330) 3008b3040e40SJassi Brar return -ENOMEM; 3009b3040e40SJassi Brar 3010cee42392SAndrew Jackson pd = &pl330->ddma; 3011cee42392SAndrew Jackson pd->dev = &adev->dev; 3012cee42392SAndrew Jackson 3013e8bb4673SMarek Szyprowski pl330->mcbufsz = 0; 3014b3040e40SJassi Brar 3015271e1b86SAddy Ke /* get quirk */ 3016271e1b86SAddy Ke for (i = 0; i < ARRAY_SIZE(of_quirks); i++) 3017271e1b86SAddy Ke if (of_property_read_bool(np, of_quirks[i].quirk)) 3018271e1b86SAddy Ke pl330->quirks |= of_quirks[i].id; 3019271e1b86SAddy Ke 3020b3040e40SJassi Brar res = &adev->res; 3021f6f2421cSLars-Peter Clausen pl330->base = devm_ioremap_resource(&adev->dev, res); 3022f6f2421cSLars-Peter Clausen if (IS_ERR(pl330->base)) 3023f6f2421cSLars-Peter Clausen return PTR_ERR(pl330->base); 3024b3040e40SJassi Brar 3025f6f2421cSLars-Peter Clausen amba_set_drvdata(adev, pl330); 3026a2f5203fSBoojin Kim 302702808b42SDan Carpenter for (i = 0; i < AMBA_NR_IRQS; i++) { 3028e98b3cafSMichal Simek irq = adev->irq[i]; 3029e98b3cafSMichal Simek if (irq) { 3030e98b3cafSMichal Simek ret = devm_request_irq(&adev->dev, irq, 3031e98b3cafSMichal Simek pl330_irq_handler, 0, 3032f6f2421cSLars-Peter Clausen dev_name(&adev->dev), pl330); 3033b3040e40SJassi Brar if (ret) 3034e4d43c17SSachin Kamat return ret; 3035e98b3cafSMichal Simek } else { 3036e98b3cafSMichal Simek break; 3037e98b3cafSMichal Simek } 3038e98b3cafSMichal Simek } 3039b3040e40SJassi Brar 3040f6f2421cSLars-Peter Clausen pcfg = &pl330->pcfg; 3041f6f2421cSLars-Peter Clausen 3042f6f2421cSLars-Peter Clausen pcfg->periph_id = adev->periphid; 3043f6f2421cSLars-Peter Clausen ret = pl330_add(pl330); 3044b3040e40SJassi Brar if (ret) 3045173e838cSMichal Simek return ret; 3046b3040e40SJassi Brar 3047f6f2421cSLars-Peter Clausen INIT_LIST_HEAD(&pl330->desc_pool); 3048f6f2421cSLars-Peter Clausen spin_lock_init(&pl330->pool_lock); 3049b3040e40SJassi Brar 3050b3040e40SJassi Brar /* Create a descriptor pool of default size */ 3051e5887103SAlexander Kochetkov if (!add_desc(&pl330->desc_pool, &pl330->pool_lock, 3052e5887103SAlexander Kochetkov GFP_KERNEL, NR_DEFAULT_DESC)) 3053b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 3054b3040e40SJassi Brar 3055b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 3056b3040e40SJassi Brar 3057b3040e40SJassi Brar /* Initialize channel parameters */ 3058f6f2421cSLars-Peter Clausen num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 3059c8473828SOlof Johansson 3060f6f2421cSLars-Peter Clausen pl330->num_peripherals = num_chan; 306170cbb163SLars-Peter Clausen 30626396bb22SKees Cook pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL); 3063f6f2421cSLars-Peter Clausen if (!pl330->peripherals) { 306461c6e753SSachin Kamat ret = -ENOMEM; 3065e4d43c17SSachin Kamat goto probe_err2; 306661c6e753SSachin Kamat } 30674e0e6109SRob Herring 30684e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 3069f6f2421cSLars-Peter Clausen pch = &pl330->peripherals[i]; 3070b3040e40SJassi Brar 3071e8bb4673SMarek Szyprowski pch->chan.private = adev->dev.of_node; 307204abf5daSLars-Peter Clausen INIT_LIST_HEAD(&pch->submitted_list); 3073b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 307439ff8613SLars-Peter Clausen INIT_LIST_HEAD(&pch->completed_list); 3075b3040e40SJassi Brar spin_lock_init(&pch->lock); 307665ad6060SLars-Peter Clausen pch->thread = NULL; 3077b3040e40SJassi Brar pch->chan.device = pd; 3078f6f2421cSLars-Peter Clausen pch->dmac = pl330; 30794d6d74e2SRobin Murphy pch->dir = DMA_NONE; 3080b3040e40SJassi Brar 3081b3040e40SJassi Brar /* Add the channel to the DMAC list */ 3082b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 3083b3040e40SJassi Brar } 3084b3040e40SJassi Brar 3085cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 3086f6f2421cSLars-Peter Clausen if (pcfg->num_peri) { 308793ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 308893ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 30895557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 309093ed5544SThomas Abraham } 3091b3040e40SJassi Brar 3092b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 3093b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 3094b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 309542bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 3096b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 3097b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 3098740aa957SMaxime Ripard pd->device_config = pl330_config; 309988987d2cSRobert Baldyga pd->device_pause = pl330_pause; 3100740aa957SMaxime Ripard pd->device_terminate_all = pl330_terminate_all; 3101b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 3102dcabe456SMaxime Ripard pd->src_addr_widths = PL330_DMA_BUSWIDTHS; 3103dcabe456SMaxime Ripard pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; 3104dcabe456SMaxime Ripard pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 3105e3f329c6SMarek Szyprowski pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 310686a8ce7dSShawn Lin pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? 310786a8ce7dSShawn Lin 1 : PL330_MAX_BURST); 3108b3040e40SJassi Brar 3109b3040e40SJassi Brar ret = dma_async_device_register(pd); 3110b3040e40SJassi Brar if (ret) { 3111b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 31120b94c577SPadmavathi Venna goto probe_err3; 31130b94c577SPadmavathi Venna } 31140b94c577SPadmavathi Venna 31150b94c577SPadmavathi Venna if (adev->dev.of_node) { 31160b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 3117f6f2421cSLars-Peter Clausen of_dma_pl330_xlate, pl330); 31180b94c577SPadmavathi Venna if (ret) { 31190b94c577SPadmavathi Venna dev_err(&adev->dev, 31200b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 31210b94c577SPadmavathi Venna } 3122b3040e40SJassi Brar } 3123b714b84eSLars-Peter Clausen 3124f6f2421cSLars-Peter Clausen adev->dev.dma_parms = &pl330->dma_parms; 3125b714b84eSLars-Peter Clausen 3126dbaf6d85SVinod Koul /* 3127dbaf6d85SVinod Koul * This is the limit for transfers with a buswidth of 1, larger 3128dbaf6d85SVinod Koul * buswidths will have larger limits. 3129dbaf6d85SVinod Koul */ 3130dbaf6d85SVinod Koul ret = dma_set_max_seg_size(&adev->dev, 1900800); 3131dbaf6d85SVinod Koul if (ret) 3132dbaf6d85SVinod Koul dev_err(&adev->dev, "unable to set the seg size\n"); 3133dbaf6d85SVinod Koul 3134b3040e40SJassi Brar 3135b45aef3aSKatsuhiro Suzuki init_pl330_debugfs(pl330); 3136b3040e40SJassi Brar dev_info(&adev->dev, 31371f0a5cbfSLiviu Dudau "Loaded driver for PL330 DMAC-%x\n", adev->periphid); 3138b3040e40SJassi Brar dev_info(&adev->dev, 3139b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 3140f6f2421cSLars-Peter Clausen pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 3141f6f2421cSLars-Peter Clausen pcfg->num_peri, pcfg->num_events); 3142b3040e40SJassi Brar 3143ae43b328SKrzysztof Kozlowski pm_runtime_irq_safe(&adev->dev); 3144ae43b328SKrzysztof Kozlowski pm_runtime_use_autosuspend(&adev->dev); 3145ae43b328SKrzysztof Kozlowski pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); 3146ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(&adev->dev); 3147ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(&adev->dev); 3148ae43b328SKrzysztof Kozlowski 3149b3040e40SJassi Brar return 0; 31500b94c577SPadmavathi Venna probe_err3: 31510b94c577SPadmavathi Venna /* Idle the DMAC */ 3152f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 31530b94c577SPadmavathi Venna chan.device_node) { 31540b94c577SPadmavathi Venna 31550b94c577SPadmavathi Venna /* Remove the channel */ 31560b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 31570b94c577SPadmavathi Venna 31580b94c577SPadmavathi Venna /* Flush the channel */ 31590f5ebabdSKrzysztof Kozlowski if (pch->thread) { 3160740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 31610b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 31620b94c577SPadmavathi Venna } 31630f5ebabdSKrzysztof Kozlowski } 3164b3040e40SJassi Brar probe_err2: 3165f6f2421cSLars-Peter Clausen pl330_del(pl330); 3166b3040e40SJassi Brar 3167b3040e40SJassi Brar return ret; 3168b3040e40SJassi Brar } 3169b3040e40SJassi Brar 31704bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 3171b3040e40SJassi Brar { 3172f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = amba_get_drvdata(adev); 3173b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 317446cf94d6SVinod Koul int i, irq; 3175b3040e40SJassi Brar 3176ae43b328SKrzysztof Kozlowski pm_runtime_get_noresume(pl330->ddma.dev); 3177ae43b328SKrzysztof Kozlowski 31780b94c577SPadmavathi Venna if (adev->dev.of_node) 3179421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 3180421da89aSPadmavathi Venna 318146cf94d6SVinod Koul for (i = 0; i < AMBA_NR_IRQS; i++) { 318246cf94d6SVinod Koul irq = adev->irq[i]; 3183ebcdaee4SJean-Philippe Brucker if (irq) 318446cf94d6SVinod Koul devm_free_irq(&adev->dev, irq, pl330); 318546cf94d6SVinod Koul } 318646cf94d6SVinod Koul 3187f6f2421cSLars-Peter Clausen dma_async_device_unregister(&pl330->ddma); 3188b3040e40SJassi Brar 3189b3040e40SJassi Brar /* Idle the DMAC */ 3190f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 3191b3040e40SJassi Brar chan.device_node) { 3192b3040e40SJassi Brar 3193b3040e40SJassi Brar /* Remove the channel */ 3194b3040e40SJassi Brar list_del(&pch->chan.device_node); 3195b3040e40SJassi Brar 3196b3040e40SJassi Brar /* Flush the channel */ 31976e4a2a83SKrzysztof Kozlowski if (pch->thread) { 3198740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 3199b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 3200b3040e40SJassi Brar } 32016e4a2a83SKrzysztof Kozlowski } 3202b3040e40SJassi Brar 3203f6f2421cSLars-Peter Clausen pl330_del(pl330); 3204b3040e40SJassi Brar 3205b3040e40SJassi Brar return 0; 3206b3040e40SJassi Brar } 3207b3040e40SJassi Brar 3208b753351eSArvind Yadav static const struct amba_id pl330_ids[] = { 3209b3040e40SJassi Brar { 3210b3040e40SJassi Brar .id = 0x00041330, 3211b3040e40SJassi Brar .mask = 0x000fffff, 3212b3040e40SJassi Brar }, 3213b3040e40SJassi Brar { 0, 0 }, 3214b3040e40SJassi Brar }; 3215b3040e40SJassi Brar 3216e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 3217e8fa516aSDave Martin 3218b3040e40SJassi Brar static struct amba_driver pl330_driver = { 3219b3040e40SJassi Brar .drv = { 3220b3040e40SJassi Brar .owner = THIS_MODULE, 3221b3040e40SJassi Brar .name = "dma-pl330", 3222b816ccc5SKrzysztof Kozlowski .pm = &pl330_pm, 3223b3040e40SJassi Brar }, 3224b3040e40SJassi Brar .id_table = pl330_ids, 3225b3040e40SJassi Brar .probe = pl330_probe, 3226b3040e40SJassi Brar .remove = pl330_remove, 3227b3040e40SJassi Brar }; 3228b3040e40SJassi Brar 32299e5ed094Sviresh kumar module_amba_driver(pl330_driver); 3230b3040e40SJassi Brar 3231046209f6SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); 3232b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3233b3040e40SJassi Brar MODULE_LICENSE("GPL"); 3234