1 /* 2 * Topcliff PCH DMA controller driver 3 * Copyright (c) 2010 Intel Corporation 4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/init.h> 19 #include <linux/pci.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pch_dma.h> 24 25 #include "dmaengine.h" 26 27 #define DRV_NAME "pch-dma" 28 29 #define DMA_CTL0_DISABLE 0x0 30 #define DMA_CTL0_SG 0x1 31 #define DMA_CTL0_ONESHOT 0x2 32 #define DMA_CTL0_MODE_MASK_BITS 0x3 33 #define DMA_CTL0_DIR_SHIFT_BITS 2 34 #define DMA_CTL0_BITS_PER_CH 4 35 36 #define DMA_CTL2_START_SHIFT_BITS 8 37 #define DMA_CTL2_IRQ_ENABLE_MASK ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1) 38 39 #define DMA_STATUS_IDLE 0x0 40 #define DMA_STATUS_DESC_READ 0x1 41 #define DMA_STATUS_WAIT 0x2 42 #define DMA_STATUS_ACCESS 0x3 43 #define DMA_STATUS_BITS_PER_CH 2 44 #define DMA_STATUS_MASK_BITS 0x3 45 #define DMA_STATUS_SHIFT_BITS 16 46 #define DMA_STATUS_IRQ(x) (0x1 << (x)) 47 #define DMA_STATUS0_ERR(x) (0x1 << ((x) + 8)) 48 #define DMA_STATUS2_ERR(x) (0x1 << (x)) 49 50 #define DMA_DESC_WIDTH_SHIFT_BITS 12 51 #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS) 52 #define DMA_DESC_WIDTH_2_BYTES (0x2 << DMA_DESC_WIDTH_SHIFT_BITS) 53 #define DMA_DESC_WIDTH_4_BYTES (0x0 << DMA_DESC_WIDTH_SHIFT_BITS) 54 #define DMA_DESC_MAX_COUNT_1_BYTE 0x3FF 55 #define DMA_DESC_MAX_COUNT_2_BYTES 0x3FF 56 #define DMA_DESC_MAX_COUNT_4_BYTES 0x7FF 57 #define DMA_DESC_END_WITHOUT_IRQ 0x0 58 #define DMA_DESC_END_WITH_IRQ 0x1 59 #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2 60 #define DMA_DESC_FOLLOW_WITH_IRQ 0x3 61 62 #define MAX_CHAN_NR 12 63 64 #define DMA_MASK_CTL0_MODE 0x33333333 65 #define DMA_MASK_CTL2_MODE 0x00003333 66 67 static unsigned int init_nr_desc_per_channel = 64; 68 module_param(init_nr_desc_per_channel, uint, 0644); 69 MODULE_PARM_DESC(init_nr_desc_per_channel, 70 "initial descriptors per channel (default: 64)"); 71 72 struct pch_dma_desc_regs { 73 u32 dev_addr; 74 u32 mem_addr; 75 u32 size; 76 u32 next; 77 }; 78 79 struct pch_dma_regs { 80 u32 dma_ctl0; 81 u32 dma_ctl1; 82 u32 dma_ctl2; 83 u32 dma_ctl3; 84 u32 dma_sts0; 85 u32 dma_sts1; 86 u32 dma_sts2; 87 u32 reserved3; 88 struct pch_dma_desc_regs desc[MAX_CHAN_NR]; 89 }; 90 91 struct pch_dma_desc { 92 struct pch_dma_desc_regs regs; 93 struct dma_async_tx_descriptor txd; 94 struct list_head desc_node; 95 struct list_head tx_list; 96 }; 97 98 struct pch_dma_chan { 99 struct dma_chan chan; 100 void __iomem *membase; 101 enum dma_transfer_direction dir; 102 struct tasklet_struct tasklet; 103 unsigned long err_status; 104 105 spinlock_t lock; 106 107 struct list_head active_list; 108 struct list_head queue; 109 struct list_head free_list; 110 unsigned int descs_allocated; 111 }; 112 113 #define PDC_DEV_ADDR 0x00 114 #define PDC_MEM_ADDR 0x04 115 #define PDC_SIZE 0x08 116 #define PDC_NEXT 0x0C 117 118 #define channel_readl(pdc, name) \ 119 readl((pdc)->membase + PDC_##name) 120 #define channel_writel(pdc, name, val) \ 121 writel((val), (pdc)->membase + PDC_##name) 122 123 struct pch_dma { 124 struct dma_device dma; 125 void __iomem *membase; 126 struct pci_pool *pool; 127 struct pch_dma_regs regs; 128 struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR]; 129 struct pch_dma_chan channels[MAX_CHAN_NR]; 130 }; 131 132 #define PCH_DMA_CTL0 0x00 133 #define PCH_DMA_CTL1 0x04 134 #define PCH_DMA_CTL2 0x08 135 #define PCH_DMA_CTL3 0x0C 136 #define PCH_DMA_STS0 0x10 137 #define PCH_DMA_STS1 0x14 138 #define PCH_DMA_STS2 0x18 139 140 #define dma_readl(pd, name) \ 141 readl((pd)->membase + PCH_DMA_##name) 142 #define dma_writel(pd, name, val) \ 143 writel((val), (pd)->membase + PCH_DMA_##name) 144 145 static inline 146 struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd) 147 { 148 return container_of(txd, struct pch_dma_desc, txd); 149 } 150 151 static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan) 152 { 153 return container_of(chan, struct pch_dma_chan, chan); 154 } 155 156 static inline struct pch_dma *to_pd(struct dma_device *ddev) 157 { 158 return container_of(ddev, struct pch_dma, dma); 159 } 160 161 static inline struct device *chan2dev(struct dma_chan *chan) 162 { 163 return &chan->dev->device; 164 } 165 166 static inline struct device *chan2parent(struct dma_chan *chan) 167 { 168 return chan->dev->device.parent; 169 } 170 171 static inline 172 struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan) 173 { 174 return list_first_entry(&pd_chan->active_list, 175 struct pch_dma_desc, desc_node); 176 } 177 178 static inline 179 struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan) 180 { 181 return list_first_entry(&pd_chan->queue, 182 struct pch_dma_desc, desc_node); 183 } 184 185 static void pdc_enable_irq(struct dma_chan *chan, int enable) 186 { 187 struct pch_dma *pd = to_pd(chan->device); 188 u32 val; 189 int pos; 190 191 if (chan->chan_id < 8) 192 pos = chan->chan_id; 193 else 194 pos = chan->chan_id + 8; 195 196 val = dma_readl(pd, CTL2); 197 198 if (enable) 199 val |= 0x1 << pos; 200 else 201 val &= ~(0x1 << pos); 202 203 dma_writel(pd, CTL2, val); 204 205 dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n", 206 chan->chan_id, val); 207 } 208 209 static void pdc_set_dir(struct dma_chan *chan) 210 { 211 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 212 struct pch_dma *pd = to_pd(chan->device); 213 u32 val; 214 u32 mask_mode; 215 u32 mask_ctl; 216 217 if (chan->chan_id < 8) { 218 val = dma_readl(pd, CTL0); 219 220 mask_mode = DMA_CTL0_MODE_MASK_BITS << 221 (DMA_CTL0_BITS_PER_CH * chan->chan_id); 222 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 223 (DMA_CTL0_BITS_PER_CH * chan->chan_id)); 224 val &= mask_mode; 225 if (pd_chan->dir == DMA_MEM_TO_DEV) 226 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + 227 DMA_CTL0_DIR_SHIFT_BITS); 228 else 229 val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + 230 DMA_CTL0_DIR_SHIFT_BITS)); 231 232 val |= mask_ctl; 233 dma_writel(pd, CTL0, val); 234 } else { 235 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */ 236 val = dma_readl(pd, CTL3); 237 238 mask_mode = DMA_CTL0_MODE_MASK_BITS << 239 (DMA_CTL0_BITS_PER_CH * ch); 240 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 241 (DMA_CTL0_BITS_PER_CH * ch)); 242 val &= mask_mode; 243 if (pd_chan->dir == DMA_MEM_TO_DEV) 244 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch + 245 DMA_CTL0_DIR_SHIFT_BITS); 246 else 247 val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch + 248 DMA_CTL0_DIR_SHIFT_BITS)); 249 val |= mask_ctl; 250 dma_writel(pd, CTL3, val); 251 } 252 253 dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n", 254 chan->chan_id, val); 255 } 256 257 static void pdc_set_mode(struct dma_chan *chan, u32 mode) 258 { 259 struct pch_dma *pd = to_pd(chan->device); 260 u32 val; 261 u32 mask_ctl; 262 u32 mask_dir; 263 264 if (chan->chan_id < 8) { 265 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 266 (DMA_CTL0_BITS_PER_CH * chan->chan_id)); 267 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\ 268 DMA_CTL0_DIR_SHIFT_BITS); 269 val = dma_readl(pd, CTL0); 270 val &= mask_dir; 271 val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id); 272 val |= mask_ctl; 273 dma_writel(pd, CTL0, val); 274 } else { 275 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */ 276 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 277 (DMA_CTL0_BITS_PER_CH * ch)); 278 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\ 279 DMA_CTL0_DIR_SHIFT_BITS); 280 val = dma_readl(pd, CTL3); 281 val &= mask_dir; 282 val |= mode << (DMA_CTL0_BITS_PER_CH * ch); 283 val |= mask_ctl; 284 dma_writel(pd, CTL3, val); 285 } 286 287 dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n", 288 chan->chan_id, val); 289 } 290 291 static u32 pdc_get_status0(struct pch_dma_chan *pd_chan) 292 { 293 struct pch_dma *pd = to_pd(pd_chan->chan.device); 294 u32 val; 295 296 val = dma_readl(pd, STS0); 297 return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + 298 DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id)); 299 } 300 301 static u32 pdc_get_status2(struct pch_dma_chan *pd_chan) 302 { 303 struct pch_dma *pd = to_pd(pd_chan->chan.device); 304 u32 val; 305 306 val = dma_readl(pd, STS2); 307 return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + 308 DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8))); 309 } 310 311 static bool pdc_is_idle(struct pch_dma_chan *pd_chan) 312 { 313 u32 sts; 314 315 if (pd_chan->chan.chan_id < 8) 316 sts = pdc_get_status0(pd_chan); 317 else 318 sts = pdc_get_status2(pd_chan); 319 320 321 if (sts == DMA_STATUS_IDLE) 322 return true; 323 else 324 return false; 325 } 326 327 static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc) 328 { 329 if (!pdc_is_idle(pd_chan)) { 330 dev_err(chan2dev(&pd_chan->chan), 331 "BUG: Attempt to start non-idle channel\n"); 332 return; 333 } 334 335 dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n", 336 pd_chan->chan.chan_id, desc->regs.dev_addr); 337 dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n", 338 pd_chan->chan.chan_id, desc->regs.mem_addr); 339 dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n", 340 pd_chan->chan.chan_id, desc->regs.size); 341 dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n", 342 pd_chan->chan.chan_id, desc->regs.next); 343 344 if (list_empty(&desc->tx_list)) { 345 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr); 346 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr); 347 channel_writel(pd_chan, SIZE, desc->regs.size); 348 channel_writel(pd_chan, NEXT, desc->regs.next); 349 pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT); 350 } else { 351 channel_writel(pd_chan, NEXT, desc->txd.phys); 352 pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG); 353 } 354 } 355 356 static void pdc_chain_complete(struct pch_dma_chan *pd_chan, 357 struct pch_dma_desc *desc) 358 { 359 struct dma_async_tx_descriptor *txd = &desc->txd; 360 struct dmaengine_desc_callback cb; 361 362 dmaengine_desc_get_callback(txd, &cb); 363 list_splice_init(&desc->tx_list, &pd_chan->free_list); 364 list_move(&desc->desc_node, &pd_chan->free_list); 365 366 dmaengine_desc_callback_invoke(&cb, NULL); 367 } 368 369 static void pdc_complete_all(struct pch_dma_chan *pd_chan) 370 { 371 struct pch_dma_desc *desc, *_d; 372 LIST_HEAD(list); 373 374 BUG_ON(!pdc_is_idle(pd_chan)); 375 376 if (!list_empty(&pd_chan->queue)) 377 pdc_dostart(pd_chan, pdc_first_queued(pd_chan)); 378 379 list_splice_init(&pd_chan->active_list, &list); 380 list_splice_init(&pd_chan->queue, &pd_chan->active_list); 381 382 list_for_each_entry_safe(desc, _d, &list, desc_node) 383 pdc_chain_complete(pd_chan, desc); 384 } 385 386 static void pdc_handle_error(struct pch_dma_chan *pd_chan) 387 { 388 struct pch_dma_desc *bad_desc; 389 390 bad_desc = pdc_first_active(pd_chan); 391 list_del(&bad_desc->desc_node); 392 393 list_splice_init(&pd_chan->queue, pd_chan->active_list.prev); 394 395 if (!list_empty(&pd_chan->active_list)) 396 pdc_dostart(pd_chan, pdc_first_active(pd_chan)); 397 398 dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n"); 399 dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n", 400 bad_desc->txd.cookie); 401 402 pdc_chain_complete(pd_chan, bad_desc); 403 } 404 405 static void pdc_advance_work(struct pch_dma_chan *pd_chan) 406 { 407 if (list_empty(&pd_chan->active_list) || 408 list_is_singular(&pd_chan->active_list)) { 409 pdc_complete_all(pd_chan); 410 } else { 411 pdc_chain_complete(pd_chan, pdc_first_active(pd_chan)); 412 pdc_dostart(pd_chan, pdc_first_active(pd_chan)); 413 } 414 } 415 416 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd) 417 { 418 struct pch_dma_desc *desc = to_pd_desc(txd); 419 struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan); 420 421 spin_lock(&pd_chan->lock); 422 423 if (list_empty(&pd_chan->active_list)) { 424 list_add_tail(&desc->desc_node, &pd_chan->active_list); 425 pdc_dostart(pd_chan, desc); 426 } else { 427 list_add_tail(&desc->desc_node, &pd_chan->queue); 428 } 429 430 spin_unlock(&pd_chan->lock); 431 return 0; 432 } 433 434 static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags) 435 { 436 struct pch_dma_desc *desc = NULL; 437 struct pch_dma *pd = to_pd(chan->device); 438 dma_addr_t addr; 439 440 desc = pci_pool_zalloc(pd->pool, flags, &addr); 441 if (desc) { 442 INIT_LIST_HEAD(&desc->tx_list); 443 dma_async_tx_descriptor_init(&desc->txd, chan); 444 desc->txd.tx_submit = pd_tx_submit; 445 desc->txd.flags = DMA_CTRL_ACK; 446 desc->txd.phys = addr; 447 } 448 449 return desc; 450 } 451 452 static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan) 453 { 454 struct pch_dma_desc *desc, *_d; 455 struct pch_dma_desc *ret = NULL; 456 int i = 0; 457 458 spin_lock(&pd_chan->lock); 459 list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) { 460 i++; 461 if (async_tx_test_ack(&desc->txd)) { 462 list_del(&desc->desc_node); 463 ret = desc; 464 break; 465 } 466 dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc); 467 } 468 spin_unlock(&pd_chan->lock); 469 dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i); 470 471 if (!ret) { 472 ret = pdc_alloc_desc(&pd_chan->chan, GFP_ATOMIC); 473 if (ret) { 474 spin_lock(&pd_chan->lock); 475 pd_chan->descs_allocated++; 476 spin_unlock(&pd_chan->lock); 477 } else { 478 dev_err(chan2dev(&pd_chan->chan), 479 "failed to alloc desc\n"); 480 } 481 } 482 483 return ret; 484 } 485 486 static void pdc_desc_put(struct pch_dma_chan *pd_chan, 487 struct pch_dma_desc *desc) 488 { 489 if (desc) { 490 spin_lock(&pd_chan->lock); 491 list_splice_init(&desc->tx_list, &pd_chan->free_list); 492 list_add(&desc->desc_node, &pd_chan->free_list); 493 spin_unlock(&pd_chan->lock); 494 } 495 } 496 497 static int pd_alloc_chan_resources(struct dma_chan *chan) 498 { 499 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 500 struct pch_dma_desc *desc; 501 LIST_HEAD(tmp_list); 502 int i; 503 504 if (!pdc_is_idle(pd_chan)) { 505 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 506 return -EIO; 507 } 508 509 if (!list_empty(&pd_chan->free_list)) 510 return pd_chan->descs_allocated; 511 512 for (i = 0; i < init_nr_desc_per_channel; i++) { 513 desc = pdc_alloc_desc(chan, GFP_KERNEL); 514 515 if (!desc) { 516 dev_warn(chan2dev(chan), 517 "Only allocated %d initial descriptors\n", i); 518 break; 519 } 520 521 list_add_tail(&desc->desc_node, &tmp_list); 522 } 523 524 spin_lock_irq(&pd_chan->lock); 525 list_splice(&tmp_list, &pd_chan->free_list); 526 pd_chan->descs_allocated = i; 527 dma_cookie_init(chan); 528 spin_unlock_irq(&pd_chan->lock); 529 530 pdc_enable_irq(chan, 1); 531 532 return pd_chan->descs_allocated; 533 } 534 535 static void pd_free_chan_resources(struct dma_chan *chan) 536 { 537 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 538 struct pch_dma *pd = to_pd(chan->device); 539 struct pch_dma_desc *desc, *_d; 540 LIST_HEAD(tmp_list); 541 542 BUG_ON(!pdc_is_idle(pd_chan)); 543 BUG_ON(!list_empty(&pd_chan->active_list)); 544 BUG_ON(!list_empty(&pd_chan->queue)); 545 546 spin_lock_irq(&pd_chan->lock); 547 list_splice_init(&pd_chan->free_list, &tmp_list); 548 pd_chan->descs_allocated = 0; 549 spin_unlock_irq(&pd_chan->lock); 550 551 list_for_each_entry_safe(desc, _d, &tmp_list, desc_node) 552 pci_pool_free(pd->pool, desc, desc->txd.phys); 553 554 pdc_enable_irq(chan, 0); 555 } 556 557 static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 558 struct dma_tx_state *txstate) 559 { 560 return dma_cookie_status(chan, cookie, txstate); 561 } 562 563 static void pd_issue_pending(struct dma_chan *chan) 564 { 565 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 566 567 if (pdc_is_idle(pd_chan)) { 568 spin_lock(&pd_chan->lock); 569 pdc_advance_work(pd_chan); 570 spin_unlock(&pd_chan->lock); 571 } 572 } 573 574 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, 575 struct scatterlist *sgl, unsigned int sg_len, 576 enum dma_transfer_direction direction, unsigned long flags, 577 void *context) 578 { 579 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 580 struct pch_dma_slave *pd_slave = chan->private; 581 struct pch_dma_desc *first = NULL; 582 struct pch_dma_desc *prev = NULL; 583 struct pch_dma_desc *desc = NULL; 584 struct scatterlist *sg; 585 dma_addr_t reg; 586 int i; 587 588 if (unlikely(!sg_len)) { 589 dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n"); 590 return NULL; 591 } 592 593 if (direction == DMA_DEV_TO_MEM) 594 reg = pd_slave->rx_reg; 595 else if (direction == DMA_MEM_TO_DEV) 596 reg = pd_slave->tx_reg; 597 else 598 return NULL; 599 600 pd_chan->dir = direction; 601 pdc_set_dir(chan); 602 603 for_each_sg(sgl, sg, sg_len, i) { 604 desc = pdc_desc_get(pd_chan); 605 606 if (!desc) 607 goto err_desc_get; 608 609 desc->regs.dev_addr = reg; 610 desc->regs.mem_addr = sg_dma_address(sg); 611 desc->regs.size = sg_dma_len(sg); 612 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ; 613 614 switch (pd_slave->width) { 615 case PCH_DMA_WIDTH_1_BYTE: 616 if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE) 617 goto err_desc_get; 618 desc->regs.size |= DMA_DESC_WIDTH_1_BYTE; 619 break; 620 case PCH_DMA_WIDTH_2_BYTES: 621 if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES) 622 goto err_desc_get; 623 desc->regs.size |= DMA_DESC_WIDTH_2_BYTES; 624 break; 625 case PCH_DMA_WIDTH_4_BYTES: 626 if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES) 627 goto err_desc_get; 628 desc->regs.size |= DMA_DESC_WIDTH_4_BYTES; 629 break; 630 default: 631 goto err_desc_get; 632 } 633 634 if (!first) { 635 first = desc; 636 } else { 637 prev->regs.next |= desc->txd.phys; 638 list_add_tail(&desc->desc_node, &first->tx_list); 639 } 640 641 prev = desc; 642 } 643 644 if (flags & DMA_PREP_INTERRUPT) 645 desc->regs.next = DMA_DESC_END_WITH_IRQ; 646 else 647 desc->regs.next = DMA_DESC_END_WITHOUT_IRQ; 648 649 first->txd.cookie = -EBUSY; 650 desc->txd.flags = flags; 651 652 return &first->txd; 653 654 err_desc_get: 655 dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n"); 656 pdc_desc_put(pd_chan, first); 657 return NULL; 658 } 659 660 static int pd_device_terminate_all(struct dma_chan *chan) 661 { 662 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 663 struct pch_dma_desc *desc, *_d; 664 LIST_HEAD(list); 665 666 spin_lock_irq(&pd_chan->lock); 667 668 pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE); 669 670 list_splice_init(&pd_chan->active_list, &list); 671 list_splice_init(&pd_chan->queue, &list); 672 673 list_for_each_entry_safe(desc, _d, &list, desc_node) 674 pdc_chain_complete(pd_chan, desc); 675 676 spin_unlock_irq(&pd_chan->lock); 677 678 return 0; 679 } 680 681 static void pdc_tasklet(unsigned long data) 682 { 683 struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data; 684 unsigned long flags; 685 686 if (!pdc_is_idle(pd_chan)) { 687 dev_err(chan2dev(&pd_chan->chan), 688 "BUG: handle non-idle channel in tasklet\n"); 689 return; 690 } 691 692 spin_lock_irqsave(&pd_chan->lock, flags); 693 if (test_and_clear_bit(0, &pd_chan->err_status)) 694 pdc_handle_error(pd_chan); 695 else 696 pdc_advance_work(pd_chan); 697 spin_unlock_irqrestore(&pd_chan->lock, flags); 698 } 699 700 static irqreturn_t pd_irq(int irq, void *devid) 701 { 702 struct pch_dma *pd = (struct pch_dma *)devid; 703 struct pch_dma_chan *pd_chan; 704 u32 sts0; 705 u32 sts2; 706 int i; 707 int ret0 = IRQ_NONE; 708 int ret2 = IRQ_NONE; 709 710 sts0 = dma_readl(pd, STS0); 711 sts2 = dma_readl(pd, STS2); 712 713 dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0); 714 715 for (i = 0; i < pd->dma.chancnt; i++) { 716 pd_chan = &pd->channels[i]; 717 718 if (i < 8) { 719 if (sts0 & DMA_STATUS_IRQ(i)) { 720 if (sts0 & DMA_STATUS0_ERR(i)) 721 set_bit(0, &pd_chan->err_status); 722 723 tasklet_schedule(&pd_chan->tasklet); 724 ret0 = IRQ_HANDLED; 725 } 726 } else { 727 if (sts2 & DMA_STATUS_IRQ(i - 8)) { 728 if (sts2 & DMA_STATUS2_ERR(i)) 729 set_bit(0, &pd_chan->err_status); 730 731 tasklet_schedule(&pd_chan->tasklet); 732 ret2 = IRQ_HANDLED; 733 } 734 } 735 } 736 737 /* clear interrupt bits in status register */ 738 if (ret0) 739 dma_writel(pd, STS0, sts0); 740 if (ret2) 741 dma_writel(pd, STS2, sts2); 742 743 return ret0 | ret2; 744 } 745 746 #ifdef CONFIG_PM 747 static void pch_dma_save_regs(struct pch_dma *pd) 748 { 749 struct pch_dma_chan *pd_chan; 750 struct dma_chan *chan, *_c; 751 int i = 0; 752 753 pd->regs.dma_ctl0 = dma_readl(pd, CTL0); 754 pd->regs.dma_ctl1 = dma_readl(pd, CTL1); 755 pd->regs.dma_ctl2 = dma_readl(pd, CTL2); 756 pd->regs.dma_ctl3 = dma_readl(pd, CTL3); 757 758 list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { 759 pd_chan = to_pd_chan(chan); 760 761 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); 762 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); 763 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); 764 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT); 765 766 i++; 767 } 768 } 769 770 static void pch_dma_restore_regs(struct pch_dma *pd) 771 { 772 struct pch_dma_chan *pd_chan; 773 struct dma_chan *chan, *_c; 774 int i = 0; 775 776 dma_writel(pd, CTL0, pd->regs.dma_ctl0); 777 dma_writel(pd, CTL1, pd->regs.dma_ctl1); 778 dma_writel(pd, CTL2, pd->regs.dma_ctl2); 779 dma_writel(pd, CTL3, pd->regs.dma_ctl3); 780 781 list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { 782 pd_chan = to_pd_chan(chan); 783 784 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); 785 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); 786 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); 787 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); 788 789 i++; 790 } 791 } 792 793 static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state) 794 { 795 struct pch_dma *pd = pci_get_drvdata(pdev); 796 797 if (pd) 798 pch_dma_save_regs(pd); 799 800 pci_save_state(pdev); 801 pci_disable_device(pdev); 802 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 803 804 return 0; 805 } 806 807 static int pch_dma_resume(struct pci_dev *pdev) 808 { 809 struct pch_dma *pd = pci_get_drvdata(pdev); 810 int err; 811 812 pci_set_power_state(pdev, PCI_D0); 813 pci_restore_state(pdev); 814 815 err = pci_enable_device(pdev); 816 if (err) { 817 dev_dbg(&pdev->dev, "failed to enable device\n"); 818 return err; 819 } 820 821 if (pd) 822 pch_dma_restore_regs(pd); 823 824 return 0; 825 } 826 #endif 827 828 static int pch_dma_probe(struct pci_dev *pdev, 829 const struct pci_device_id *id) 830 { 831 struct pch_dma *pd; 832 struct pch_dma_regs *regs; 833 unsigned int nr_channels; 834 int err; 835 int i; 836 837 nr_channels = id->driver_data; 838 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 839 if (!pd) 840 return -ENOMEM; 841 842 pci_set_drvdata(pdev, pd); 843 844 err = pci_enable_device(pdev); 845 if (err) { 846 dev_err(&pdev->dev, "Cannot enable PCI device\n"); 847 goto err_free_mem; 848 } 849 850 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 851 dev_err(&pdev->dev, "Cannot find proper base address\n"); 852 err = -ENODEV; 853 goto err_disable_pdev; 854 } 855 856 err = pci_request_regions(pdev, DRV_NAME); 857 if (err) { 858 dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); 859 goto err_disable_pdev; 860 } 861 862 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 863 if (err) { 864 dev_err(&pdev->dev, "Cannot set proper DMA config\n"); 865 goto err_free_res; 866 } 867 868 regs = pd->membase = pci_iomap(pdev, 1, 0); 869 if (!pd->membase) { 870 dev_err(&pdev->dev, "Cannot map MMIO registers\n"); 871 err = -ENOMEM; 872 goto err_free_res; 873 } 874 875 pci_set_master(pdev); 876 877 err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd); 878 if (err) { 879 dev_err(&pdev->dev, "Failed to request IRQ\n"); 880 goto err_iounmap; 881 } 882 883 pd->pool = pci_pool_create("pch_dma_desc_pool", pdev, 884 sizeof(struct pch_dma_desc), 4, 0); 885 if (!pd->pool) { 886 dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n"); 887 err = -ENOMEM; 888 goto err_free_irq; 889 } 890 891 pd->dma.dev = &pdev->dev; 892 893 INIT_LIST_HEAD(&pd->dma.channels); 894 895 for (i = 0; i < nr_channels; i++) { 896 struct pch_dma_chan *pd_chan = &pd->channels[i]; 897 898 pd_chan->chan.device = &pd->dma; 899 dma_cookie_init(&pd_chan->chan); 900 901 pd_chan->membase = ®s->desc[i]; 902 903 spin_lock_init(&pd_chan->lock); 904 905 INIT_LIST_HEAD(&pd_chan->active_list); 906 INIT_LIST_HEAD(&pd_chan->queue); 907 INIT_LIST_HEAD(&pd_chan->free_list); 908 909 tasklet_init(&pd_chan->tasklet, pdc_tasklet, 910 (unsigned long)pd_chan); 911 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels); 912 } 913 914 dma_cap_zero(pd->dma.cap_mask); 915 dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask); 916 dma_cap_set(DMA_SLAVE, pd->dma.cap_mask); 917 918 pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources; 919 pd->dma.device_free_chan_resources = pd_free_chan_resources; 920 pd->dma.device_tx_status = pd_tx_status; 921 pd->dma.device_issue_pending = pd_issue_pending; 922 pd->dma.device_prep_slave_sg = pd_prep_slave_sg; 923 pd->dma.device_terminate_all = pd_device_terminate_all; 924 925 err = dma_async_device_register(&pd->dma); 926 if (err) { 927 dev_err(&pdev->dev, "Failed to register DMA device\n"); 928 goto err_free_pool; 929 } 930 931 return 0; 932 933 err_free_pool: 934 pci_pool_destroy(pd->pool); 935 err_free_irq: 936 free_irq(pdev->irq, pd); 937 err_iounmap: 938 pci_iounmap(pdev, pd->membase); 939 err_free_res: 940 pci_release_regions(pdev); 941 err_disable_pdev: 942 pci_disable_device(pdev); 943 err_free_mem: 944 kfree(pd); 945 return err; 946 } 947 948 static void pch_dma_remove(struct pci_dev *pdev) 949 { 950 struct pch_dma *pd = pci_get_drvdata(pdev); 951 struct pch_dma_chan *pd_chan; 952 struct dma_chan *chan, *_c; 953 954 if (pd) { 955 dma_async_device_unregister(&pd->dma); 956 957 free_irq(pdev->irq, pd); 958 959 list_for_each_entry_safe(chan, _c, &pd->dma.channels, 960 device_node) { 961 pd_chan = to_pd_chan(chan); 962 963 tasklet_kill(&pd_chan->tasklet); 964 } 965 966 pci_pool_destroy(pd->pool); 967 pci_iounmap(pdev, pd->membase); 968 pci_release_regions(pdev); 969 pci_disable_device(pdev); 970 kfree(pd); 971 } 972 } 973 974 /* PCI Device ID of DMA device */ 975 #define PCI_VENDOR_ID_ROHM 0x10DB 976 #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810 977 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815 978 #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026 979 #define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B 980 #define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034 981 #define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032 982 #define PCI_DEVICE_ID_ML7223_DMA1_4CH 0x800B 983 #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E 984 #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017 985 #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B 986 #define PCI_DEVICE_ID_ML7831_DMA1_8CH 0x8810 987 #define PCI_DEVICE_ID_ML7831_DMA2_4CH 0x8815 988 989 static const struct pci_device_id pch_dma_id_table[] = { 990 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 }, 991 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 }, 992 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */ 993 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */ 994 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */ 995 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */ 996 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */ 997 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */ 998 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */ 999 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */ 1000 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */ 1001 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */ 1002 { 0, }, 1003 }; 1004 1005 static struct pci_driver pch_dma_driver = { 1006 .name = DRV_NAME, 1007 .id_table = pch_dma_id_table, 1008 .probe = pch_dma_probe, 1009 .remove = pch_dma_remove, 1010 #ifdef CONFIG_PM 1011 .suspend = pch_dma_suspend, 1012 .resume = pch_dma_resume, 1013 #endif 1014 }; 1015 1016 module_pci_driver(pch_dma_driver); 1017 1018 MODULE_DESCRIPTION("Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH " 1019 "DMA controller driver"); 1020 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>"); 1021 MODULE_LICENSE("GPL v2"); 1022 MODULE_DEVICE_TABLE(pci, pch_dma_id_table); 1023