1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 4 // 5 // Refer to drivers/dma/imx-sdma.c 6 7 #include <linux/init.h> 8 #include <linux/types.h> 9 #include <linux/mm.h> 10 #include <linux/interrupt.h> 11 #include <linux/clk.h> 12 #include <linux/wait.h> 13 #include <linux/sched.h> 14 #include <linux/semaphore.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/slab.h> 18 #include <linux/platform_device.h> 19 #include <linux/dmaengine.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/stmp_device.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_dma.h> 26 #include <linux/list.h> 27 #include <linux/dma/mxs-dma.h> 28 29 #include <asm/irq.h> 30 31 #include "dmaengine.h" 32 33 /* 34 * NOTE: The term "PIO" throughout the mxs-dma implementation means 35 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 36 * dma can program the controller registers of peripheral devices. 37 */ 38 39 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) 40 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) 41 42 #define HW_APBHX_CTRL0 0x000 43 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 44 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 45 #define BP_APBH_CTRL0_RESET_CHANNEL 16 46 #define HW_APBHX_CTRL1 0x010 47 #define HW_APBHX_CTRL2 0x020 48 #define HW_APBHX_CHANNEL_CTRL 0x030 49 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 50 /* 51 * The offset of NXTCMDAR register is different per both dma type and version, 52 * while stride for each channel is all the same 0x70. 53 */ 54 #define HW_APBHX_CHn_NXTCMDAR(d, n) \ 55 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) 56 #define HW_APBHX_CHn_SEMA(d, n) \ 57 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) 58 #define HW_APBHX_CHn_BAR(d, n) \ 59 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70) 60 #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70) 61 62 /* 63 * ccw bits definitions 64 * 65 * COMMAND: 0..1 (2) 66 * CHAIN: 2 (1) 67 * IRQ: 3 (1) 68 * NAND_LOCK: 4 (1) - not implemented 69 * NAND_WAIT4READY: 5 (1) - not implemented 70 * DEC_SEM: 6 (1) 71 * WAIT4END: 7 (1) 72 * HALT_ON_TERMINATE: 8 (1) 73 * TERMINATE_FLUSH: 9 (1) 74 * RESERVED: 10..11 (2) 75 * PIO_NUM: 12..15 (4) 76 */ 77 #define BP_CCW_COMMAND 0 78 #define BM_CCW_COMMAND (3 << 0) 79 #define CCW_CHAIN (1 << 2) 80 #define CCW_IRQ (1 << 3) 81 #define CCW_WAIT4RDY (1 << 5) 82 #define CCW_DEC_SEM (1 << 6) 83 #define CCW_WAIT4END (1 << 7) 84 #define CCW_HALT_ON_TERM (1 << 8) 85 #define CCW_TERM_FLUSH (1 << 9) 86 #define BP_CCW_PIO_NUM 12 87 #define BM_CCW_PIO_NUM (0xf << 12) 88 89 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 90 91 #define MXS_DMA_CMD_NO_XFER 0 92 #define MXS_DMA_CMD_WRITE 1 93 #define MXS_DMA_CMD_READ 2 94 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 95 96 struct mxs_dma_ccw { 97 u32 next; 98 u16 bits; 99 u16 xfer_bytes; 100 #define MAX_XFER_BYTES 0xff00 101 u32 bufaddr; 102 #define MXS_PIO_WORDS 16 103 u32 pio_words[MXS_PIO_WORDS]; 104 }; 105 106 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE) 107 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw)) 108 109 struct mxs_dma_chan { 110 struct mxs_dma_engine *mxs_dma; 111 struct dma_chan chan; 112 struct dma_async_tx_descriptor desc; 113 struct tasklet_struct tasklet; 114 unsigned int chan_irq; 115 struct mxs_dma_ccw *ccw; 116 dma_addr_t ccw_phys; 117 int desc_count; 118 enum dma_status status; 119 unsigned int flags; 120 bool reset; 121 #define MXS_DMA_SG_LOOP (1 << 0) 122 #define MXS_DMA_USE_SEMAPHORE (1 << 1) 123 }; 124 125 #define MXS_DMA_CHANNELS 16 126 #define MXS_DMA_CHANNELS_MASK 0xffff 127 128 enum mxs_dma_devtype { 129 MXS_DMA_APBH, 130 MXS_DMA_APBX, 131 }; 132 133 enum mxs_dma_id { 134 IMX23_DMA, 135 IMX28_DMA, 136 }; 137 138 struct mxs_dma_engine { 139 enum mxs_dma_id dev_id; 140 enum mxs_dma_devtype type; 141 void __iomem *base; 142 struct clk *clk; 143 struct dma_device dma_device; 144 struct device_dma_parameters dma_parms; 145 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 146 struct platform_device *pdev; 147 unsigned int nr_channels; 148 }; 149 150 struct mxs_dma_type { 151 enum mxs_dma_id id; 152 enum mxs_dma_devtype type; 153 }; 154 155 static struct mxs_dma_type mxs_dma_types[] = { 156 { 157 .id = IMX23_DMA, 158 .type = MXS_DMA_APBH, 159 }, { 160 .id = IMX23_DMA, 161 .type = MXS_DMA_APBX, 162 }, { 163 .id = IMX28_DMA, 164 .type = MXS_DMA_APBH, 165 }, { 166 .id = IMX28_DMA, 167 .type = MXS_DMA_APBX, 168 } 169 }; 170 171 static const struct platform_device_id mxs_dma_ids[] = { 172 { 173 .name = "imx23-dma-apbh", 174 .driver_data = (kernel_ulong_t) &mxs_dma_types[0], 175 }, { 176 .name = "imx23-dma-apbx", 177 .driver_data = (kernel_ulong_t) &mxs_dma_types[1], 178 }, { 179 .name = "imx28-dma-apbh", 180 .driver_data = (kernel_ulong_t) &mxs_dma_types[2], 181 }, { 182 .name = "imx28-dma-apbx", 183 .driver_data = (kernel_ulong_t) &mxs_dma_types[3], 184 }, { 185 /* end of list */ 186 } 187 }; 188 189 static const struct of_device_id mxs_dma_dt_ids[] = { 190 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], }, 191 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, 192 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, 193 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, 194 { /* sentinel */ } 195 }; 196 MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); 197 198 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 199 { 200 return container_of(chan, struct mxs_dma_chan, chan); 201 } 202 203 static void mxs_dma_reset_chan(struct dma_chan *chan) 204 { 205 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 206 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 207 int chan_id = mxs_chan->chan.chan_id; 208 209 /* 210 * mxs dma channel resets can cause a channel stall. To recover from a 211 * channel stall, we have to reset the whole DMA engine. To avoid this, 212 * we use cyclic DMA with semaphores, that are enhanced in 213 * mxs_dma_int_handler. To reset the channel, we can simply stop writing 214 * into the semaphore counter. 215 */ 216 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 217 mxs_chan->flags & MXS_DMA_SG_LOOP) { 218 mxs_chan->reset = true; 219 } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) { 220 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 221 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 222 } else { 223 unsigned long elapsed = 0; 224 const unsigned long max_wait = 50000; /* 50ms */ 225 void __iomem *reg_dbg1 = mxs_dma->base + 226 HW_APBX_CHn_DEBUG1(mxs_dma, chan_id); 227 228 /* 229 * On i.MX28 APBX, the DMA channel can stop working if we reset 230 * the channel while it is in READ_FLUSH (0x08) state. 231 * We wait here until we leave the state. Then we trigger the 232 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash 233 * because of this. 234 */ 235 while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) { 236 udelay(100); 237 elapsed += 100; 238 } 239 240 if (elapsed >= max_wait) 241 dev_err(&mxs_chan->mxs_dma->pdev->dev, 242 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n", 243 chan_id); 244 245 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 246 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 247 } 248 249 mxs_chan->status = DMA_COMPLETE; 250 } 251 252 static void mxs_dma_enable_chan(struct dma_chan *chan) 253 { 254 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 255 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 256 int chan_id = mxs_chan->chan.chan_id; 257 258 /* set cmd_addr up */ 259 writel(mxs_chan->ccw_phys, 260 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); 261 262 /* write 1 to SEMA to kick off the channel */ 263 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 264 mxs_chan->flags & MXS_DMA_SG_LOOP) { 265 /* A cyclic DMA consists of at least 2 segments, so initialize 266 * the semaphore with 2 so we have enough time to add 1 to the 267 * semaphore if we need to */ 268 writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 269 } else { 270 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 271 } 272 mxs_chan->reset = false; 273 } 274 275 static void mxs_dma_disable_chan(struct dma_chan *chan) 276 { 277 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 278 279 mxs_chan->status = DMA_COMPLETE; 280 } 281 282 static int mxs_dma_pause_chan(struct dma_chan *chan) 283 { 284 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 285 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 286 int chan_id = mxs_chan->chan.chan_id; 287 288 /* freeze the channel */ 289 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 290 writel(1 << chan_id, 291 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 292 else 293 writel(1 << chan_id, 294 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 295 296 mxs_chan->status = DMA_PAUSED; 297 return 0; 298 } 299 300 static int mxs_dma_resume_chan(struct dma_chan *chan) 301 { 302 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 303 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 304 int chan_id = mxs_chan->chan.chan_id; 305 306 /* unfreeze the channel */ 307 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 308 writel(1 << chan_id, 309 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); 310 else 311 writel(1 << chan_id, 312 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); 313 314 mxs_chan->status = DMA_IN_PROGRESS; 315 return 0; 316 } 317 318 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 319 { 320 return dma_cookie_assign(tx); 321 } 322 323 static void mxs_dma_tasklet(unsigned long data) 324 { 325 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 326 327 dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL); 328 } 329 330 static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq) 331 { 332 int i; 333 334 for (i = 0; i != mxs_dma->nr_channels; ++i) 335 if (mxs_dma->mxs_chans[i].chan_irq == irq) 336 return i; 337 338 return -EINVAL; 339 } 340 341 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 342 { 343 struct mxs_dma_engine *mxs_dma = dev_id; 344 struct mxs_dma_chan *mxs_chan; 345 u32 completed; 346 u32 err; 347 int chan = mxs_dma_irq_to_chan(mxs_dma, irq); 348 349 if (chan < 0) 350 return IRQ_NONE; 351 352 /* completion status */ 353 completed = readl(mxs_dma->base + HW_APBHX_CTRL1); 354 completed = (completed >> chan) & 0x1; 355 356 /* Clear interrupt */ 357 writel((1 << chan), 358 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); 359 360 /* error status */ 361 err = readl(mxs_dma->base + HW_APBHX_CTRL2); 362 err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan); 363 364 /* 365 * error status bit is in the upper 16 bits, error irq bit in the lower 366 * 16 bits. We transform it into a simpler error code: 367 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR 368 */ 369 err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan); 370 371 /* Clear error irq */ 372 writel((1 << chan), 373 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); 374 375 /* 376 * When both completion and error of termination bits set at the 377 * same time, we do not take it as an error. IOW, it only becomes 378 * an error we need to handle here in case of either it's a bus 379 * error or a termination error with no completion. 0x01 is termination 380 * error, so we can subtract err & completed to get the real error case. 381 */ 382 err -= err & completed; 383 384 mxs_chan = &mxs_dma->mxs_chans[chan]; 385 386 if (err) { 387 dev_dbg(mxs_dma->dma_device.dev, 388 "%s: error in channel %d\n", __func__, 389 chan); 390 mxs_chan->status = DMA_ERROR; 391 mxs_dma_reset_chan(&mxs_chan->chan); 392 } else if (mxs_chan->status != DMA_COMPLETE) { 393 if (mxs_chan->flags & MXS_DMA_SG_LOOP) { 394 mxs_chan->status = DMA_IN_PROGRESS; 395 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE) 396 writel(1, mxs_dma->base + 397 HW_APBHX_CHn_SEMA(mxs_dma, chan)); 398 } else { 399 mxs_chan->status = DMA_COMPLETE; 400 } 401 } 402 403 if (mxs_chan->status == DMA_COMPLETE) { 404 if (mxs_chan->reset) 405 return IRQ_HANDLED; 406 dma_cookie_complete(&mxs_chan->desc); 407 } 408 409 /* schedule tasklet on this channel */ 410 tasklet_schedule(&mxs_chan->tasklet); 411 412 return IRQ_HANDLED; 413 } 414 415 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 416 { 417 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 418 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 419 int ret; 420 421 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, 422 CCW_BLOCK_SIZE, 423 &mxs_chan->ccw_phys, GFP_KERNEL); 424 if (!mxs_chan->ccw) { 425 ret = -ENOMEM; 426 goto err_alloc; 427 } 428 429 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 430 0, "mxs-dma", mxs_dma); 431 if (ret) 432 goto err_irq; 433 434 ret = clk_prepare_enable(mxs_dma->clk); 435 if (ret) 436 goto err_clk; 437 438 mxs_dma_reset_chan(chan); 439 440 dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 441 mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 442 443 /* the descriptor is ready */ 444 async_tx_ack(&mxs_chan->desc); 445 446 return 0; 447 448 err_clk: 449 free_irq(mxs_chan->chan_irq, mxs_dma); 450 err_irq: 451 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 452 mxs_chan->ccw, mxs_chan->ccw_phys); 453 err_alloc: 454 return ret; 455 } 456 457 static void mxs_dma_free_chan_resources(struct dma_chan *chan) 458 { 459 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 460 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 461 462 mxs_dma_disable_chan(chan); 463 464 free_irq(mxs_chan->chan_irq, mxs_dma); 465 466 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 467 mxs_chan->ccw, mxs_chan->ccw_phys); 468 469 clk_disable_unprepare(mxs_dma->clk); 470 } 471 472 /* 473 * How to use the flags for ->device_prep_slave_sg() : 474 * [1] If there is only one DMA command in the DMA chain, the code should be: 475 * ...... 476 * ->device_prep_slave_sg(DMA_CTRL_ACK); 477 * ...... 478 * [2] If there are two DMA commands in the DMA chain, the code should be 479 * ...... 480 * ->device_prep_slave_sg(0); 481 * ...... 482 * ->device_prep_slave_sg(DMA_CTRL_ACK); 483 * ...... 484 * [3] If there are more than two DMA commands in the DMA chain, the code 485 * should be: 486 * ...... 487 * ->device_prep_slave_sg(0); // First 488 * ...... 489 * ->device_prep_slave_sg(DMA_CTRL_ACK]); 490 * ...... 491 * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last 492 * ...... 493 */ 494 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 495 struct dma_chan *chan, struct scatterlist *sgl, 496 unsigned int sg_len, enum dma_transfer_direction direction, 497 unsigned long flags, void *context) 498 { 499 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 500 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 501 struct mxs_dma_ccw *ccw; 502 struct scatterlist *sg; 503 u32 i, j; 504 u32 *pio; 505 int idx = 0; 506 507 if (mxs_chan->status == DMA_IN_PROGRESS) 508 idx = mxs_chan->desc_count; 509 510 if (sg_len + idx > NUM_CCW) { 511 dev_err(mxs_dma->dma_device.dev, 512 "maximum number of sg exceeded: %d > %d\n", 513 sg_len, NUM_CCW); 514 goto err_out; 515 } 516 517 mxs_chan->status = DMA_IN_PROGRESS; 518 mxs_chan->flags = 0; 519 520 /* 521 * If the sg is prepared with append flag set, the sg 522 * will be appended to the last prepared sg. 523 */ 524 if (idx) { 525 BUG_ON(idx < 1); 526 ccw = &mxs_chan->ccw[idx - 1]; 527 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 528 ccw->bits |= CCW_CHAIN; 529 ccw->bits &= ~CCW_IRQ; 530 ccw->bits &= ~CCW_DEC_SEM; 531 } else { 532 idx = 0; 533 } 534 535 if (direction == DMA_TRANS_NONE) { 536 ccw = &mxs_chan->ccw[idx++]; 537 pio = (u32 *) sgl; 538 539 for (j = 0; j < sg_len;) 540 ccw->pio_words[j++] = *pio++; 541 542 ccw->bits = 0; 543 ccw->bits |= CCW_IRQ; 544 ccw->bits |= CCW_DEC_SEM; 545 if (flags & MXS_DMA_CTRL_WAIT4END) 546 ccw->bits |= CCW_WAIT4END; 547 ccw->bits |= CCW_HALT_ON_TERM; 548 ccw->bits |= CCW_TERM_FLUSH; 549 ccw->bits |= BF_CCW(sg_len, PIO_NUM); 550 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 551 if (flags & MXS_DMA_CTRL_WAIT4RDY) 552 ccw->bits |= CCW_WAIT4RDY; 553 } else { 554 for_each_sg(sgl, sg, sg_len, i) { 555 if (sg_dma_len(sg) > MAX_XFER_BYTES) { 556 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 557 sg_dma_len(sg), MAX_XFER_BYTES); 558 goto err_out; 559 } 560 561 ccw = &mxs_chan->ccw[idx++]; 562 563 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 564 ccw->bufaddr = sg->dma_address; 565 ccw->xfer_bytes = sg_dma_len(sg); 566 567 ccw->bits = 0; 568 ccw->bits |= CCW_CHAIN; 569 ccw->bits |= CCW_HALT_ON_TERM; 570 ccw->bits |= CCW_TERM_FLUSH; 571 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 572 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 573 COMMAND); 574 575 if (i + 1 == sg_len) { 576 ccw->bits &= ~CCW_CHAIN; 577 ccw->bits |= CCW_IRQ; 578 ccw->bits |= CCW_DEC_SEM; 579 if (flags & MXS_DMA_CTRL_WAIT4END) 580 ccw->bits |= CCW_WAIT4END; 581 } 582 } 583 } 584 mxs_chan->desc_count = idx; 585 586 return &mxs_chan->desc; 587 588 err_out: 589 mxs_chan->status = DMA_ERROR; 590 return NULL; 591 } 592 593 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 594 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 595 size_t period_len, enum dma_transfer_direction direction, 596 unsigned long flags) 597 { 598 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 599 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 600 u32 num_periods = buf_len / period_len; 601 u32 i = 0, buf = 0; 602 603 if (mxs_chan->status == DMA_IN_PROGRESS) 604 return NULL; 605 606 mxs_chan->status = DMA_IN_PROGRESS; 607 mxs_chan->flags |= MXS_DMA_SG_LOOP; 608 mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE; 609 610 if (num_periods > NUM_CCW) { 611 dev_err(mxs_dma->dma_device.dev, 612 "maximum number of sg exceeded: %d > %d\n", 613 num_periods, NUM_CCW); 614 goto err_out; 615 } 616 617 if (period_len > MAX_XFER_BYTES) { 618 dev_err(mxs_dma->dma_device.dev, 619 "maximum period size exceeded: %zu > %d\n", 620 period_len, MAX_XFER_BYTES); 621 goto err_out; 622 } 623 624 while (buf < buf_len) { 625 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 626 627 if (i + 1 == num_periods) 628 ccw->next = mxs_chan->ccw_phys; 629 else 630 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 631 632 ccw->bufaddr = dma_addr; 633 ccw->xfer_bytes = period_len; 634 635 ccw->bits = 0; 636 ccw->bits |= CCW_CHAIN; 637 ccw->bits |= CCW_IRQ; 638 ccw->bits |= CCW_HALT_ON_TERM; 639 ccw->bits |= CCW_TERM_FLUSH; 640 ccw->bits |= CCW_DEC_SEM; 641 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 642 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 643 644 dma_addr += period_len; 645 buf += period_len; 646 647 i++; 648 } 649 mxs_chan->desc_count = i; 650 651 return &mxs_chan->desc; 652 653 err_out: 654 mxs_chan->status = DMA_ERROR; 655 return NULL; 656 } 657 658 static int mxs_dma_terminate_all(struct dma_chan *chan) 659 { 660 mxs_dma_reset_chan(chan); 661 mxs_dma_disable_chan(chan); 662 663 return 0; 664 } 665 666 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 667 dma_cookie_t cookie, struct dma_tx_state *txstate) 668 { 669 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 670 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 671 u32 residue = 0; 672 673 if (mxs_chan->status == DMA_IN_PROGRESS && 674 mxs_chan->flags & MXS_DMA_SG_LOOP) { 675 struct mxs_dma_ccw *last_ccw; 676 u32 bar; 677 678 last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1]; 679 residue = last_ccw->xfer_bytes + last_ccw->bufaddr; 680 681 bar = readl(mxs_dma->base + 682 HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id)); 683 residue -= bar; 684 } 685 686 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 687 residue); 688 689 return mxs_chan->status; 690 } 691 692 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 693 { 694 int ret; 695 696 ret = clk_prepare_enable(mxs_dma->clk); 697 if (ret) 698 return ret; 699 700 ret = stmp_reset_block(mxs_dma->base); 701 if (ret) 702 goto err_out; 703 704 /* enable apbh burst */ 705 if (dma_is_apbh(mxs_dma)) { 706 writel(BM_APBH_CTRL0_APB_BURST_EN, 707 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 708 writel(BM_APBH_CTRL0_APB_BURST8_EN, 709 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 710 } 711 712 /* enable irq for all the channels */ 713 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 714 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); 715 716 err_out: 717 clk_disable_unprepare(mxs_dma->clk); 718 return ret; 719 } 720 721 struct mxs_dma_filter_param { 722 unsigned int chan_id; 723 }; 724 725 static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) 726 { 727 struct mxs_dma_filter_param *param = fn_param; 728 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 729 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 730 int chan_irq; 731 732 if (chan->chan_id != param->chan_id) 733 return false; 734 735 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id); 736 if (chan_irq < 0) 737 return false; 738 739 mxs_chan->chan_irq = chan_irq; 740 741 return true; 742 } 743 744 static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, 745 struct of_dma *ofdma) 746 { 747 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data; 748 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; 749 struct mxs_dma_filter_param param; 750 751 if (dma_spec->args_count != 1) 752 return NULL; 753 754 param.chan_id = dma_spec->args[0]; 755 756 if (param.chan_id >= mxs_dma->nr_channels) 757 return NULL; 758 759 return __dma_request_channel(&mask, mxs_dma_filter_fn, ¶m, 760 ofdma->of_node); 761 } 762 763 static int __init mxs_dma_probe(struct platform_device *pdev) 764 { 765 struct device_node *np = pdev->dev.of_node; 766 const struct platform_device_id *id_entry; 767 const struct of_device_id *of_id; 768 const struct mxs_dma_type *dma_type; 769 struct mxs_dma_engine *mxs_dma; 770 struct resource *iores; 771 int ret, i; 772 773 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); 774 if (!mxs_dma) 775 return -ENOMEM; 776 777 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); 778 if (ret) { 779 dev_err(&pdev->dev, "failed to read dma-channels\n"); 780 return ret; 781 } 782 783 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev); 784 if (of_id) 785 id_entry = of_id->data; 786 else 787 id_entry = platform_get_device_id(pdev); 788 789 dma_type = (struct mxs_dma_type *)id_entry->driver_data; 790 mxs_dma->type = dma_type->type; 791 mxs_dma->dev_id = dma_type->id; 792 793 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); 795 if (IS_ERR(mxs_dma->base)) 796 return PTR_ERR(mxs_dma->base); 797 798 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); 799 if (IS_ERR(mxs_dma->clk)) 800 return PTR_ERR(mxs_dma->clk); 801 802 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 803 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 804 805 INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 806 807 /* Initialize channel parameters */ 808 for (i = 0; i < MXS_DMA_CHANNELS; i++) { 809 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 810 811 mxs_chan->mxs_dma = mxs_dma; 812 mxs_chan->chan.device = &mxs_dma->dma_device; 813 dma_cookie_init(&mxs_chan->chan); 814 815 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 816 (unsigned long) mxs_chan); 817 818 819 /* Add the channel to mxs_chan list */ 820 list_add_tail(&mxs_chan->chan.device_node, 821 &mxs_dma->dma_device.channels); 822 } 823 824 ret = mxs_dma_init(mxs_dma); 825 if (ret) 826 return ret; 827 828 mxs_dma->pdev = pdev; 829 mxs_dma->dma_device.dev = &pdev->dev; 830 831 /* mxs_dma gets 65535 bytes maximum sg size */ 832 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 833 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 834 835 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 836 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 837 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 838 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 839 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 840 mxs_dma->dma_device.device_pause = mxs_dma_pause_chan; 841 mxs_dma->dma_device.device_resume = mxs_dma_resume_chan; 842 mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all; 843 mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 844 mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 845 mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 846 mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 847 mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan; 848 849 ret = dmaenginem_async_device_register(&mxs_dma->dma_device); 850 if (ret) { 851 dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 852 return ret; 853 } 854 855 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); 856 if (ret) { 857 dev_err(mxs_dma->dma_device.dev, 858 "failed to register controller\n"); 859 } 860 861 dev_info(mxs_dma->dma_device.dev, "initialized\n"); 862 863 return 0; 864 } 865 866 static struct platform_driver mxs_dma_driver = { 867 .driver = { 868 .name = "mxs-dma", 869 .of_match_table = mxs_dma_dt_ids, 870 }, 871 .id_table = mxs_dma_ids, 872 }; 873 874 static int __init mxs_dma_module_init(void) 875 { 876 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 877 } 878 subsys_initcall(mxs_dma_module_init); 879