1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * Refer to drivers/dma/imx-sdma.c 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/mm.h> 14 #include <linux/interrupt.h> 15 #include <linux/clk.h> 16 #include <linux/wait.h> 17 #include <linux/sched.h> 18 #include <linux/semaphore.h> 19 #include <linux/device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/dmaengine.h> 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/fsl/mxs-dma.h> 27 #include <linux/stmp_device.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/of_dma.h> 31 32 #include <asm/irq.h> 33 34 #include "dmaengine.h" 35 36 /* 37 * NOTE: The term "PIO" throughout the mxs-dma implementation means 38 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 39 * dma can program the controller registers of peripheral devices. 40 */ 41 42 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) 43 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) 44 45 #define HW_APBHX_CTRL0 0x000 46 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 47 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 48 #define BP_APBH_CTRL0_RESET_CHANNEL 16 49 #define HW_APBHX_CTRL1 0x010 50 #define HW_APBHX_CTRL2 0x020 51 #define HW_APBHX_CHANNEL_CTRL 0x030 52 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 53 /* 54 * The offset of NXTCMDAR register is different per both dma type and version, 55 * while stride for each channel is all the same 0x70. 56 */ 57 #define HW_APBHX_CHn_NXTCMDAR(d, n) \ 58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) 59 #define HW_APBHX_CHn_SEMA(d, n) \ 60 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) 61 62 /* 63 * ccw bits definitions 64 * 65 * COMMAND: 0..1 (2) 66 * CHAIN: 2 (1) 67 * IRQ: 3 (1) 68 * NAND_LOCK: 4 (1) - not implemented 69 * NAND_WAIT4READY: 5 (1) - not implemented 70 * DEC_SEM: 6 (1) 71 * WAIT4END: 7 (1) 72 * HALT_ON_TERMINATE: 8 (1) 73 * TERMINATE_FLUSH: 9 (1) 74 * RESERVED: 10..11 (2) 75 * PIO_NUM: 12..15 (4) 76 */ 77 #define BP_CCW_COMMAND 0 78 #define BM_CCW_COMMAND (3 << 0) 79 #define CCW_CHAIN (1 << 2) 80 #define CCW_IRQ (1 << 3) 81 #define CCW_DEC_SEM (1 << 6) 82 #define CCW_WAIT4END (1 << 7) 83 #define CCW_HALT_ON_TERM (1 << 8) 84 #define CCW_TERM_FLUSH (1 << 9) 85 #define BP_CCW_PIO_NUM 12 86 #define BM_CCW_PIO_NUM (0xf << 12) 87 88 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 89 90 #define MXS_DMA_CMD_NO_XFER 0 91 #define MXS_DMA_CMD_WRITE 1 92 #define MXS_DMA_CMD_READ 2 93 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 94 95 struct mxs_dma_ccw { 96 u32 next; 97 u16 bits; 98 u16 xfer_bytes; 99 #define MAX_XFER_BYTES 0xff00 100 u32 bufaddr; 101 #define MXS_PIO_WORDS 16 102 u32 pio_words[MXS_PIO_WORDS]; 103 }; 104 105 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE) 106 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw)) 107 108 struct mxs_dma_chan { 109 struct mxs_dma_engine *mxs_dma; 110 struct dma_chan chan; 111 struct dma_async_tx_descriptor desc; 112 struct tasklet_struct tasklet; 113 unsigned int chan_irq; 114 struct mxs_dma_ccw *ccw; 115 dma_addr_t ccw_phys; 116 int desc_count; 117 enum dma_status status; 118 unsigned int flags; 119 #define MXS_DMA_SG_LOOP (1 << 0) 120 }; 121 122 #define MXS_DMA_CHANNELS 16 123 #define MXS_DMA_CHANNELS_MASK 0xffff 124 125 enum mxs_dma_devtype { 126 MXS_DMA_APBH, 127 MXS_DMA_APBX, 128 }; 129 130 enum mxs_dma_id { 131 IMX23_DMA, 132 IMX28_DMA, 133 }; 134 135 struct mxs_dma_engine { 136 enum mxs_dma_id dev_id; 137 enum mxs_dma_devtype type; 138 void __iomem *base; 139 struct clk *clk; 140 struct dma_device dma_device; 141 struct device_dma_parameters dma_parms; 142 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 143 struct platform_device *pdev; 144 unsigned int nr_channels; 145 }; 146 147 struct mxs_dma_type { 148 enum mxs_dma_id id; 149 enum mxs_dma_devtype type; 150 }; 151 152 static struct mxs_dma_type mxs_dma_types[] = { 153 { 154 .id = IMX23_DMA, 155 .type = MXS_DMA_APBH, 156 }, { 157 .id = IMX23_DMA, 158 .type = MXS_DMA_APBX, 159 }, { 160 .id = IMX28_DMA, 161 .type = MXS_DMA_APBH, 162 }, { 163 .id = IMX28_DMA, 164 .type = MXS_DMA_APBX, 165 } 166 }; 167 168 static struct platform_device_id mxs_dma_ids[] = { 169 { 170 .name = "imx23-dma-apbh", 171 .driver_data = (kernel_ulong_t) &mxs_dma_types[0], 172 }, { 173 .name = "imx23-dma-apbx", 174 .driver_data = (kernel_ulong_t) &mxs_dma_types[1], 175 }, { 176 .name = "imx28-dma-apbh", 177 .driver_data = (kernel_ulong_t) &mxs_dma_types[2], 178 }, { 179 .name = "imx28-dma-apbx", 180 .driver_data = (kernel_ulong_t) &mxs_dma_types[3], 181 }, { 182 /* end of list */ 183 } 184 }; 185 186 static const struct of_device_id mxs_dma_dt_ids[] = { 187 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], }, 188 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, 189 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, 190 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, 191 { /* sentinel */ } 192 }; 193 MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); 194 195 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 196 { 197 return container_of(chan, struct mxs_dma_chan, chan); 198 } 199 200 int mxs_dma_is_apbh(struct dma_chan *chan) 201 { 202 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 203 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 204 205 return dma_is_apbh(mxs_dma); 206 } 207 EXPORT_SYMBOL_GPL(mxs_dma_is_apbh); 208 209 int mxs_dma_is_apbx(struct dma_chan *chan) 210 { 211 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 212 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 213 214 return !dma_is_apbh(mxs_dma); 215 } 216 EXPORT_SYMBOL_GPL(mxs_dma_is_apbx); 217 218 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) 219 { 220 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 221 int chan_id = mxs_chan->chan.chan_id; 222 223 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 224 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 225 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 226 else 227 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 228 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 229 } 230 231 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) 232 { 233 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 234 int chan_id = mxs_chan->chan.chan_id; 235 236 /* set cmd_addr up */ 237 writel(mxs_chan->ccw_phys, 238 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); 239 240 /* write 1 to SEMA to kick off the channel */ 241 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 242 } 243 244 static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) 245 { 246 mxs_chan->status = DMA_SUCCESS; 247 } 248 249 static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) 250 { 251 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 252 int chan_id = mxs_chan->chan.chan_id; 253 254 /* freeze the channel */ 255 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 256 writel(1 << chan_id, 257 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 258 else 259 writel(1 << chan_id, 260 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 261 262 mxs_chan->status = DMA_PAUSED; 263 } 264 265 static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) 266 { 267 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 268 int chan_id = mxs_chan->chan.chan_id; 269 270 /* unfreeze the channel */ 271 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 272 writel(1 << chan_id, 273 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); 274 else 275 writel(1 << chan_id, 276 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); 277 278 mxs_chan->status = DMA_IN_PROGRESS; 279 } 280 281 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 282 { 283 return dma_cookie_assign(tx); 284 } 285 286 static void mxs_dma_tasklet(unsigned long data) 287 { 288 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 289 290 if (mxs_chan->desc.callback) 291 mxs_chan->desc.callback(mxs_chan->desc.callback_param); 292 } 293 294 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 295 { 296 struct mxs_dma_engine *mxs_dma = dev_id; 297 u32 stat1, stat2; 298 299 /* completion status */ 300 stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); 301 stat1 &= MXS_DMA_CHANNELS_MASK; 302 writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); 303 304 /* error status */ 305 stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); 306 writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); 307 308 /* 309 * When both completion and error of termination bits set at the 310 * same time, we do not take it as an error. IOW, it only becomes 311 * an error we need to handle here in case of either it's (1) a bus 312 * error or (2) a termination error with no completion. 313 */ 314 stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ 315 (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ 316 317 /* combine error and completion status for checking */ 318 stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; 319 while (stat1) { 320 int channel = fls(stat1) - 1; 321 struct mxs_dma_chan *mxs_chan = 322 &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; 323 324 if (channel >= MXS_DMA_CHANNELS) { 325 dev_dbg(mxs_dma->dma_device.dev, 326 "%s: error in channel %d\n", __func__, 327 channel - MXS_DMA_CHANNELS); 328 mxs_chan->status = DMA_ERROR; 329 mxs_dma_reset_chan(mxs_chan); 330 } else { 331 if (mxs_chan->flags & MXS_DMA_SG_LOOP) 332 mxs_chan->status = DMA_IN_PROGRESS; 333 else 334 mxs_chan->status = DMA_SUCCESS; 335 } 336 337 stat1 &= ~(1 << channel); 338 339 if (mxs_chan->status == DMA_SUCCESS) 340 dma_cookie_complete(&mxs_chan->desc); 341 342 /* schedule tasklet on this channel */ 343 tasklet_schedule(&mxs_chan->tasklet); 344 } 345 346 return IRQ_HANDLED; 347 } 348 349 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 350 { 351 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 352 struct mxs_dma_data *data = chan->private; 353 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 354 int ret; 355 356 if (data) 357 mxs_chan->chan_irq = data->chan_irq; 358 359 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, 360 CCW_BLOCK_SIZE, &mxs_chan->ccw_phys, 361 GFP_KERNEL); 362 if (!mxs_chan->ccw) { 363 ret = -ENOMEM; 364 goto err_alloc; 365 } 366 367 memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE); 368 369 if (mxs_chan->chan_irq != NO_IRQ) { 370 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 371 0, "mxs-dma", mxs_dma); 372 if (ret) 373 goto err_irq; 374 } 375 376 ret = clk_prepare_enable(mxs_dma->clk); 377 if (ret) 378 goto err_clk; 379 380 mxs_dma_reset_chan(mxs_chan); 381 382 dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 383 mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 384 385 /* the descriptor is ready */ 386 async_tx_ack(&mxs_chan->desc); 387 388 return 0; 389 390 err_clk: 391 free_irq(mxs_chan->chan_irq, mxs_dma); 392 err_irq: 393 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 394 mxs_chan->ccw, mxs_chan->ccw_phys); 395 err_alloc: 396 return ret; 397 } 398 399 static void mxs_dma_free_chan_resources(struct dma_chan *chan) 400 { 401 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 402 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 403 404 mxs_dma_disable_chan(mxs_chan); 405 406 free_irq(mxs_chan->chan_irq, mxs_dma); 407 408 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 409 mxs_chan->ccw, mxs_chan->ccw_phys); 410 411 clk_disable_unprepare(mxs_dma->clk); 412 } 413 414 /* 415 * How to use the flags for ->device_prep_slave_sg() : 416 * [1] If there is only one DMA command in the DMA chain, the code should be: 417 * ...... 418 * ->device_prep_slave_sg(DMA_CTRL_ACK); 419 * ...... 420 * [2] If there are two DMA commands in the DMA chain, the code should be 421 * ...... 422 * ->device_prep_slave_sg(0); 423 * ...... 424 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 425 * ...... 426 * [3] If there are more than two DMA commands in the DMA chain, the code 427 * should be: 428 * ...... 429 * ->device_prep_slave_sg(0); // First 430 * ...... 431 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]); 432 * ...... 433 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last 434 * ...... 435 */ 436 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 437 struct dma_chan *chan, struct scatterlist *sgl, 438 unsigned int sg_len, enum dma_transfer_direction direction, 439 unsigned long flags, void *context) 440 { 441 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 442 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 443 struct mxs_dma_ccw *ccw; 444 struct scatterlist *sg; 445 u32 i, j; 446 u32 *pio; 447 bool append = flags & DMA_PREP_INTERRUPT; 448 int idx = append ? mxs_chan->desc_count : 0; 449 450 if (mxs_chan->status == DMA_IN_PROGRESS && !append) 451 return NULL; 452 453 if (sg_len + (append ? idx : 0) > NUM_CCW) { 454 dev_err(mxs_dma->dma_device.dev, 455 "maximum number of sg exceeded: %d > %d\n", 456 sg_len, NUM_CCW); 457 goto err_out; 458 } 459 460 mxs_chan->status = DMA_IN_PROGRESS; 461 mxs_chan->flags = 0; 462 463 /* 464 * If the sg is prepared with append flag set, the sg 465 * will be appended to the last prepared sg. 466 */ 467 if (append) { 468 BUG_ON(idx < 1); 469 ccw = &mxs_chan->ccw[idx - 1]; 470 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 471 ccw->bits |= CCW_CHAIN; 472 ccw->bits &= ~CCW_IRQ; 473 ccw->bits &= ~CCW_DEC_SEM; 474 } else { 475 idx = 0; 476 } 477 478 if (direction == DMA_TRANS_NONE) { 479 ccw = &mxs_chan->ccw[idx++]; 480 pio = (u32 *) sgl; 481 482 for (j = 0; j < sg_len;) 483 ccw->pio_words[j++] = *pio++; 484 485 ccw->bits = 0; 486 ccw->bits |= CCW_IRQ; 487 ccw->bits |= CCW_DEC_SEM; 488 if (flags & DMA_CTRL_ACK) 489 ccw->bits |= CCW_WAIT4END; 490 ccw->bits |= CCW_HALT_ON_TERM; 491 ccw->bits |= CCW_TERM_FLUSH; 492 ccw->bits |= BF_CCW(sg_len, PIO_NUM); 493 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 494 } else { 495 for_each_sg(sgl, sg, sg_len, i) { 496 if (sg_dma_len(sg) > MAX_XFER_BYTES) { 497 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 498 sg_dma_len(sg), MAX_XFER_BYTES); 499 goto err_out; 500 } 501 502 ccw = &mxs_chan->ccw[idx++]; 503 504 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 505 ccw->bufaddr = sg->dma_address; 506 ccw->xfer_bytes = sg_dma_len(sg); 507 508 ccw->bits = 0; 509 ccw->bits |= CCW_CHAIN; 510 ccw->bits |= CCW_HALT_ON_TERM; 511 ccw->bits |= CCW_TERM_FLUSH; 512 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 513 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 514 COMMAND); 515 516 if (i + 1 == sg_len) { 517 ccw->bits &= ~CCW_CHAIN; 518 ccw->bits |= CCW_IRQ; 519 ccw->bits |= CCW_DEC_SEM; 520 if (flags & DMA_CTRL_ACK) 521 ccw->bits |= CCW_WAIT4END; 522 } 523 } 524 } 525 mxs_chan->desc_count = idx; 526 527 return &mxs_chan->desc; 528 529 err_out: 530 mxs_chan->status = DMA_ERROR; 531 return NULL; 532 } 533 534 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 535 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 536 size_t period_len, enum dma_transfer_direction direction, 537 unsigned long flags, void *context) 538 { 539 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 540 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 541 u32 num_periods = buf_len / period_len; 542 u32 i = 0, buf = 0; 543 544 if (mxs_chan->status == DMA_IN_PROGRESS) 545 return NULL; 546 547 mxs_chan->status = DMA_IN_PROGRESS; 548 mxs_chan->flags |= MXS_DMA_SG_LOOP; 549 550 if (num_periods > NUM_CCW) { 551 dev_err(mxs_dma->dma_device.dev, 552 "maximum number of sg exceeded: %d > %d\n", 553 num_periods, NUM_CCW); 554 goto err_out; 555 } 556 557 if (period_len > MAX_XFER_BYTES) { 558 dev_err(mxs_dma->dma_device.dev, 559 "maximum period size exceeded: %d > %d\n", 560 period_len, MAX_XFER_BYTES); 561 goto err_out; 562 } 563 564 while (buf < buf_len) { 565 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 566 567 if (i + 1 == num_periods) 568 ccw->next = mxs_chan->ccw_phys; 569 else 570 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 571 572 ccw->bufaddr = dma_addr; 573 ccw->xfer_bytes = period_len; 574 575 ccw->bits = 0; 576 ccw->bits |= CCW_CHAIN; 577 ccw->bits |= CCW_IRQ; 578 ccw->bits |= CCW_HALT_ON_TERM; 579 ccw->bits |= CCW_TERM_FLUSH; 580 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 581 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 582 583 dma_addr += period_len; 584 buf += period_len; 585 586 i++; 587 } 588 mxs_chan->desc_count = i; 589 590 return &mxs_chan->desc; 591 592 err_out: 593 mxs_chan->status = DMA_ERROR; 594 return NULL; 595 } 596 597 static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 598 unsigned long arg) 599 { 600 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 601 int ret = 0; 602 603 switch (cmd) { 604 case DMA_TERMINATE_ALL: 605 mxs_dma_reset_chan(mxs_chan); 606 mxs_dma_disable_chan(mxs_chan); 607 break; 608 case DMA_PAUSE: 609 mxs_dma_pause_chan(mxs_chan); 610 break; 611 case DMA_RESUME: 612 mxs_dma_resume_chan(mxs_chan); 613 break; 614 default: 615 ret = -ENOSYS; 616 } 617 618 return ret; 619 } 620 621 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 622 dma_cookie_t cookie, struct dma_tx_state *txstate) 623 { 624 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 625 dma_cookie_t last_used; 626 627 last_used = chan->cookie; 628 dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); 629 630 return mxs_chan->status; 631 } 632 633 static void mxs_dma_issue_pending(struct dma_chan *chan) 634 { 635 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 636 637 mxs_dma_enable_chan(mxs_chan); 638 } 639 640 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 641 { 642 int ret; 643 644 ret = clk_prepare_enable(mxs_dma->clk); 645 if (ret) 646 return ret; 647 648 ret = stmp_reset_block(mxs_dma->base); 649 if (ret) 650 goto err_out; 651 652 /* enable apbh burst */ 653 if (dma_is_apbh(mxs_dma)) { 654 writel(BM_APBH_CTRL0_APB_BURST_EN, 655 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 656 writel(BM_APBH_CTRL0_APB_BURST8_EN, 657 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 658 } 659 660 /* enable irq for all the channels */ 661 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 662 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); 663 664 err_out: 665 clk_disable_unprepare(mxs_dma->clk); 666 return ret; 667 } 668 669 struct mxs_dma_filter_param { 670 struct device_node *of_node; 671 unsigned int chan_id; 672 }; 673 674 static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) 675 { 676 struct mxs_dma_filter_param *param = fn_param; 677 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 678 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 679 int chan_irq; 680 681 if (mxs_dma->dma_device.dev->of_node != param->of_node) 682 return false; 683 684 if (chan->chan_id != param->chan_id) 685 return false; 686 687 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id); 688 if (chan_irq < 0) 689 return false; 690 691 mxs_chan->chan_irq = chan_irq; 692 693 return true; 694 } 695 696 struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, 697 struct of_dma *ofdma) 698 { 699 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data; 700 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; 701 struct mxs_dma_filter_param param; 702 703 if (dma_spec->args_count != 1) 704 return NULL; 705 706 param.of_node = ofdma->of_node; 707 param.chan_id = dma_spec->args[0]; 708 709 if (param.chan_id >= mxs_dma->nr_channels) 710 return NULL; 711 712 return dma_request_channel(mask, mxs_dma_filter_fn, ¶m); 713 } 714 715 static int __init mxs_dma_probe(struct platform_device *pdev) 716 { 717 struct device_node *np = pdev->dev.of_node; 718 const struct platform_device_id *id_entry; 719 const struct of_device_id *of_id; 720 const struct mxs_dma_type *dma_type; 721 struct mxs_dma_engine *mxs_dma; 722 struct resource *iores; 723 int ret, i; 724 725 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); 726 if (!mxs_dma) 727 return -ENOMEM; 728 729 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); 730 if (ret) { 731 dev_err(&pdev->dev, "failed to read dma-channels\n"); 732 return ret; 733 } 734 735 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev); 736 if (of_id) 737 id_entry = of_id->data; 738 else 739 id_entry = platform_get_device_id(pdev); 740 741 dma_type = (struct mxs_dma_type *)id_entry->driver_data; 742 mxs_dma->type = dma_type->type; 743 mxs_dma->dev_id = dma_type->id; 744 745 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 746 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); 747 if (IS_ERR(mxs_dma->base)) 748 return PTR_ERR(mxs_dma->base); 749 750 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); 751 if (IS_ERR(mxs_dma->clk)) 752 return PTR_ERR(mxs_dma->clk); 753 754 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 755 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 756 757 INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 758 759 /* Initialize channel parameters */ 760 for (i = 0; i < MXS_DMA_CHANNELS; i++) { 761 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 762 763 mxs_chan->mxs_dma = mxs_dma; 764 mxs_chan->chan.device = &mxs_dma->dma_device; 765 dma_cookie_init(&mxs_chan->chan); 766 767 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 768 (unsigned long) mxs_chan); 769 770 771 /* Add the channel to mxs_chan list */ 772 list_add_tail(&mxs_chan->chan.device_node, 773 &mxs_dma->dma_device.channels); 774 } 775 776 ret = mxs_dma_init(mxs_dma); 777 if (ret) 778 return ret; 779 780 mxs_dma->pdev = pdev; 781 mxs_dma->dma_device.dev = &pdev->dev; 782 783 /* mxs_dma gets 65535 bytes maximum sg size */ 784 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 785 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 786 787 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 788 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 789 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 790 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 791 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 792 mxs_dma->dma_device.device_control = mxs_dma_control; 793 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; 794 795 ret = dma_async_device_register(&mxs_dma->dma_device); 796 if (ret) { 797 dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 798 return ret; 799 } 800 801 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); 802 if (ret) { 803 dev_err(mxs_dma->dma_device.dev, 804 "failed to register controller\n"); 805 dma_async_device_unregister(&mxs_dma->dma_device); 806 } 807 808 dev_info(mxs_dma->dma_device.dev, "initialized\n"); 809 810 return 0; 811 } 812 813 static struct platform_driver mxs_dma_driver = { 814 .driver = { 815 .name = "mxs-dma", 816 .of_match_table = mxs_dma_dt_ids, 817 }, 818 .id_table = mxs_dma_ids, 819 }; 820 821 static int __init mxs_dma_module_init(void) 822 { 823 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 824 } 825 subsys_initcall(mxs_dma_module_init); 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