1a580b8c5SShawn Guo /* 2a580b8c5SShawn Guo * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3a580b8c5SShawn Guo * 4a580b8c5SShawn Guo * Refer to drivers/dma/imx-sdma.c 5a580b8c5SShawn Guo * 6a580b8c5SShawn Guo * This program is free software; you can redistribute it and/or modify 7a580b8c5SShawn Guo * it under the terms of the GNU General Public License version 2 as 8a580b8c5SShawn Guo * published by the Free Software Foundation. 9a580b8c5SShawn Guo */ 10a580b8c5SShawn Guo 11a580b8c5SShawn Guo #include <linux/init.h> 12a580b8c5SShawn Guo #include <linux/types.h> 13a580b8c5SShawn Guo #include <linux/mm.h> 14a580b8c5SShawn Guo #include <linux/interrupt.h> 15a580b8c5SShawn Guo #include <linux/clk.h> 16a580b8c5SShawn Guo #include <linux/wait.h> 17a580b8c5SShawn Guo #include <linux/sched.h> 18a580b8c5SShawn Guo #include <linux/semaphore.h> 19a580b8c5SShawn Guo #include <linux/device.h> 20a580b8c5SShawn Guo #include <linux/dma-mapping.h> 21a580b8c5SShawn Guo #include <linux/slab.h> 22a580b8c5SShawn Guo #include <linux/platform_device.h> 23a580b8c5SShawn Guo #include <linux/dmaengine.h> 24a580b8c5SShawn Guo #include <linux/delay.h> 25a580b8c5SShawn Guo 26a580b8c5SShawn Guo #include <asm/irq.h> 27a580b8c5SShawn Guo #include <mach/mxs.h> 28a580b8c5SShawn Guo #include <mach/dma.h> 29a580b8c5SShawn Guo #include <mach/common.h> 30a580b8c5SShawn Guo 31a580b8c5SShawn Guo /* 32a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means 33a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 34a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices. 35a580b8c5SShawn Guo */ 36a580b8c5SShawn Guo 37a580b8c5SShawn Guo #define MXS_DMA_APBH 0 38a580b8c5SShawn Guo #define MXS_DMA_APBX 1 39a580b8c5SShawn Guo #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) 40a580b8c5SShawn Guo 41a580b8c5SShawn Guo #define APBH_VERSION_LATEST 3 42a580b8c5SShawn Guo #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) 43a580b8c5SShawn Guo 44a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000 45a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 46a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 47a580b8c5SShawn Guo #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 48a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16 49a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010 50a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020 51a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030 52a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 53a580b8c5SShawn Guo #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) 54a580b8c5SShawn Guo #define HW_APBX_VERSION 0x800 55a580b8c5SShawn Guo #define BP_APBHX_VERSION_MAJOR 24 56a580b8c5SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(n) \ 57a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) 58a580b8c5SShawn Guo #define HW_APBHX_CHn_SEMA(n) \ 59a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) 60a580b8c5SShawn Guo 61a580b8c5SShawn Guo /* 62a580b8c5SShawn Guo * ccw bits definitions 63a580b8c5SShawn Guo * 64a580b8c5SShawn Guo * COMMAND: 0..1 (2) 65a580b8c5SShawn Guo * CHAIN: 2 (1) 66a580b8c5SShawn Guo * IRQ: 3 (1) 67a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented 68a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented 69a580b8c5SShawn Guo * DEC_SEM: 6 (1) 70a580b8c5SShawn Guo * WAIT4END: 7 (1) 71a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1) 72a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1) 73a580b8c5SShawn Guo * RESERVED: 10..11 (2) 74a580b8c5SShawn Guo * PIO_NUM: 12..15 (4) 75a580b8c5SShawn Guo */ 76a580b8c5SShawn Guo #define BP_CCW_COMMAND 0 77a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0) 78a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2) 79a580b8c5SShawn Guo #define CCW_IRQ (1 << 3) 80a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6) 81a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7) 82a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8) 83a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9) 84a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12 85a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12) 86a580b8c5SShawn Guo 87a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 88a580b8c5SShawn Guo 89a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0 90a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1 91a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2 92a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 93a580b8c5SShawn Guo 94a580b8c5SShawn Guo struct mxs_dma_ccw { 95a580b8c5SShawn Guo u32 next; 96a580b8c5SShawn Guo u16 bits; 97a580b8c5SShawn Guo u16 xfer_bytes; 98a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00 99a580b8c5SShawn Guo u32 bufaddr; 100a580b8c5SShawn Guo #define MXS_PIO_WORDS 16 101a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS]; 102a580b8c5SShawn Guo }; 103a580b8c5SShawn Guo 104a580b8c5SShawn Guo #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) 105a580b8c5SShawn Guo 106a580b8c5SShawn Guo struct mxs_dma_chan { 107a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 108a580b8c5SShawn Guo struct dma_chan chan; 109a580b8c5SShawn Guo struct dma_async_tx_descriptor desc; 110a580b8c5SShawn Guo struct tasklet_struct tasklet; 111a580b8c5SShawn Guo int chan_irq; 112a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 113a580b8c5SShawn Guo dma_addr_t ccw_phys; 114a580b8c5SShawn Guo dma_cookie_t last_completed; 115a580b8c5SShawn Guo enum dma_status status; 116a580b8c5SShawn Guo unsigned int flags; 117a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0) 118a580b8c5SShawn Guo }; 119a580b8c5SShawn Guo 120a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16 121a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff 122a580b8c5SShawn Guo 123a580b8c5SShawn Guo struct mxs_dma_engine { 124a580b8c5SShawn Guo int dev_id; 125a580b8c5SShawn Guo unsigned int version; 126a580b8c5SShawn Guo void __iomem *base; 127a580b8c5SShawn Guo struct clk *clk; 128a580b8c5SShawn Guo struct dma_device dma_device; 129a580b8c5SShawn Guo struct device_dma_parameters dma_parms; 130a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 131a580b8c5SShawn Guo }; 132a580b8c5SShawn Guo 133ef298c21SLothar Waßmann static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable) 134ef298c21SLothar Waßmann { 135ef298c21SLothar Waßmann struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 136ef298c21SLothar Waßmann int chan_id = mxs_chan->chan.chan_id; 137ef298c21SLothar Waßmann int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR; 138ef298c21SLothar Waßmann 139ef298c21SLothar Waßmann /* enable apbh channel clock */ 140ef298c21SLothar Waßmann if (dma_is_apbh()) { 141ef298c21SLothar Waßmann if (apbh_is_old()) 142ef298c21SLothar Waßmann writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL), 143ef298c21SLothar Waßmann mxs_dma->base + HW_APBHX_CTRL0 + set_clr); 144ef298c21SLothar Waßmann else 145ef298c21SLothar Waßmann writel(1 << chan_id, 146ef298c21SLothar Waßmann mxs_dma->base + HW_APBHX_CTRL0 + set_clr); 147ef298c21SLothar Waßmann } 148ef298c21SLothar Waßmann } 149ef298c21SLothar Waßmann 150a580b8c5SShawn Guo static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) 151a580b8c5SShawn Guo { 152a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 153a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 154a580b8c5SShawn Guo 155a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 156a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 157a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 158a580b8c5SShawn Guo else 159a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 160a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 161a580b8c5SShawn Guo } 162a580b8c5SShawn Guo 163a580b8c5SShawn Guo static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) 164a580b8c5SShawn Guo { 165a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 166a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 167a580b8c5SShawn Guo 168ef298c21SLothar Waßmann /* clkgate needs to be enabled before writing other registers */ 169ef298c21SLothar Waßmann mxs_dma_clkgate(mxs_chan, 1); 170ef298c21SLothar Waßmann 171a580b8c5SShawn Guo /* set cmd_addr up */ 172a580b8c5SShawn Guo writel(mxs_chan->ccw_phys, 173a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); 174a580b8c5SShawn Guo 175a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */ 176a580b8c5SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); 177a580b8c5SShawn Guo } 178a580b8c5SShawn Guo 179a580b8c5SShawn Guo static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) 180a580b8c5SShawn Guo { 181a580b8c5SShawn Guo /* disable apbh channel clock */ 182ef298c21SLothar Waßmann mxs_dma_clkgate(mxs_chan, 0); 183a580b8c5SShawn Guo 184a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 185a580b8c5SShawn Guo } 186a580b8c5SShawn Guo 187a580b8c5SShawn Guo static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) 188a580b8c5SShawn Guo { 189a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 190a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 191a580b8c5SShawn Guo 192a580b8c5SShawn Guo /* freeze the channel */ 193a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 194a580b8c5SShawn Guo writel(1 << chan_id, 195a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 196a580b8c5SShawn Guo else 197a580b8c5SShawn Guo writel(1 << chan_id, 198a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 199a580b8c5SShawn Guo 200a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED; 201a580b8c5SShawn Guo } 202a580b8c5SShawn Guo 203a580b8c5SShawn Guo static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) 204a580b8c5SShawn Guo { 205a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 206a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 207a580b8c5SShawn Guo 208a580b8c5SShawn Guo /* unfreeze the channel */ 209a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 210a580b8c5SShawn Guo writel(1 << chan_id, 211a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); 212a580b8c5SShawn Guo else 213a580b8c5SShawn Guo writel(1 << chan_id, 214a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); 215a580b8c5SShawn Guo 216a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 217a580b8c5SShawn Guo } 218a580b8c5SShawn Guo 219a580b8c5SShawn Guo static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan) 220a580b8c5SShawn Guo { 221a580b8c5SShawn Guo dma_cookie_t cookie = mxs_chan->chan.cookie; 222a580b8c5SShawn Guo 223a580b8c5SShawn Guo if (++cookie < 0) 224a580b8c5SShawn Guo cookie = 1; 225a580b8c5SShawn Guo 226a580b8c5SShawn Guo mxs_chan->chan.cookie = cookie; 227a580b8c5SShawn Guo mxs_chan->desc.cookie = cookie; 228a580b8c5SShawn Guo 229a580b8c5SShawn Guo return cookie; 230a580b8c5SShawn Guo } 231a580b8c5SShawn Guo 232a580b8c5SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 233a580b8c5SShawn Guo { 234a580b8c5SShawn Guo return container_of(chan, struct mxs_dma_chan, chan); 235a580b8c5SShawn Guo } 236a580b8c5SShawn Guo 237a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 238a580b8c5SShawn Guo { 239a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); 240a580b8c5SShawn Guo 241a580b8c5SShawn Guo mxs_dma_enable_chan(mxs_chan); 242a580b8c5SShawn Guo 243a580b8c5SShawn Guo return mxs_dma_assign_cookie(mxs_chan); 244a580b8c5SShawn Guo } 245a580b8c5SShawn Guo 246a580b8c5SShawn Guo static void mxs_dma_tasklet(unsigned long data) 247a580b8c5SShawn Guo { 248a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 249a580b8c5SShawn Guo 250a580b8c5SShawn Guo if (mxs_chan->desc.callback) 251a580b8c5SShawn Guo mxs_chan->desc.callback(mxs_chan->desc.callback_param); 252a580b8c5SShawn Guo } 253a580b8c5SShawn Guo 254a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 255a580b8c5SShawn Guo { 256a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id; 257a580b8c5SShawn Guo u32 stat1, stat2; 258a580b8c5SShawn Guo 259a580b8c5SShawn Guo /* completion status */ 260a580b8c5SShawn Guo stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); 261a580b8c5SShawn Guo stat1 &= MXS_DMA_CHANNELS_MASK; 262a580b8c5SShawn Guo writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); 263a580b8c5SShawn Guo 264a580b8c5SShawn Guo /* error status */ 265a580b8c5SShawn Guo stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); 266a580b8c5SShawn Guo writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); 267a580b8c5SShawn Guo 268a580b8c5SShawn Guo /* 269a580b8c5SShawn Guo * When both completion and error of termination bits set at the 270a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes 271a580b8c5SShawn Guo * an error we need to handler here in case of ether it's (1) an bus 272a580b8c5SShawn Guo * error or (2) a termination error with no completion. 273a580b8c5SShawn Guo */ 274a580b8c5SShawn Guo stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ 275a580b8c5SShawn Guo (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ 276a580b8c5SShawn Guo 277a580b8c5SShawn Guo /* combine error and completion status for checking */ 278a580b8c5SShawn Guo stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; 279a580b8c5SShawn Guo while (stat1) { 280a580b8c5SShawn Guo int channel = fls(stat1) - 1; 281a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = 282a580b8c5SShawn Guo &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; 283a580b8c5SShawn Guo 284a580b8c5SShawn Guo if (channel >= MXS_DMA_CHANNELS) { 285a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev, 286a580b8c5SShawn Guo "%s: error in channel %d\n", __func__, 287a580b8c5SShawn Guo channel - MXS_DMA_CHANNELS); 288a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 289a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 290a580b8c5SShawn Guo } else { 291a580b8c5SShawn Guo if (mxs_chan->flags & MXS_DMA_SG_LOOP) 292a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 293a580b8c5SShawn Guo else 294a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 295a580b8c5SShawn Guo } 296a580b8c5SShawn Guo 297a580b8c5SShawn Guo stat1 &= ~(1 << channel); 298a580b8c5SShawn Guo 299a580b8c5SShawn Guo if (mxs_chan->status == DMA_SUCCESS) 300a580b8c5SShawn Guo mxs_chan->last_completed = mxs_chan->desc.cookie; 301a580b8c5SShawn Guo 302a580b8c5SShawn Guo /* schedule tasklet on this channel */ 303a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet); 304a580b8c5SShawn Guo } 305a580b8c5SShawn Guo 306a580b8c5SShawn Guo return IRQ_HANDLED; 307a580b8c5SShawn Guo } 308a580b8c5SShawn Guo 309a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 310a580b8c5SShawn Guo { 311a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 312a580b8c5SShawn Guo struct mxs_dma_data *data = chan->private; 313a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 314a580b8c5SShawn Guo int ret; 315a580b8c5SShawn Guo 316a580b8c5SShawn Guo if (!data) 317a580b8c5SShawn Guo return -EINVAL; 318a580b8c5SShawn Guo 319a580b8c5SShawn Guo mxs_chan->chan_irq = data->chan_irq; 320a580b8c5SShawn Guo 321a580b8c5SShawn Guo mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 322a580b8c5SShawn Guo &mxs_chan->ccw_phys, GFP_KERNEL); 323a580b8c5SShawn Guo if (!mxs_chan->ccw) { 324a580b8c5SShawn Guo ret = -ENOMEM; 325a580b8c5SShawn Guo goto err_alloc; 326a580b8c5SShawn Guo } 327a580b8c5SShawn Guo 328a580b8c5SShawn Guo memset(mxs_chan->ccw, 0, PAGE_SIZE); 329a580b8c5SShawn Guo 33095bfea16SShawn Guo if (mxs_chan->chan_irq != NO_IRQ) { 331a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 332a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma); 333a580b8c5SShawn Guo if (ret) 334a580b8c5SShawn Guo goto err_irq; 33595bfea16SShawn Guo } 336a580b8c5SShawn Guo 337a580b8c5SShawn Guo ret = clk_enable(mxs_dma->clk); 338a580b8c5SShawn Guo if (ret) 339a580b8c5SShawn Guo goto err_clk; 340a580b8c5SShawn Guo 341ef298c21SLothar Waßmann /* clkgate needs to be enabled for reset to finish */ 342ef298c21SLothar Waßmann mxs_dma_clkgate(mxs_chan, 1); 343a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 344ef298c21SLothar Waßmann mxs_dma_clkgate(mxs_chan, 0); 345a580b8c5SShawn Guo 346a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 347a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 348a580b8c5SShawn Guo 349a580b8c5SShawn Guo /* the descriptor is ready */ 350a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc); 351a580b8c5SShawn Guo 352a580b8c5SShawn Guo return 0; 353a580b8c5SShawn Guo 354a580b8c5SShawn Guo err_clk: 355a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 356a580b8c5SShawn Guo err_irq: 357a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 358a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 359a580b8c5SShawn Guo err_alloc: 360a580b8c5SShawn Guo return ret; 361a580b8c5SShawn Guo } 362a580b8c5SShawn Guo 363a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan) 364a580b8c5SShawn Guo { 365a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 366a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 367a580b8c5SShawn Guo 368a580b8c5SShawn Guo mxs_dma_disable_chan(mxs_chan); 369a580b8c5SShawn Guo 370a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 371a580b8c5SShawn Guo 372a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 373a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 374a580b8c5SShawn Guo 375a580b8c5SShawn Guo clk_disable(mxs_dma->clk); 376a580b8c5SShawn Guo } 377a580b8c5SShawn Guo 378a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 379a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl, 380a580b8c5SShawn Guo unsigned int sg_len, enum dma_data_direction direction, 381a580b8c5SShawn Guo unsigned long append) 382a580b8c5SShawn Guo { 383a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 384a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 385a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 386a580b8c5SShawn Guo struct scatterlist *sg; 387a580b8c5SShawn Guo int i, j; 388a580b8c5SShawn Guo u32 *pio; 389a580b8c5SShawn Guo static int idx; 390a580b8c5SShawn Guo 391a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS && !append) 392a580b8c5SShawn Guo return NULL; 393a580b8c5SShawn Guo 394a580b8c5SShawn Guo if (sg_len + (append ? idx : 0) > NUM_CCW) { 395a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 396a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 397a580b8c5SShawn Guo sg_len, NUM_CCW); 398a580b8c5SShawn Guo goto err_out; 399a580b8c5SShawn Guo } 400a580b8c5SShawn Guo 401a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 402a580b8c5SShawn Guo mxs_chan->flags = 0; 403a580b8c5SShawn Guo 404a580b8c5SShawn Guo /* 405a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg 406a580b8c5SShawn Guo * will be appended to the last prepared sg. 407a580b8c5SShawn Guo */ 408a580b8c5SShawn Guo if (append) { 409a580b8c5SShawn Guo BUG_ON(idx < 1); 410a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1]; 411a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 412a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 413a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ; 414a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM; 415a580b8c5SShawn Guo ccw->bits &= ~CCW_WAIT4END; 416a580b8c5SShawn Guo } else { 417a580b8c5SShawn Guo idx = 0; 418a580b8c5SShawn Guo } 419a580b8c5SShawn Guo 420a580b8c5SShawn Guo if (direction == DMA_NONE) { 421a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 422a580b8c5SShawn Guo pio = (u32 *) sgl; 423a580b8c5SShawn Guo 424a580b8c5SShawn Guo for (j = 0; j < sg_len;) 425a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++; 426a580b8c5SShawn Guo 427a580b8c5SShawn Guo ccw->bits = 0; 428a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 429a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 430a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 431a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 432a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 433a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM); 434a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 435a580b8c5SShawn Guo } else { 436a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) { 437a580b8c5SShawn Guo if (sg->length > MAX_XFER_BYTES) { 438a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 439a580b8c5SShawn Guo sg->length, MAX_XFER_BYTES); 440a580b8c5SShawn Guo goto err_out; 441a580b8c5SShawn Guo } 442a580b8c5SShawn Guo 443a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 444a580b8c5SShawn Guo 445a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 446a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address; 447a580b8c5SShawn Guo ccw->xfer_bytes = sg->length; 448a580b8c5SShawn Guo 449a580b8c5SShawn Guo ccw->bits = 0; 450a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 451a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 452a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 453a580b8c5SShawn Guo ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 454a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 455a580b8c5SShawn Guo COMMAND); 456a580b8c5SShawn Guo 457a580b8c5SShawn Guo if (i + 1 == sg_len) { 458a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN; 459a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 460a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 461a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 462a580b8c5SShawn Guo } 463a580b8c5SShawn Guo } 464a580b8c5SShawn Guo } 465a580b8c5SShawn Guo 466a580b8c5SShawn Guo return &mxs_chan->desc; 467a580b8c5SShawn Guo 468a580b8c5SShawn Guo err_out: 469a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 470a580b8c5SShawn Guo return NULL; 471a580b8c5SShawn Guo } 472a580b8c5SShawn Guo 473a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 474a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 475a580b8c5SShawn Guo size_t period_len, enum dma_data_direction direction) 476a580b8c5SShawn Guo { 477a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 478a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 479a580b8c5SShawn Guo int num_periods = buf_len / period_len; 480a580b8c5SShawn Guo int i = 0, buf = 0; 481a580b8c5SShawn Guo 482a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS) 483a580b8c5SShawn Guo return NULL; 484a580b8c5SShawn Guo 485a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 486a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP; 487a580b8c5SShawn Guo 488a580b8c5SShawn Guo if (num_periods > NUM_CCW) { 489a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 490a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 491a580b8c5SShawn Guo num_periods, NUM_CCW); 492a580b8c5SShawn Guo goto err_out; 493a580b8c5SShawn Guo } 494a580b8c5SShawn Guo 495a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) { 496a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 497a580b8c5SShawn Guo "maximum period size exceeded: %d > %d\n", 498a580b8c5SShawn Guo period_len, MAX_XFER_BYTES); 499a580b8c5SShawn Guo goto err_out; 500a580b8c5SShawn Guo } 501a580b8c5SShawn Guo 502a580b8c5SShawn Guo while (buf < buf_len) { 503a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 504a580b8c5SShawn Guo 505a580b8c5SShawn Guo if (i + 1 == num_periods) 506a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys; 507a580b8c5SShawn Guo else 508a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 509a580b8c5SShawn Guo 510a580b8c5SShawn Guo ccw->bufaddr = dma_addr; 511a580b8c5SShawn Guo ccw->xfer_bytes = period_len; 512a580b8c5SShawn Guo 513a580b8c5SShawn Guo ccw->bits = 0; 514a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 515a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 516a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 517a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 518a580b8c5SShawn Guo ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 519a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 520a580b8c5SShawn Guo 521a580b8c5SShawn Guo dma_addr += period_len; 522a580b8c5SShawn Guo buf += period_len; 523a580b8c5SShawn Guo 524a580b8c5SShawn Guo i++; 525a580b8c5SShawn Guo } 526a580b8c5SShawn Guo 527a580b8c5SShawn Guo return &mxs_chan->desc; 528a580b8c5SShawn Guo 529a580b8c5SShawn Guo err_out: 530a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 531a580b8c5SShawn Guo return NULL; 532a580b8c5SShawn Guo } 533a580b8c5SShawn Guo 534a580b8c5SShawn Guo static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 535a580b8c5SShawn Guo unsigned long arg) 536a580b8c5SShawn Guo { 537a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 538a580b8c5SShawn Guo int ret = 0; 539a580b8c5SShawn Guo 540a580b8c5SShawn Guo switch (cmd) { 541a580b8c5SShawn Guo case DMA_TERMINATE_ALL: 542a580b8c5SShawn Guo mxs_dma_disable_chan(mxs_chan); 543a62bae98SDong Aisheng mxs_dma_reset_chan(mxs_chan); 544a580b8c5SShawn Guo break; 545a580b8c5SShawn Guo case DMA_PAUSE: 546a580b8c5SShawn Guo mxs_dma_pause_chan(mxs_chan); 547a580b8c5SShawn Guo break; 548a580b8c5SShawn Guo case DMA_RESUME: 549a580b8c5SShawn Guo mxs_dma_resume_chan(mxs_chan); 550a580b8c5SShawn Guo break; 551a580b8c5SShawn Guo default: 552a580b8c5SShawn Guo ret = -ENOSYS; 553a580b8c5SShawn Guo } 554a580b8c5SShawn Guo 555a580b8c5SShawn Guo return ret; 556a580b8c5SShawn Guo } 557a580b8c5SShawn Guo 558a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 559a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate) 560a580b8c5SShawn Guo { 561a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 562a580b8c5SShawn Guo dma_cookie_t last_used; 563a580b8c5SShawn Guo 564a580b8c5SShawn Guo last_used = chan->cookie; 565a580b8c5SShawn Guo dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0); 566a580b8c5SShawn Guo 567a580b8c5SShawn Guo return mxs_chan->status; 568a580b8c5SShawn Guo } 569a580b8c5SShawn Guo 570a580b8c5SShawn Guo static void mxs_dma_issue_pending(struct dma_chan *chan) 571a580b8c5SShawn Guo { 572a580b8c5SShawn Guo /* 573a580b8c5SShawn Guo * Nothing to do. We only have a single descriptor. 574a580b8c5SShawn Guo */ 575a580b8c5SShawn Guo } 576a580b8c5SShawn Guo 577a580b8c5SShawn Guo static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 578a580b8c5SShawn Guo { 579a580b8c5SShawn Guo int ret; 580a580b8c5SShawn Guo 581a580b8c5SShawn Guo ret = clk_enable(mxs_dma->clk); 582a580b8c5SShawn Guo if (ret) 583a580b8c5SShawn Guo goto err_out; 584a580b8c5SShawn Guo 585a580b8c5SShawn Guo ret = mxs_reset_block(mxs_dma->base); 586a580b8c5SShawn Guo if (ret) 587a580b8c5SShawn Guo goto err_out; 588a580b8c5SShawn Guo 589a580b8c5SShawn Guo /* only major version matters */ 590a580b8c5SShawn Guo mxs_dma->version = readl(mxs_dma->base + 591a580b8c5SShawn Guo ((mxs_dma->dev_id == MXS_DMA_APBX) ? 592a580b8c5SShawn Guo HW_APBX_VERSION : HW_APBH_VERSION)) >> 593a580b8c5SShawn Guo BP_APBHX_VERSION_MAJOR; 594a580b8c5SShawn Guo 595a580b8c5SShawn Guo /* enable apbh burst */ 596a580b8c5SShawn Guo if (dma_is_apbh()) { 597a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN, 598a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 599a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN, 600a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 601a580b8c5SShawn Guo } 602a580b8c5SShawn Guo 603a580b8c5SShawn Guo /* enable irq for all the channels */ 604a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 605a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); 606a580b8c5SShawn Guo 607a580b8c5SShawn Guo clk_disable(mxs_dma->clk); 608a580b8c5SShawn Guo 609a580b8c5SShawn Guo return 0; 610a580b8c5SShawn Guo 611a580b8c5SShawn Guo err_out: 612a580b8c5SShawn Guo return ret; 613a580b8c5SShawn Guo } 614a580b8c5SShawn Guo 615a580b8c5SShawn Guo static int __init mxs_dma_probe(struct platform_device *pdev) 616a580b8c5SShawn Guo { 617a580b8c5SShawn Guo const struct platform_device_id *id_entry = 618a580b8c5SShawn Guo platform_get_device_id(pdev); 619a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 620a580b8c5SShawn Guo struct resource *iores; 621a580b8c5SShawn Guo int ret, i; 622a580b8c5SShawn Guo 623a580b8c5SShawn Guo mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); 624a580b8c5SShawn Guo if (!mxs_dma) 625a580b8c5SShawn Guo return -ENOMEM; 626a580b8c5SShawn Guo 627a580b8c5SShawn Guo mxs_dma->dev_id = id_entry->driver_data; 628a580b8c5SShawn Guo 629a580b8c5SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 630a580b8c5SShawn Guo 631a580b8c5SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 632a580b8c5SShawn Guo pdev->name)) { 633a580b8c5SShawn Guo ret = -EBUSY; 634a580b8c5SShawn Guo goto err_request_region; 635a580b8c5SShawn Guo } 636a580b8c5SShawn Guo 637a580b8c5SShawn Guo mxs_dma->base = ioremap(iores->start, resource_size(iores)); 638a580b8c5SShawn Guo if (!mxs_dma->base) { 639a580b8c5SShawn Guo ret = -ENOMEM; 640a580b8c5SShawn Guo goto err_ioremap; 641a580b8c5SShawn Guo } 642a580b8c5SShawn Guo 643a580b8c5SShawn Guo mxs_dma->clk = clk_get(&pdev->dev, NULL); 644a580b8c5SShawn Guo if (IS_ERR(mxs_dma->clk)) { 645a580b8c5SShawn Guo ret = PTR_ERR(mxs_dma->clk); 646a580b8c5SShawn Guo goto err_clk; 647a580b8c5SShawn Guo } 648a580b8c5SShawn Guo 649a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 650a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 651a580b8c5SShawn Guo 652a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 653a580b8c5SShawn Guo 654a580b8c5SShawn Guo /* Initialize channel parameters */ 655a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) { 656a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 657a580b8c5SShawn Guo 658a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma; 659a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device; 660a580b8c5SShawn Guo 661a580b8c5SShawn Guo tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 662a580b8c5SShawn Guo (unsigned long) mxs_chan); 663a580b8c5SShawn Guo 664a580b8c5SShawn Guo 665a580b8c5SShawn Guo /* Add the channel to mxs_chan list */ 666a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node, 667a580b8c5SShawn Guo &mxs_dma->dma_device.channels); 668a580b8c5SShawn Guo } 669a580b8c5SShawn Guo 670a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma); 671a580b8c5SShawn Guo if (ret) 672a580b8c5SShawn Guo goto err_init; 673a580b8c5SShawn Guo 674a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev; 675a580b8c5SShawn Guo 676a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */ 677a580b8c5SShawn Guo mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 678a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 679a580b8c5SShawn Guo 680a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 681a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 682a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 683a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 684a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 685a580b8c5SShawn Guo mxs_dma->dma_device.device_control = mxs_dma_control; 686a580b8c5SShawn Guo mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; 687a580b8c5SShawn Guo 688a580b8c5SShawn Guo ret = dma_async_device_register(&mxs_dma->dma_device); 689a580b8c5SShawn Guo if (ret) { 690a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 691a580b8c5SShawn Guo goto err_init; 692a580b8c5SShawn Guo } 693a580b8c5SShawn Guo 694a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n"); 695a580b8c5SShawn Guo 696a580b8c5SShawn Guo return 0; 697a580b8c5SShawn Guo 698a580b8c5SShawn Guo err_init: 699a580b8c5SShawn Guo clk_put(mxs_dma->clk); 700a580b8c5SShawn Guo err_clk: 701a580b8c5SShawn Guo iounmap(mxs_dma->base); 702a580b8c5SShawn Guo err_ioremap: 703a580b8c5SShawn Guo release_mem_region(iores->start, resource_size(iores)); 704a580b8c5SShawn Guo err_request_region: 705a580b8c5SShawn Guo kfree(mxs_dma); 706a580b8c5SShawn Guo return ret; 707a580b8c5SShawn Guo } 708a580b8c5SShawn Guo 709a580b8c5SShawn Guo static struct platform_device_id mxs_dma_type[] = { 710a580b8c5SShawn Guo { 711a580b8c5SShawn Guo .name = "mxs-dma-apbh", 712a580b8c5SShawn Guo .driver_data = MXS_DMA_APBH, 713a580b8c5SShawn Guo }, { 714a580b8c5SShawn Guo .name = "mxs-dma-apbx", 715a580b8c5SShawn Guo .driver_data = MXS_DMA_APBX, 7162a9778edSAxel Lin }, { 7172a9778edSAxel Lin /* end of list */ 718a580b8c5SShawn Guo } 719a580b8c5SShawn Guo }; 720a580b8c5SShawn Guo 721a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = { 722a580b8c5SShawn Guo .driver = { 723a580b8c5SShawn Guo .name = "mxs-dma", 724a580b8c5SShawn Guo }, 725a580b8c5SShawn Guo .id_table = mxs_dma_type, 726a580b8c5SShawn Guo }; 727a580b8c5SShawn Guo 728a580b8c5SShawn Guo static int __init mxs_dma_module_init(void) 729a580b8c5SShawn Guo { 730a580b8c5SShawn Guo return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 731a580b8c5SShawn Guo } 732a580b8c5SShawn Guo subsys_initcall(mxs_dma_module_init); 733