1d9617a3fSFabio Estevam // SPDX-License-Identifier: GPL-2.0 2d9617a3fSFabio Estevam // 3d9617a3fSFabio Estevam // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 4d9617a3fSFabio Estevam // 5d9617a3fSFabio Estevam // Refer to drivers/dma/imx-sdma.c 6a580b8c5SShawn Guo 7a580b8c5SShawn Guo #include <linux/init.h> 8a580b8c5SShawn Guo #include <linux/types.h> 9a580b8c5SShawn Guo #include <linux/mm.h> 10a580b8c5SShawn Guo #include <linux/interrupt.h> 11a580b8c5SShawn Guo #include <linux/clk.h> 12a580b8c5SShawn Guo #include <linux/wait.h> 13a580b8c5SShawn Guo #include <linux/sched.h> 14a580b8c5SShawn Guo #include <linux/semaphore.h> 15a580b8c5SShawn Guo #include <linux/device.h> 16a580b8c5SShawn Guo #include <linux/dma-mapping.h> 17a580b8c5SShawn Guo #include <linux/slab.h> 18a580b8c5SShawn Guo #include <linux/platform_device.h> 19a580b8c5SShawn Guo #include <linux/dmaengine.h> 20a580b8c5SShawn Guo #include <linux/delay.h> 2190c9abc5SDong Aisheng #include <linux/module.h> 22f5b7efccSDong Aisheng #include <linux/stmp_device.h> 2390c9abc5SDong Aisheng #include <linux/of.h> 2490c9abc5SDong Aisheng #include <linux/of_device.h> 25d84f638bSShawn Guo #include <linux/of_dma.h> 26b2d63989SMarkus Pargmann #include <linux/list.h> 27a580b8c5SShawn Guo 28a580b8c5SShawn Guo #include <asm/irq.h> 29a580b8c5SShawn Guo 30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 31d2ebfb33SRussell King - ARM Linux 32a580b8c5SShawn Guo /* 33a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means 34a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 35a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices. 36a580b8c5SShawn Guo */ 37a580b8c5SShawn Guo 388c920136SShawn Guo #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) 398c920136SShawn Guo #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) 40a580b8c5SShawn Guo 41a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000 42a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 43a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 44a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16 45a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010 46a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020 47a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030 48a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 49bb11fb63SShawn Guo /* 50bb11fb63SShawn Guo * The offset of NXTCMDAR register is different per both dma type and version, 51bb11fb63SShawn Guo * while stride for each channel is all the same 0x70. 52bb11fb63SShawn Guo */ 53bb11fb63SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(d, n) \ 54bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) 55bb11fb63SShawn Guo #define HW_APBHX_CHn_SEMA(d, n) \ 56bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) 577b11304aSMarkus Pargmann #define HW_APBHX_CHn_BAR(d, n) \ 587b11304aSMarkus Pargmann (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70) 59702e94d6SMarkus Pargmann #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70) 60a580b8c5SShawn Guo 61a580b8c5SShawn Guo /* 62a580b8c5SShawn Guo * ccw bits definitions 63a580b8c5SShawn Guo * 64a580b8c5SShawn Guo * COMMAND: 0..1 (2) 65a580b8c5SShawn Guo * CHAIN: 2 (1) 66a580b8c5SShawn Guo * IRQ: 3 (1) 67a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented 68a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented 69a580b8c5SShawn Guo * DEC_SEM: 6 (1) 70a580b8c5SShawn Guo * WAIT4END: 7 (1) 71a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1) 72a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1) 73a580b8c5SShawn Guo * RESERVED: 10..11 (2) 74a580b8c5SShawn Guo * PIO_NUM: 12..15 (4) 75a580b8c5SShawn Guo */ 76a580b8c5SShawn Guo #define BP_CCW_COMMAND 0 77a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0) 78a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2) 79a580b8c5SShawn Guo #define CCW_IRQ (1 << 3) 80a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6) 81a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7) 82a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8) 83a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9) 84a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12 85a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12) 86a580b8c5SShawn Guo 87a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 88a580b8c5SShawn Guo 89a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0 90a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1 91a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2 92a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 93a580b8c5SShawn Guo 94a580b8c5SShawn Guo struct mxs_dma_ccw { 95a580b8c5SShawn Guo u32 next; 96a580b8c5SShawn Guo u16 bits; 97a580b8c5SShawn Guo u16 xfer_bytes; 98a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00 99a580b8c5SShawn Guo u32 bufaddr; 100a580b8c5SShawn Guo #define MXS_PIO_WORDS 16 101a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS]; 102a580b8c5SShawn Guo }; 103a580b8c5SShawn Guo 1045e97fa91SMarek Vasut #define CCW_BLOCK_SIZE (4 * PAGE_SIZE) 1055e97fa91SMarek Vasut #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw)) 106a580b8c5SShawn Guo 107a580b8c5SShawn Guo struct mxs_dma_chan { 108a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 109a580b8c5SShawn Guo struct dma_chan chan; 110a580b8c5SShawn Guo struct dma_async_tx_descriptor desc; 111a580b8c5SShawn Guo struct tasklet_struct tasklet; 112f2ad6992SFabio Estevam unsigned int chan_irq; 113a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 114a580b8c5SShawn Guo dma_addr_t ccw_phys; 1156d23ea4bSLothar Waßmann int desc_count; 116a580b8c5SShawn Guo enum dma_status status; 117a580b8c5SShawn Guo unsigned int flags; 1182dcbdce3SMarkus Pargmann bool reset; 119a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0) 1202dcbdce3SMarkus Pargmann #define MXS_DMA_USE_SEMAPHORE (1 << 1) 121a580b8c5SShawn Guo }; 122a580b8c5SShawn Guo 123a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16 124a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff 125a580b8c5SShawn Guo 1268c920136SShawn Guo enum mxs_dma_devtype { 1278c920136SShawn Guo MXS_DMA_APBH, 1288c920136SShawn Guo MXS_DMA_APBX, 1298c920136SShawn Guo }; 1308c920136SShawn Guo 1318c920136SShawn Guo enum mxs_dma_id { 1328c920136SShawn Guo IMX23_DMA, 1338c920136SShawn Guo IMX28_DMA, 1348c920136SShawn Guo }; 1358c920136SShawn Guo 136a580b8c5SShawn Guo struct mxs_dma_engine { 1378c920136SShawn Guo enum mxs_dma_id dev_id; 1388c920136SShawn Guo enum mxs_dma_devtype type; 139a580b8c5SShawn Guo void __iomem *base; 140a580b8c5SShawn Guo struct clk *clk; 141a580b8c5SShawn Guo struct dma_device dma_device; 142a580b8c5SShawn Guo struct device_dma_parameters dma_parms; 143a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 144d84f638bSShawn Guo struct platform_device *pdev; 145d84f638bSShawn Guo unsigned int nr_channels; 146a580b8c5SShawn Guo }; 147a580b8c5SShawn Guo 1488c920136SShawn Guo struct mxs_dma_type { 1498c920136SShawn Guo enum mxs_dma_id id; 1508c920136SShawn Guo enum mxs_dma_devtype type; 1518c920136SShawn Guo }; 1528c920136SShawn Guo 1538c920136SShawn Guo static struct mxs_dma_type mxs_dma_types[] = { 1548c920136SShawn Guo { 1558c920136SShawn Guo .id = IMX23_DMA, 1568c920136SShawn Guo .type = MXS_DMA_APBH, 1578c920136SShawn Guo }, { 1588c920136SShawn Guo .id = IMX23_DMA, 1598c920136SShawn Guo .type = MXS_DMA_APBX, 1608c920136SShawn Guo }, { 1618c920136SShawn Guo .id = IMX28_DMA, 1628c920136SShawn Guo .type = MXS_DMA_APBH, 1638c920136SShawn Guo }, { 1648c920136SShawn Guo .id = IMX28_DMA, 1658c920136SShawn Guo .type = MXS_DMA_APBX, 1668c920136SShawn Guo } 1678c920136SShawn Guo }; 1688c920136SShawn Guo 1690d850504SKrzysztof Kozlowski static const struct platform_device_id mxs_dma_ids[] = { 1708c920136SShawn Guo { 1718c920136SShawn Guo .name = "imx23-dma-apbh", 1728c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[0], 1738c920136SShawn Guo }, { 1748c920136SShawn Guo .name = "imx23-dma-apbx", 1758c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[1], 1768c920136SShawn Guo }, { 1778c920136SShawn Guo .name = "imx28-dma-apbh", 1788c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[2], 1798c920136SShawn Guo }, { 1808c920136SShawn Guo .name = "imx28-dma-apbx", 1818c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[3], 1828c920136SShawn Guo }, { 1838c920136SShawn Guo /* end of list */ 1848c920136SShawn Guo } 1858c920136SShawn Guo }; 1868c920136SShawn Guo 18790c9abc5SDong Aisheng static const struct of_device_id mxs_dma_dt_ids[] = { 18890c9abc5SDong Aisheng { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], }, 18990c9abc5SDong Aisheng { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, 19090c9abc5SDong Aisheng { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, 19190c9abc5SDong Aisheng { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, 19290c9abc5SDong Aisheng { /* sentinel */ } 19390c9abc5SDong Aisheng }; 19490c9abc5SDong Aisheng MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); 19590c9abc5SDong Aisheng 1968c920136SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 1978c920136SShawn Guo { 1988c920136SShawn Guo return container_of(chan, struct mxs_dma_chan, chan); 1998c920136SShawn Guo } 2008c920136SShawn Guo 2015c9d2e37SMaxime Ripard static void mxs_dma_reset_chan(struct dma_chan *chan) 202a580b8c5SShawn Guo { 2035c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 204a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 205a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 206a580b8c5SShawn Guo 2072dcbdce3SMarkus Pargmann /* 2082dcbdce3SMarkus Pargmann * mxs dma channel resets can cause a channel stall. To recover from a 2092dcbdce3SMarkus Pargmann * channel stall, we have to reset the whole DMA engine. To avoid this, 2102dcbdce3SMarkus Pargmann * we use cyclic DMA with semaphores, that are enhanced in 2112dcbdce3SMarkus Pargmann * mxs_dma_int_handler. To reset the channel, we can simply stop writing 2122dcbdce3SMarkus Pargmann * into the semaphore counter. 2132dcbdce3SMarkus Pargmann */ 2142dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 2152dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 2162dcbdce3SMarkus Pargmann mxs_chan->reset = true; 2172dcbdce3SMarkus Pargmann } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) { 218a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 219f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 220702e94d6SMarkus Pargmann } else { 221702e94d6SMarkus Pargmann unsigned long elapsed = 0; 222702e94d6SMarkus Pargmann const unsigned long max_wait = 50000; /* 50ms */ 223702e94d6SMarkus Pargmann void __iomem *reg_dbg1 = mxs_dma->base + 224702e94d6SMarkus Pargmann HW_APBX_CHn_DEBUG1(mxs_dma, chan_id); 225702e94d6SMarkus Pargmann 226702e94d6SMarkus Pargmann /* 227702e94d6SMarkus Pargmann * On i.MX28 APBX, the DMA channel can stop working if we reset 228702e94d6SMarkus Pargmann * the channel while it is in READ_FLUSH (0x08) state. 229702e94d6SMarkus Pargmann * We wait here until we leave the state. Then we trigger the 230702e94d6SMarkus Pargmann * reset. Waiting a maximum of 50ms, the kernel shouldn't crash 231702e94d6SMarkus Pargmann * because of this. 232702e94d6SMarkus Pargmann */ 233702e94d6SMarkus Pargmann while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) { 234702e94d6SMarkus Pargmann udelay(100); 235702e94d6SMarkus Pargmann elapsed += 100; 236702e94d6SMarkus Pargmann } 237702e94d6SMarkus Pargmann 238702e94d6SMarkus Pargmann if (elapsed >= max_wait) 239702e94d6SMarkus Pargmann dev_err(&mxs_chan->mxs_dma->pdev->dev, 240702e94d6SMarkus Pargmann "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n", 241702e94d6SMarkus Pargmann chan_id); 242702e94d6SMarkus Pargmann 243a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 244f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 245a580b8c5SShawn Guo } 246bb3660f1SMarkus Pargmann 247bb3660f1SMarkus Pargmann mxs_chan->status = DMA_COMPLETE; 248702e94d6SMarkus Pargmann } 249a580b8c5SShawn Guo 2505c9d2e37SMaxime Ripard static void mxs_dma_enable_chan(struct dma_chan *chan) 251a580b8c5SShawn Guo { 2525c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 253a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 254a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 255a580b8c5SShawn Guo 256a580b8c5SShawn Guo /* set cmd_addr up */ 257a580b8c5SShawn Guo writel(mxs_chan->ccw_phys, 258bb11fb63SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); 259a580b8c5SShawn Guo 260a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */ 2612dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 2622dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 2632dcbdce3SMarkus Pargmann /* A cyclic DMA consists of at least 2 segments, so initialize 2642dcbdce3SMarkus Pargmann * the semaphore with 2 so we have enough time to add 1 to the 2652dcbdce3SMarkus Pargmann * semaphore if we need to */ 2662dcbdce3SMarkus Pargmann writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 2672dcbdce3SMarkus Pargmann } else { 268bb11fb63SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 269a580b8c5SShawn Guo } 2702dcbdce3SMarkus Pargmann mxs_chan->reset = false; 2712dcbdce3SMarkus Pargmann } 272a580b8c5SShawn Guo 2735c9d2e37SMaxime Ripard static void mxs_dma_disable_chan(struct dma_chan *chan) 274a580b8c5SShawn Guo { 2755c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 2765c9d2e37SMaxime Ripard 2772737583eSVinod Koul mxs_chan->status = DMA_COMPLETE; 278a580b8c5SShawn Guo } 279a580b8c5SShawn Guo 280a29c3956SVinod Koul static int mxs_dma_pause_chan(struct dma_chan *chan) 281a580b8c5SShawn Guo { 2825c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 283a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 284a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 285a580b8c5SShawn Guo 286a580b8c5SShawn Guo /* freeze the channel */ 287bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 288a580b8c5SShawn Guo writel(1 << chan_id, 289f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 290a580b8c5SShawn Guo else 291a580b8c5SShawn Guo writel(1 << chan_id, 292f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 293a580b8c5SShawn Guo 294a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED; 295a29c3956SVinod Koul return 0; 296a580b8c5SShawn Guo } 297a580b8c5SShawn Guo 298a29c3956SVinod Koul static int mxs_dma_resume_chan(struct dma_chan *chan) 299a580b8c5SShawn Guo { 3005c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 301a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 302a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 303a580b8c5SShawn Guo 304a580b8c5SShawn Guo /* unfreeze the channel */ 305bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 306a580b8c5SShawn Guo writel(1 << chan_id, 307f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); 308a580b8c5SShawn Guo else 309a580b8c5SShawn Guo writel(1 << chan_id, 310f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); 311a580b8c5SShawn Guo 312a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 313a29c3956SVinod Koul return 0; 314a580b8c5SShawn Guo } 315a580b8c5SShawn Guo 316a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 317a580b8c5SShawn Guo { 318884485e1SRussell King - ARM Linux return dma_cookie_assign(tx); 319a580b8c5SShawn Guo } 320a580b8c5SShawn Guo 321a580b8c5SShawn Guo static void mxs_dma_tasklet(unsigned long data) 322a580b8c5SShawn Guo { 323a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 324a580b8c5SShawn Guo 325064370c6SDave Jiang dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL); 326a580b8c5SShawn Guo } 327a580b8c5SShawn Guo 328b2d63989SMarkus Pargmann static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq) 329b2d63989SMarkus Pargmann { 330b2d63989SMarkus Pargmann int i; 331b2d63989SMarkus Pargmann 332b2d63989SMarkus Pargmann for (i = 0; i != mxs_dma->nr_channels; ++i) 333b2d63989SMarkus Pargmann if (mxs_dma->mxs_chans[i].chan_irq == irq) 334b2d63989SMarkus Pargmann return i; 335b2d63989SMarkus Pargmann 336b2d63989SMarkus Pargmann return -EINVAL; 337b2d63989SMarkus Pargmann } 338b2d63989SMarkus Pargmann 339a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 340a580b8c5SShawn Guo { 341a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id; 342b2d63989SMarkus Pargmann struct mxs_dma_chan *mxs_chan; 343b2d63989SMarkus Pargmann u32 completed; 344b2d63989SMarkus Pargmann u32 err; 345b2d63989SMarkus Pargmann int chan = mxs_dma_irq_to_chan(mxs_dma, irq); 346b2d63989SMarkus Pargmann 347b2d63989SMarkus Pargmann if (chan < 0) 348b2d63989SMarkus Pargmann return IRQ_NONE; 349a580b8c5SShawn Guo 350a580b8c5SShawn Guo /* completion status */ 351b2d63989SMarkus Pargmann completed = readl(mxs_dma->base + HW_APBHX_CTRL1); 352b2d63989SMarkus Pargmann completed = (completed >> chan) & 0x1; 353b2d63989SMarkus Pargmann 354b2d63989SMarkus Pargmann /* Clear interrupt */ 355b2d63989SMarkus Pargmann writel((1 << chan), 356b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); 357a580b8c5SShawn Guo 358a580b8c5SShawn Guo /* error status */ 359b2d63989SMarkus Pargmann err = readl(mxs_dma->base + HW_APBHX_CTRL2); 360b2d63989SMarkus Pargmann err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan); 361b2d63989SMarkus Pargmann 362b2d63989SMarkus Pargmann /* 363b2d63989SMarkus Pargmann * error status bit is in the upper 16 bits, error irq bit in the lower 364b2d63989SMarkus Pargmann * 16 bits. We transform it into a simpler error code: 365b2d63989SMarkus Pargmann * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR 366b2d63989SMarkus Pargmann */ 367b2d63989SMarkus Pargmann err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan); 368b2d63989SMarkus Pargmann 369b2d63989SMarkus Pargmann /* Clear error irq */ 370b2d63989SMarkus Pargmann writel((1 << chan), 371b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); 372a580b8c5SShawn Guo 373a580b8c5SShawn Guo /* 374a580b8c5SShawn Guo * When both completion and error of termination bits set at the 375a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes 376b2d63989SMarkus Pargmann * an error we need to handle here in case of either it's a bus 377b2d63989SMarkus Pargmann * error or a termination error with no completion. 0x01 is termination 378b2d63989SMarkus Pargmann * error, so we can subtract err & completed to get the real error case. 379a580b8c5SShawn Guo */ 380b2d63989SMarkus Pargmann err -= err & completed; 381a580b8c5SShawn Guo 382b2d63989SMarkus Pargmann mxs_chan = &mxs_dma->mxs_chans[chan]; 383a580b8c5SShawn Guo 384b2d63989SMarkus Pargmann if (err) { 385a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev, 386a580b8c5SShawn Guo "%s: error in channel %d\n", __func__, 387b2d63989SMarkus Pargmann chan); 388a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 389e0cad7a0SVinod Koul mxs_dma_reset_chan(&mxs_chan->chan); 390bb3660f1SMarkus Pargmann } else if (mxs_chan->status != DMA_COMPLETE) { 3912dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_SG_LOOP) { 392a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 3932dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE) 3942dcbdce3SMarkus Pargmann writel(1, mxs_dma->base + 3952dcbdce3SMarkus Pargmann HW_APBHX_CHn_SEMA(mxs_dma, chan)); 3962dcbdce3SMarkus Pargmann } else { 3972737583eSVinod Koul mxs_chan->status = DMA_COMPLETE; 398a580b8c5SShawn Guo } 3992dcbdce3SMarkus Pargmann } 400a580b8c5SShawn Guo 4012dcbdce3SMarkus Pargmann if (mxs_chan->status == DMA_COMPLETE) { 4022dcbdce3SMarkus Pargmann if (mxs_chan->reset) 4032dcbdce3SMarkus Pargmann return IRQ_HANDLED; 404f7fbce07SRussell King - ARM Linux dma_cookie_complete(&mxs_chan->desc); 4052dcbdce3SMarkus Pargmann } 406a580b8c5SShawn Guo 407a580b8c5SShawn Guo /* schedule tasklet on this channel */ 408a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet); 409a580b8c5SShawn Guo 410a580b8c5SShawn Guo return IRQ_HANDLED; 411a580b8c5SShawn Guo } 412a580b8c5SShawn Guo 413a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 414a580b8c5SShawn Guo { 415a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 416a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 417a580b8c5SShawn Guo int ret; 418a580b8c5SShawn Guo 419750afb08SLuis Chamberlain mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, 4209f92d223SJoe Perches CCW_BLOCK_SIZE, 4219f92d223SJoe Perches &mxs_chan->ccw_phys, GFP_KERNEL); 422a580b8c5SShawn Guo if (!mxs_chan->ccw) { 423a580b8c5SShawn Guo ret = -ENOMEM; 424a580b8c5SShawn Guo goto err_alloc; 425a580b8c5SShawn Guo } 426a580b8c5SShawn Guo 427a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 428a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma); 429a580b8c5SShawn Guo if (ret) 430a580b8c5SShawn Guo goto err_irq; 431a580b8c5SShawn Guo 432759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 433a580b8c5SShawn Guo if (ret) 434a580b8c5SShawn Guo goto err_clk; 435a580b8c5SShawn Guo 4365c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan); 437a580b8c5SShawn Guo 438a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 439a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 440a580b8c5SShawn Guo 441a580b8c5SShawn Guo /* the descriptor is ready */ 442a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc); 443a580b8c5SShawn Guo 444a580b8c5SShawn Guo return 0; 445a580b8c5SShawn Guo 446a580b8c5SShawn Guo err_clk: 447a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 448a580b8c5SShawn Guo err_irq: 4495e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 450a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 451a580b8c5SShawn Guo err_alloc: 452a580b8c5SShawn Guo return ret; 453a580b8c5SShawn Guo } 454a580b8c5SShawn Guo 455a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan) 456a580b8c5SShawn Guo { 457a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 458a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 459a580b8c5SShawn Guo 4605c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan); 461a580b8c5SShawn Guo 462a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 463a580b8c5SShawn Guo 4645e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 465a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 466a580b8c5SShawn Guo 467759a2e30SShawn Guo clk_disable_unprepare(mxs_dma->clk); 468a580b8c5SShawn Guo } 469a580b8c5SShawn Guo 470921de864SHuang Shijie /* 471921de864SHuang Shijie * How to use the flags for ->device_prep_slave_sg() : 472921de864SHuang Shijie * [1] If there is only one DMA command in the DMA chain, the code should be: 473921de864SHuang Shijie * ...... 474921de864SHuang Shijie * ->device_prep_slave_sg(DMA_CTRL_ACK); 475921de864SHuang Shijie * ...... 476921de864SHuang Shijie * [2] If there are two DMA commands in the DMA chain, the code should be 477921de864SHuang Shijie * ...... 478921de864SHuang Shijie * ->device_prep_slave_sg(0); 479921de864SHuang Shijie * ...... 480d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK); 481921de864SHuang Shijie * ...... 482921de864SHuang Shijie * [3] If there are more than two DMA commands in the DMA chain, the code 483921de864SHuang Shijie * should be: 484921de864SHuang Shijie * ...... 485921de864SHuang Shijie * ->device_prep_slave_sg(0); // First 486921de864SHuang Shijie * ...... 487d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK]); 488921de864SHuang Shijie * ...... 489d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last 490921de864SHuang Shijie * ...... 491921de864SHuang Shijie */ 492a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 493a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl, 494db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 495623ff773SLinus Torvalds unsigned long flags, void *context) 496a580b8c5SShawn Guo { 497a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 498a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 499a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 500a580b8c5SShawn Guo struct scatterlist *sg; 501f2ad6992SFabio Estevam u32 i, j; 502a580b8c5SShawn Guo u32 *pio; 503d443cb25SSascha Hauer int idx = 0; 504a580b8c5SShawn Guo 505d443cb25SSascha Hauer if (mxs_chan->status == DMA_IN_PROGRESS) 506d443cb25SSascha Hauer idx = mxs_chan->desc_count; 507a580b8c5SShawn Guo 508d443cb25SSascha Hauer if (sg_len + idx > NUM_CCW) { 509a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 510a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 511a580b8c5SShawn Guo sg_len, NUM_CCW); 512a580b8c5SShawn Guo goto err_out; 513a580b8c5SShawn Guo } 514a580b8c5SShawn Guo 515a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 516a580b8c5SShawn Guo mxs_chan->flags = 0; 517a580b8c5SShawn Guo 518a580b8c5SShawn Guo /* 519a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg 520a580b8c5SShawn Guo * will be appended to the last prepared sg. 521a580b8c5SShawn Guo */ 522d443cb25SSascha Hauer if (idx) { 523a580b8c5SShawn Guo BUG_ON(idx < 1); 524a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1]; 525a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 526a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 527a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ; 528a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM; 529a580b8c5SShawn Guo } else { 530a580b8c5SShawn Guo idx = 0; 531a580b8c5SShawn Guo } 532a580b8c5SShawn Guo 53362268ce9SShawn Guo if (direction == DMA_TRANS_NONE) { 534a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 535a580b8c5SShawn Guo pio = (u32 *) sgl; 536a580b8c5SShawn Guo 537a580b8c5SShawn Guo for (j = 0; j < sg_len;) 538a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++; 539a580b8c5SShawn Guo 540a580b8c5SShawn Guo ccw->bits = 0; 541a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 542a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 543921de864SHuang Shijie if (flags & DMA_CTRL_ACK) 544a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 545a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 546a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 547a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM); 548a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 549a580b8c5SShawn Guo } else { 550a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) { 551fdaf9c4bSLars-Peter Clausen if (sg_dma_len(sg) > MAX_XFER_BYTES) { 552a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 553fdaf9c4bSLars-Peter Clausen sg_dma_len(sg), MAX_XFER_BYTES); 554a580b8c5SShawn Guo goto err_out; 555a580b8c5SShawn Guo } 556a580b8c5SShawn Guo 557a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 558a580b8c5SShawn Guo 559a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 560a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address; 561fdaf9c4bSLars-Peter Clausen ccw->xfer_bytes = sg_dma_len(sg); 562a580b8c5SShawn Guo 563a580b8c5SShawn Guo ccw->bits = 0; 564a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 565a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 566a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 567db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 568a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 569a580b8c5SShawn Guo COMMAND); 570a580b8c5SShawn Guo 571a580b8c5SShawn Guo if (i + 1 == sg_len) { 572a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN; 573a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 574a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 575921de864SHuang Shijie if (flags & DMA_CTRL_ACK) 576a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 577a580b8c5SShawn Guo } 578a580b8c5SShawn Guo } 579a580b8c5SShawn Guo } 5806d23ea4bSLothar Waßmann mxs_chan->desc_count = idx; 581a580b8c5SShawn Guo 582a580b8c5SShawn Guo return &mxs_chan->desc; 583a580b8c5SShawn Guo 584a580b8c5SShawn Guo err_out: 585a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 586a580b8c5SShawn Guo return NULL; 587a580b8c5SShawn Guo } 588a580b8c5SShawn Guo 589a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 590a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 591185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 59231c1e5a1SLaurent Pinchart unsigned long flags) 593a580b8c5SShawn Guo { 594a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 595a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 596f2ad6992SFabio Estevam u32 num_periods = buf_len / period_len; 597f2ad6992SFabio Estevam u32 i = 0, buf = 0; 598a580b8c5SShawn Guo 599a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS) 600a580b8c5SShawn Guo return NULL; 601a580b8c5SShawn Guo 602a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 603a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP; 6042dcbdce3SMarkus Pargmann mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE; 605a580b8c5SShawn Guo 606a580b8c5SShawn Guo if (num_periods > NUM_CCW) { 607a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 608a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 609a580b8c5SShawn Guo num_periods, NUM_CCW); 610a580b8c5SShawn Guo goto err_out; 611a580b8c5SShawn Guo } 612a580b8c5SShawn Guo 613a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) { 614a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 6154aff2f93SFabio Estevam "maximum period size exceeded: %zu > %d\n", 616a580b8c5SShawn Guo period_len, MAX_XFER_BYTES); 617a580b8c5SShawn Guo goto err_out; 618a580b8c5SShawn Guo } 619a580b8c5SShawn Guo 620a580b8c5SShawn Guo while (buf < buf_len) { 621a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 622a580b8c5SShawn Guo 623a580b8c5SShawn Guo if (i + 1 == num_periods) 624a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys; 625a580b8c5SShawn Guo else 626a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 627a580b8c5SShawn Guo 628a580b8c5SShawn Guo ccw->bufaddr = dma_addr; 629a580b8c5SShawn Guo ccw->xfer_bytes = period_len; 630a580b8c5SShawn Guo 631a580b8c5SShawn Guo ccw->bits = 0; 632a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 633a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 634a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 635a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 6362dcbdce3SMarkus Pargmann ccw->bits |= CCW_DEC_SEM; 637db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 638a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 639a580b8c5SShawn Guo 640a580b8c5SShawn Guo dma_addr += period_len; 641a580b8c5SShawn Guo buf += period_len; 642a580b8c5SShawn Guo 643a580b8c5SShawn Guo i++; 644a580b8c5SShawn Guo } 6456d23ea4bSLothar Waßmann mxs_chan->desc_count = i; 646a580b8c5SShawn Guo 647a580b8c5SShawn Guo return &mxs_chan->desc; 648a580b8c5SShawn Guo 649a580b8c5SShawn Guo err_out: 650a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 651a580b8c5SShawn Guo return NULL; 652a580b8c5SShawn Guo } 653a580b8c5SShawn Guo 6545c9d2e37SMaxime Ripard static int mxs_dma_terminate_all(struct dma_chan *chan) 655a580b8c5SShawn Guo { 6565c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan); 6575c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan); 658a580b8c5SShawn Guo 6595c9d2e37SMaxime Ripard return 0; 660a580b8c5SShawn Guo } 661a580b8c5SShawn Guo 662a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 663a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate) 664a580b8c5SShawn Guo { 665a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 6667b11304aSMarkus Pargmann struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 6677b11304aSMarkus Pargmann u32 residue = 0; 668a580b8c5SShawn Guo 6697b11304aSMarkus Pargmann if (mxs_chan->status == DMA_IN_PROGRESS && 6707b11304aSMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 6717b11304aSMarkus Pargmann struct mxs_dma_ccw *last_ccw; 6727b11304aSMarkus Pargmann u32 bar; 6737b11304aSMarkus Pargmann 6747b11304aSMarkus Pargmann last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1]; 6757b11304aSMarkus Pargmann residue = last_ccw->xfer_bytes + last_ccw->bufaddr; 6767b11304aSMarkus Pargmann 6777b11304aSMarkus Pargmann bar = readl(mxs_dma->base + 6787b11304aSMarkus Pargmann HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id)); 6797b11304aSMarkus Pargmann residue -= bar; 6807b11304aSMarkus Pargmann } 6817b11304aSMarkus Pargmann 6827b11304aSMarkus Pargmann dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 6837b11304aSMarkus Pargmann residue); 684a580b8c5SShawn Guo 685a580b8c5SShawn Guo return mxs_chan->status; 686a580b8c5SShawn Guo } 687a580b8c5SShawn Guo 688a580b8c5SShawn Guo static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 689a580b8c5SShawn Guo { 690a580b8c5SShawn Guo int ret; 691a580b8c5SShawn Guo 692759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 693a580b8c5SShawn Guo if (ret) 694feb397deSLothar Waßmann return ret; 695a580b8c5SShawn Guo 696f5b7efccSDong Aisheng ret = stmp_reset_block(mxs_dma->base); 697a580b8c5SShawn Guo if (ret) 698a580b8c5SShawn Guo goto err_out; 699a580b8c5SShawn Guo 700a580b8c5SShawn Guo /* enable apbh burst */ 701bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma)) { 702a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN, 703f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 704a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN, 705f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 706a580b8c5SShawn Guo } 707a580b8c5SShawn Guo 708a580b8c5SShawn Guo /* enable irq for all the channels */ 709a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 710f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); 711a580b8c5SShawn Guo 712a580b8c5SShawn Guo err_out: 71357f2685cSLinus Torvalds clk_disable_unprepare(mxs_dma->clk); 714a580b8c5SShawn Guo return ret; 715a580b8c5SShawn Guo } 716a580b8c5SShawn Guo 717d84f638bSShawn Guo struct mxs_dma_filter_param { 718d84f638bSShawn Guo struct device_node *of_node; 719d84f638bSShawn Guo unsigned int chan_id; 720d84f638bSShawn Guo }; 721d84f638bSShawn Guo 722d84f638bSShawn Guo static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) 723d84f638bSShawn Guo { 724d84f638bSShawn Guo struct mxs_dma_filter_param *param = fn_param; 725d84f638bSShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 726d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 727d84f638bSShawn Guo int chan_irq; 728d84f638bSShawn Guo 729d84f638bSShawn Guo if (mxs_dma->dma_device.dev->of_node != param->of_node) 730d84f638bSShawn Guo return false; 731d84f638bSShawn Guo 732d84f638bSShawn Guo if (chan->chan_id != param->chan_id) 733d84f638bSShawn Guo return false; 734d84f638bSShawn Guo 735d84f638bSShawn Guo chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id); 736d84f638bSShawn Guo if (chan_irq < 0) 737d84f638bSShawn Guo return false; 738d84f638bSShawn Guo 739d84f638bSShawn Guo mxs_chan->chan_irq = chan_irq; 740d84f638bSShawn Guo 741d84f638bSShawn Guo return true; 742d84f638bSShawn Guo } 743d84f638bSShawn Guo 7443208b370SFabio Estevam static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, 745d84f638bSShawn Guo struct of_dma *ofdma) 746d84f638bSShawn Guo { 747d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data; 748d84f638bSShawn Guo dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; 749d84f638bSShawn Guo struct mxs_dma_filter_param param; 750d84f638bSShawn Guo 751d84f638bSShawn Guo if (dma_spec->args_count != 1) 752d84f638bSShawn Guo return NULL; 753d84f638bSShawn Guo 754d84f638bSShawn Guo param.of_node = ofdma->of_node; 755d84f638bSShawn Guo param.chan_id = dma_spec->args[0]; 756d84f638bSShawn Guo 757d84f638bSShawn Guo if (param.chan_id >= mxs_dma->nr_channels) 758d84f638bSShawn Guo return NULL; 759d84f638bSShawn Guo 760d84f638bSShawn Guo return dma_request_channel(mask, mxs_dma_filter_fn, ¶m); 761d84f638bSShawn Guo } 762d84f638bSShawn Guo 763a580b8c5SShawn Guo static int __init mxs_dma_probe(struct platform_device *pdev) 764a580b8c5SShawn Guo { 765d84f638bSShawn Guo struct device_node *np = pdev->dev.of_node; 76690c9abc5SDong Aisheng const struct platform_device_id *id_entry; 76790c9abc5SDong Aisheng const struct of_device_id *of_id; 76890c9abc5SDong Aisheng const struct mxs_dma_type *dma_type; 769a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 770a580b8c5SShawn Guo struct resource *iores; 771a580b8c5SShawn Guo int ret, i; 772a580b8c5SShawn Guo 773aaa20517SShawn Guo mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); 774a580b8c5SShawn Guo if (!mxs_dma) 775a580b8c5SShawn Guo return -ENOMEM; 776a580b8c5SShawn Guo 777d84f638bSShawn Guo ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); 778d84f638bSShawn Guo if (ret) { 779d84f638bSShawn Guo dev_err(&pdev->dev, "failed to read dma-channels\n"); 780d84f638bSShawn Guo return ret; 781d84f638bSShawn Guo } 782d84f638bSShawn Guo 78390c9abc5SDong Aisheng of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev); 78490c9abc5SDong Aisheng if (of_id) 78590c9abc5SDong Aisheng id_entry = of_id->data; 78690c9abc5SDong Aisheng else 78790c9abc5SDong Aisheng id_entry = platform_get_device_id(pdev); 78890c9abc5SDong Aisheng 78990c9abc5SDong Aisheng dma_type = (struct mxs_dma_type *)id_entry->driver_data; 7908c920136SShawn Guo mxs_dma->type = dma_type->type; 79190c9abc5SDong Aisheng mxs_dma->dev_id = dma_type->id; 792a580b8c5SShawn Guo 793a580b8c5SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794aaa20517SShawn Guo mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); 795aaa20517SShawn Guo if (IS_ERR(mxs_dma->base)) 796aaa20517SShawn Guo return PTR_ERR(mxs_dma->base); 797a580b8c5SShawn Guo 798aaa20517SShawn Guo mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); 799aaa20517SShawn Guo if (IS_ERR(mxs_dma->clk)) 800aaa20517SShawn Guo return PTR_ERR(mxs_dma->clk); 801a580b8c5SShawn Guo 802a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 803a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 804a580b8c5SShawn Guo 805a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 806a580b8c5SShawn Guo 807a580b8c5SShawn Guo /* Initialize channel parameters */ 808a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) { 809a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 810a580b8c5SShawn Guo 811a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma; 812a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device; 8138ac69546SRussell King - ARM Linux dma_cookie_init(&mxs_chan->chan); 814a580b8c5SShawn Guo 815a580b8c5SShawn Guo tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 816a580b8c5SShawn Guo (unsigned long) mxs_chan); 817a580b8c5SShawn Guo 818a580b8c5SShawn Guo 819a580b8c5SShawn Guo /* Add the channel to mxs_chan list */ 820a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node, 821a580b8c5SShawn Guo &mxs_dma->dma_device.channels); 822a580b8c5SShawn Guo } 823a580b8c5SShawn Guo 824a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma); 825a580b8c5SShawn Guo if (ret) 826aaa20517SShawn Guo return ret; 827a580b8c5SShawn Guo 828d84f638bSShawn Guo mxs_dma->pdev = pdev; 829a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev; 830a580b8c5SShawn Guo 831a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */ 832a580b8c5SShawn Guo mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 833a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 834a580b8c5SShawn Guo 835a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 836a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 837a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 838a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 839a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 8405c9d2e37SMaxime Ripard mxs_dma->dma_device.device_pause = mxs_dma_pause_chan; 8415c9d2e37SMaxime Ripard mxs_dma->dma_device.device_resume = mxs_dma_resume_chan; 8425c9d2e37SMaxime Ripard mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all; 843ef9d2a92SFabio Estevam mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 844ef9d2a92SFabio Estevam mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 845ef9d2a92SFabio Estevam mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 846ef9d2a92SFabio Estevam mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 8475c9d2e37SMaxime Ripard mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan; 848a580b8c5SShawn Guo 849fbb69eceSHuang Shijie ret = dmaenginem_async_device_register(&mxs_dma->dma_device); 850a580b8c5SShawn Guo if (ret) { 851a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 852aaa20517SShawn Guo return ret; 853a580b8c5SShawn Guo } 854a580b8c5SShawn Guo 855d84f638bSShawn Guo ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); 856d84f638bSShawn Guo if (ret) { 857d84f638bSShawn Guo dev_err(mxs_dma->dma_device.dev, 858d84f638bSShawn Guo "failed to register controller\n"); 859d84f638bSShawn Guo } 860d84f638bSShawn Guo 861a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n"); 862a580b8c5SShawn Guo 863a580b8c5SShawn Guo return 0; 864a580b8c5SShawn Guo } 865a580b8c5SShawn Guo 866a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = { 867a580b8c5SShawn Guo .driver = { 868a580b8c5SShawn Guo .name = "mxs-dma", 86990c9abc5SDong Aisheng .of_match_table = mxs_dma_dt_ids, 870a580b8c5SShawn Guo }, 8718c920136SShawn Guo .id_table = mxs_dma_ids, 872a580b8c5SShawn Guo }; 873a580b8c5SShawn Guo 874a580b8c5SShawn Guo static int __init mxs_dma_module_init(void) 875a580b8c5SShawn Guo { 876a580b8c5SShawn Guo return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 877a580b8c5SShawn Guo } 878a580b8c5SShawn Guo subsys_initcall(mxs_dma_module_init); 879