1a580b8c5SShawn Guo /* 2a580b8c5SShawn Guo * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3a580b8c5SShawn Guo * 4a580b8c5SShawn Guo * Refer to drivers/dma/imx-sdma.c 5a580b8c5SShawn Guo * 6a580b8c5SShawn Guo * This program is free software; you can redistribute it and/or modify 7a580b8c5SShawn Guo * it under the terms of the GNU General Public License version 2 as 8a580b8c5SShawn Guo * published by the Free Software Foundation. 9a580b8c5SShawn Guo */ 10a580b8c5SShawn Guo 11a580b8c5SShawn Guo #include <linux/init.h> 12a580b8c5SShawn Guo #include <linux/types.h> 13a580b8c5SShawn Guo #include <linux/mm.h> 14a580b8c5SShawn Guo #include <linux/interrupt.h> 15a580b8c5SShawn Guo #include <linux/clk.h> 16a580b8c5SShawn Guo #include <linux/wait.h> 17a580b8c5SShawn Guo #include <linux/sched.h> 18a580b8c5SShawn Guo #include <linux/semaphore.h> 19a580b8c5SShawn Guo #include <linux/device.h> 20a580b8c5SShawn Guo #include <linux/dma-mapping.h> 21a580b8c5SShawn Guo #include <linux/slab.h> 22a580b8c5SShawn Guo #include <linux/platform_device.h> 23a580b8c5SShawn Guo #include <linux/dmaengine.h> 24a580b8c5SShawn Guo #include <linux/delay.h> 25a580b8c5SShawn Guo 26a580b8c5SShawn Guo #include <asm/irq.h> 27a580b8c5SShawn Guo #include <mach/mxs.h> 28a580b8c5SShawn Guo #include <mach/dma.h> 29a580b8c5SShawn Guo #include <mach/common.h> 30a580b8c5SShawn Guo 31a580b8c5SShawn Guo /* 32a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means 33a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 34a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices. 35a580b8c5SShawn Guo */ 36a580b8c5SShawn Guo 37a580b8c5SShawn Guo #define MXS_DMA_APBH 0 38a580b8c5SShawn Guo #define MXS_DMA_APBX 1 39a580b8c5SShawn Guo #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) 40a580b8c5SShawn Guo 41a580b8c5SShawn Guo #define APBH_VERSION_LATEST 3 42a580b8c5SShawn Guo #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) 43a580b8c5SShawn Guo 44a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000 45a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 46a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 47a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16 48a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010 49a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020 50a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030 51a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 52a580b8c5SShawn Guo #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) 53a580b8c5SShawn Guo #define HW_APBX_VERSION 0x800 54a580b8c5SShawn Guo #define BP_APBHX_VERSION_MAJOR 24 55a580b8c5SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(n) \ 56a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) 57a580b8c5SShawn Guo #define HW_APBHX_CHn_SEMA(n) \ 58a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) 59a580b8c5SShawn Guo 60a580b8c5SShawn Guo /* 61a580b8c5SShawn Guo * ccw bits definitions 62a580b8c5SShawn Guo * 63a580b8c5SShawn Guo * COMMAND: 0..1 (2) 64a580b8c5SShawn Guo * CHAIN: 2 (1) 65a580b8c5SShawn Guo * IRQ: 3 (1) 66a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented 67a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented 68a580b8c5SShawn Guo * DEC_SEM: 6 (1) 69a580b8c5SShawn Guo * WAIT4END: 7 (1) 70a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1) 71a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1) 72a580b8c5SShawn Guo * RESERVED: 10..11 (2) 73a580b8c5SShawn Guo * PIO_NUM: 12..15 (4) 74a580b8c5SShawn Guo */ 75a580b8c5SShawn Guo #define BP_CCW_COMMAND 0 76a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0) 77a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2) 78a580b8c5SShawn Guo #define CCW_IRQ (1 << 3) 79a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6) 80a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7) 81a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8) 82a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9) 83a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12 84a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12) 85a580b8c5SShawn Guo 86a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 87a580b8c5SShawn Guo 88a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0 89a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1 90a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2 91a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 92a580b8c5SShawn Guo 93a580b8c5SShawn Guo struct mxs_dma_ccw { 94a580b8c5SShawn Guo u32 next; 95a580b8c5SShawn Guo u16 bits; 96a580b8c5SShawn Guo u16 xfer_bytes; 97a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00 98a580b8c5SShawn Guo u32 bufaddr; 99a580b8c5SShawn Guo #define MXS_PIO_WORDS 16 100a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS]; 101a580b8c5SShawn Guo }; 102a580b8c5SShawn Guo 103a580b8c5SShawn Guo #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) 104a580b8c5SShawn Guo 105a580b8c5SShawn Guo struct mxs_dma_chan { 106a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 107a580b8c5SShawn Guo struct dma_chan chan; 108a580b8c5SShawn Guo struct dma_async_tx_descriptor desc; 109a580b8c5SShawn Guo struct tasklet_struct tasklet; 110a580b8c5SShawn Guo int chan_irq; 111a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 112a580b8c5SShawn Guo dma_addr_t ccw_phys; 1136d23ea4bSLothar Waßmann int desc_count; 114a580b8c5SShawn Guo dma_cookie_t last_completed; 115a580b8c5SShawn Guo enum dma_status status; 116a580b8c5SShawn Guo unsigned int flags; 117a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0) 118a580b8c5SShawn Guo }; 119a580b8c5SShawn Guo 120a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16 121a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff 122a580b8c5SShawn Guo 123a580b8c5SShawn Guo struct mxs_dma_engine { 124a580b8c5SShawn Guo int dev_id; 125a580b8c5SShawn Guo unsigned int version; 126a580b8c5SShawn Guo void __iomem *base; 127a580b8c5SShawn Guo struct clk *clk; 128a580b8c5SShawn Guo struct dma_device dma_device; 129a580b8c5SShawn Guo struct device_dma_parameters dma_parms; 130a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 131a580b8c5SShawn Guo }; 132a580b8c5SShawn Guo 133a580b8c5SShawn Guo static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) 134a580b8c5SShawn Guo { 135a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 136a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 137a580b8c5SShawn Guo 138a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 139a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 140a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 141a580b8c5SShawn Guo else 142a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 143a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 144a580b8c5SShawn Guo } 145a580b8c5SShawn Guo 146a580b8c5SShawn Guo static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) 147a580b8c5SShawn Guo { 148a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 149a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 150a580b8c5SShawn Guo 151a580b8c5SShawn Guo /* set cmd_addr up */ 152a580b8c5SShawn Guo writel(mxs_chan->ccw_phys, 153a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); 154a580b8c5SShawn Guo 155a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */ 156a580b8c5SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); 157a580b8c5SShawn Guo } 158a580b8c5SShawn Guo 159a580b8c5SShawn Guo static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) 160a580b8c5SShawn Guo { 161a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 162a580b8c5SShawn Guo } 163a580b8c5SShawn Guo 164a580b8c5SShawn Guo static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) 165a580b8c5SShawn Guo { 166a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 167a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 168a580b8c5SShawn Guo 169a580b8c5SShawn Guo /* freeze the channel */ 170a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 171a580b8c5SShawn Guo writel(1 << chan_id, 172a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 173a580b8c5SShawn Guo else 174a580b8c5SShawn Guo writel(1 << chan_id, 175a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 176a580b8c5SShawn Guo 177a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED; 178a580b8c5SShawn Guo } 179a580b8c5SShawn Guo 180a580b8c5SShawn Guo static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) 181a580b8c5SShawn Guo { 182a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 183a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 184a580b8c5SShawn Guo 185a580b8c5SShawn Guo /* unfreeze the channel */ 186a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 187a580b8c5SShawn Guo writel(1 << chan_id, 188a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); 189a580b8c5SShawn Guo else 190a580b8c5SShawn Guo writel(1 << chan_id, 191a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); 192a580b8c5SShawn Guo 193a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 194a580b8c5SShawn Guo } 195a580b8c5SShawn Guo 196a580b8c5SShawn Guo static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan) 197a580b8c5SShawn Guo { 198a580b8c5SShawn Guo dma_cookie_t cookie = mxs_chan->chan.cookie; 199a580b8c5SShawn Guo 200a580b8c5SShawn Guo if (++cookie < 0) 201a580b8c5SShawn Guo cookie = 1; 202a580b8c5SShawn Guo 203a580b8c5SShawn Guo mxs_chan->chan.cookie = cookie; 204a580b8c5SShawn Guo mxs_chan->desc.cookie = cookie; 205a580b8c5SShawn Guo 206a580b8c5SShawn Guo return cookie; 207a580b8c5SShawn Guo } 208a580b8c5SShawn Guo 209a580b8c5SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 210a580b8c5SShawn Guo { 211a580b8c5SShawn Guo return container_of(chan, struct mxs_dma_chan, chan); 212a580b8c5SShawn Guo } 213a580b8c5SShawn Guo 214a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 215a580b8c5SShawn Guo { 216a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); 217a580b8c5SShawn Guo 218a580b8c5SShawn Guo mxs_dma_enable_chan(mxs_chan); 219a580b8c5SShawn Guo 220a580b8c5SShawn Guo return mxs_dma_assign_cookie(mxs_chan); 221a580b8c5SShawn Guo } 222a580b8c5SShawn Guo 223a580b8c5SShawn Guo static void mxs_dma_tasklet(unsigned long data) 224a580b8c5SShawn Guo { 225a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 226a580b8c5SShawn Guo 227a580b8c5SShawn Guo if (mxs_chan->desc.callback) 228a580b8c5SShawn Guo mxs_chan->desc.callback(mxs_chan->desc.callback_param); 229a580b8c5SShawn Guo } 230a580b8c5SShawn Guo 231a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 232a580b8c5SShawn Guo { 233a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id; 234a580b8c5SShawn Guo u32 stat1, stat2; 235a580b8c5SShawn Guo 236a580b8c5SShawn Guo /* completion status */ 237a580b8c5SShawn Guo stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); 238a580b8c5SShawn Guo stat1 &= MXS_DMA_CHANNELS_MASK; 239a580b8c5SShawn Guo writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); 240a580b8c5SShawn Guo 241a580b8c5SShawn Guo /* error status */ 242a580b8c5SShawn Guo stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); 243a580b8c5SShawn Guo writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); 244a580b8c5SShawn Guo 245a580b8c5SShawn Guo /* 246a580b8c5SShawn Guo * When both completion and error of termination bits set at the 247a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes 24840031220SLothar Waßmann * an error we need to handle here in case of either it's (1) a bus 249a580b8c5SShawn Guo * error or (2) a termination error with no completion. 250a580b8c5SShawn Guo */ 251a580b8c5SShawn Guo stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ 252a580b8c5SShawn Guo (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ 253a580b8c5SShawn Guo 254a580b8c5SShawn Guo /* combine error and completion status for checking */ 255a580b8c5SShawn Guo stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; 256a580b8c5SShawn Guo while (stat1) { 257a580b8c5SShawn Guo int channel = fls(stat1) - 1; 258a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = 259a580b8c5SShawn Guo &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; 260a580b8c5SShawn Guo 261a580b8c5SShawn Guo if (channel >= MXS_DMA_CHANNELS) { 262a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev, 263a580b8c5SShawn Guo "%s: error in channel %d\n", __func__, 264a580b8c5SShawn Guo channel - MXS_DMA_CHANNELS); 265a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 266a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 267a580b8c5SShawn Guo } else { 268a580b8c5SShawn Guo if (mxs_chan->flags & MXS_DMA_SG_LOOP) 269a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 270a580b8c5SShawn Guo else 271a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 272a580b8c5SShawn Guo } 273a580b8c5SShawn Guo 274a580b8c5SShawn Guo stat1 &= ~(1 << channel); 275a580b8c5SShawn Guo 276a580b8c5SShawn Guo if (mxs_chan->status == DMA_SUCCESS) 277a580b8c5SShawn Guo mxs_chan->last_completed = mxs_chan->desc.cookie; 278a580b8c5SShawn Guo 279a580b8c5SShawn Guo /* schedule tasklet on this channel */ 280a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet); 281a580b8c5SShawn Guo } 282a580b8c5SShawn Guo 283a580b8c5SShawn Guo return IRQ_HANDLED; 284a580b8c5SShawn Guo } 285a580b8c5SShawn Guo 286a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 287a580b8c5SShawn Guo { 288a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 289a580b8c5SShawn Guo struct mxs_dma_data *data = chan->private; 290a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 291a580b8c5SShawn Guo int ret; 292a580b8c5SShawn Guo 293a580b8c5SShawn Guo if (!data) 294a580b8c5SShawn Guo return -EINVAL; 295a580b8c5SShawn Guo 296a580b8c5SShawn Guo mxs_chan->chan_irq = data->chan_irq; 297a580b8c5SShawn Guo 298a580b8c5SShawn Guo mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 299a580b8c5SShawn Guo &mxs_chan->ccw_phys, GFP_KERNEL); 300a580b8c5SShawn Guo if (!mxs_chan->ccw) { 301a580b8c5SShawn Guo ret = -ENOMEM; 302a580b8c5SShawn Guo goto err_alloc; 303a580b8c5SShawn Guo } 304a580b8c5SShawn Guo 305a580b8c5SShawn Guo memset(mxs_chan->ccw, 0, PAGE_SIZE); 306a580b8c5SShawn Guo 30795bfea16SShawn Guo if (mxs_chan->chan_irq != NO_IRQ) { 308a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 309a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma); 310a580b8c5SShawn Guo if (ret) 311a580b8c5SShawn Guo goto err_irq; 31295bfea16SShawn Guo } 313a580b8c5SShawn Guo 314a580b8c5SShawn Guo ret = clk_enable(mxs_dma->clk); 315a580b8c5SShawn Guo if (ret) 316a580b8c5SShawn Guo goto err_clk; 317a580b8c5SShawn Guo 318a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 319a580b8c5SShawn Guo 320a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 321a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 322a580b8c5SShawn Guo 323a580b8c5SShawn Guo /* the descriptor is ready */ 324a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc); 325a580b8c5SShawn Guo 326a580b8c5SShawn Guo return 0; 327a580b8c5SShawn Guo 328a580b8c5SShawn Guo err_clk: 329a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 330a580b8c5SShawn Guo err_irq: 331a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 332a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 333a580b8c5SShawn Guo err_alloc: 334a580b8c5SShawn Guo return ret; 335a580b8c5SShawn Guo } 336a580b8c5SShawn Guo 337a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan) 338a580b8c5SShawn Guo { 339a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 340a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 341a580b8c5SShawn Guo 342a580b8c5SShawn Guo mxs_dma_disable_chan(mxs_chan); 343a580b8c5SShawn Guo 344a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 345a580b8c5SShawn Guo 346a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 347a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 348a580b8c5SShawn Guo 349a580b8c5SShawn Guo clk_disable(mxs_dma->clk); 350a580b8c5SShawn Guo } 351a580b8c5SShawn Guo 352a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 353a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl, 354db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 355a580b8c5SShawn Guo unsigned long append) 356a580b8c5SShawn Guo { 357a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 358a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 359a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 360a580b8c5SShawn Guo struct scatterlist *sg; 361a580b8c5SShawn Guo int i, j; 362a580b8c5SShawn Guo u32 *pio; 3636d23ea4bSLothar Waßmann int idx = append ? mxs_chan->desc_count : 0; 364a580b8c5SShawn Guo 365a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS && !append) 366a580b8c5SShawn Guo return NULL; 367a580b8c5SShawn Guo 368a580b8c5SShawn Guo if (sg_len + (append ? idx : 0) > NUM_CCW) { 369a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 370a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 371a580b8c5SShawn Guo sg_len, NUM_CCW); 372a580b8c5SShawn Guo goto err_out; 373a580b8c5SShawn Guo } 374a580b8c5SShawn Guo 375a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 376a580b8c5SShawn Guo mxs_chan->flags = 0; 377a580b8c5SShawn Guo 378a580b8c5SShawn Guo /* 379a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg 380a580b8c5SShawn Guo * will be appended to the last prepared sg. 381a580b8c5SShawn Guo */ 382a580b8c5SShawn Guo if (append) { 383a580b8c5SShawn Guo BUG_ON(idx < 1); 384a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1]; 385a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 386a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 387a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ; 388a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM; 389a580b8c5SShawn Guo ccw->bits &= ~CCW_WAIT4END; 390a580b8c5SShawn Guo } else { 391a580b8c5SShawn Guo idx = 0; 392a580b8c5SShawn Guo } 393a580b8c5SShawn Guo 394a580b8c5SShawn Guo if (direction == DMA_NONE) { 395a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 396a580b8c5SShawn Guo pio = (u32 *) sgl; 397a580b8c5SShawn Guo 398a580b8c5SShawn Guo for (j = 0; j < sg_len;) 399a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++; 400a580b8c5SShawn Guo 401a580b8c5SShawn Guo ccw->bits = 0; 402a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 403a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 404a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 405a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 406a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 407a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM); 408a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 409a580b8c5SShawn Guo } else { 410a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) { 411a580b8c5SShawn Guo if (sg->length > MAX_XFER_BYTES) { 412a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 413a580b8c5SShawn Guo sg->length, MAX_XFER_BYTES); 414a580b8c5SShawn Guo goto err_out; 415a580b8c5SShawn Guo } 416a580b8c5SShawn Guo 417a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 418a580b8c5SShawn Guo 419a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 420a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address; 421a580b8c5SShawn Guo ccw->xfer_bytes = sg->length; 422a580b8c5SShawn Guo 423a580b8c5SShawn Guo ccw->bits = 0; 424a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 425a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 426a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 427db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 428a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 429a580b8c5SShawn Guo COMMAND); 430a580b8c5SShawn Guo 431a580b8c5SShawn Guo if (i + 1 == sg_len) { 432a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN; 433a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 434a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 435a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 436a580b8c5SShawn Guo } 437a580b8c5SShawn Guo } 438a580b8c5SShawn Guo } 4396d23ea4bSLothar Waßmann mxs_chan->desc_count = idx; 440a580b8c5SShawn Guo 441a580b8c5SShawn Guo return &mxs_chan->desc; 442a580b8c5SShawn Guo 443a580b8c5SShawn Guo err_out: 444a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 445a580b8c5SShawn Guo return NULL; 446a580b8c5SShawn Guo } 447a580b8c5SShawn Guo 448a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 449a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 450db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 451a580b8c5SShawn Guo { 452a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 453a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 454a580b8c5SShawn Guo int num_periods = buf_len / period_len; 455a580b8c5SShawn Guo int i = 0, buf = 0; 456a580b8c5SShawn Guo 457a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS) 458a580b8c5SShawn Guo return NULL; 459a580b8c5SShawn Guo 460a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 461a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP; 462a580b8c5SShawn Guo 463a580b8c5SShawn Guo if (num_periods > NUM_CCW) { 464a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 465a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 466a580b8c5SShawn Guo num_periods, NUM_CCW); 467a580b8c5SShawn Guo goto err_out; 468a580b8c5SShawn Guo } 469a580b8c5SShawn Guo 470a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) { 471a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 472a580b8c5SShawn Guo "maximum period size exceeded: %d > %d\n", 473a580b8c5SShawn Guo period_len, MAX_XFER_BYTES); 474a580b8c5SShawn Guo goto err_out; 475a580b8c5SShawn Guo } 476a580b8c5SShawn Guo 477a580b8c5SShawn Guo while (buf < buf_len) { 478a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 479a580b8c5SShawn Guo 480a580b8c5SShawn Guo if (i + 1 == num_periods) 481a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys; 482a580b8c5SShawn Guo else 483a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 484a580b8c5SShawn Guo 485a580b8c5SShawn Guo ccw->bufaddr = dma_addr; 486a580b8c5SShawn Guo ccw->xfer_bytes = period_len; 487a580b8c5SShawn Guo 488a580b8c5SShawn Guo ccw->bits = 0; 489a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 490a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 491a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 492a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 493db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 494a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 495a580b8c5SShawn Guo 496a580b8c5SShawn Guo dma_addr += period_len; 497a580b8c5SShawn Guo buf += period_len; 498a580b8c5SShawn Guo 499a580b8c5SShawn Guo i++; 500a580b8c5SShawn Guo } 5016d23ea4bSLothar Waßmann mxs_chan->desc_count = i; 502a580b8c5SShawn Guo 503a580b8c5SShawn Guo return &mxs_chan->desc; 504a580b8c5SShawn Guo 505a580b8c5SShawn Guo err_out: 506a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 507a580b8c5SShawn Guo return NULL; 508a580b8c5SShawn Guo } 509a580b8c5SShawn Guo 510a580b8c5SShawn Guo static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 511a580b8c5SShawn Guo unsigned long arg) 512a580b8c5SShawn Guo { 513a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 514a580b8c5SShawn Guo int ret = 0; 515a580b8c5SShawn Guo 516a580b8c5SShawn Guo switch (cmd) { 517a580b8c5SShawn Guo case DMA_TERMINATE_ALL: 518a62bae98SDong Aisheng mxs_dma_reset_chan(mxs_chan); 5197ad7a345SLothar Waßmann mxs_dma_disable_chan(mxs_chan); 520a580b8c5SShawn Guo break; 521a580b8c5SShawn Guo case DMA_PAUSE: 522a580b8c5SShawn Guo mxs_dma_pause_chan(mxs_chan); 523a580b8c5SShawn Guo break; 524a580b8c5SShawn Guo case DMA_RESUME: 525a580b8c5SShawn Guo mxs_dma_resume_chan(mxs_chan); 526a580b8c5SShawn Guo break; 527a580b8c5SShawn Guo default: 528a580b8c5SShawn Guo ret = -ENOSYS; 529a580b8c5SShawn Guo } 530a580b8c5SShawn Guo 531a580b8c5SShawn Guo return ret; 532a580b8c5SShawn Guo } 533a580b8c5SShawn Guo 534a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 535a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate) 536a580b8c5SShawn Guo { 537a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 538a580b8c5SShawn Guo dma_cookie_t last_used; 539a580b8c5SShawn Guo 540a580b8c5SShawn Guo last_used = chan->cookie; 541a580b8c5SShawn Guo dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0); 542a580b8c5SShawn Guo 543a580b8c5SShawn Guo return mxs_chan->status; 544a580b8c5SShawn Guo } 545a580b8c5SShawn Guo 546a580b8c5SShawn Guo static void mxs_dma_issue_pending(struct dma_chan *chan) 547a580b8c5SShawn Guo { 548a580b8c5SShawn Guo /* 549a580b8c5SShawn Guo * Nothing to do. We only have a single descriptor. 550a580b8c5SShawn Guo */ 551a580b8c5SShawn Guo } 552a580b8c5SShawn Guo 553a580b8c5SShawn Guo static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 554a580b8c5SShawn Guo { 555a580b8c5SShawn Guo int ret; 556a580b8c5SShawn Guo 557a580b8c5SShawn Guo ret = clk_enable(mxs_dma->clk); 558a580b8c5SShawn Guo if (ret) 559feb397deSLothar Waßmann return ret; 560a580b8c5SShawn Guo 561a580b8c5SShawn Guo ret = mxs_reset_block(mxs_dma->base); 562a580b8c5SShawn Guo if (ret) 563a580b8c5SShawn Guo goto err_out; 564a580b8c5SShawn Guo 565a580b8c5SShawn Guo /* only major version matters */ 566a580b8c5SShawn Guo mxs_dma->version = readl(mxs_dma->base + 567a580b8c5SShawn Guo ((mxs_dma->dev_id == MXS_DMA_APBX) ? 568a580b8c5SShawn Guo HW_APBX_VERSION : HW_APBH_VERSION)) >> 569a580b8c5SShawn Guo BP_APBHX_VERSION_MAJOR; 570a580b8c5SShawn Guo 571a580b8c5SShawn Guo /* enable apbh burst */ 572a580b8c5SShawn Guo if (dma_is_apbh()) { 573a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN, 574a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 575a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN, 576a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 577a580b8c5SShawn Guo } 578a580b8c5SShawn Guo 579a580b8c5SShawn Guo /* enable irq for all the channels */ 580a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 581a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); 582a580b8c5SShawn Guo 583a580b8c5SShawn Guo err_out: 584feb397deSLothar Waßmann clk_disable(mxs_dma->clk); 585a580b8c5SShawn Guo return ret; 586a580b8c5SShawn Guo } 587a580b8c5SShawn Guo 588a580b8c5SShawn Guo static int __init mxs_dma_probe(struct platform_device *pdev) 589a580b8c5SShawn Guo { 590a580b8c5SShawn Guo const struct platform_device_id *id_entry = 591a580b8c5SShawn Guo platform_get_device_id(pdev); 592a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 593a580b8c5SShawn Guo struct resource *iores; 594a580b8c5SShawn Guo int ret, i; 595a580b8c5SShawn Guo 596a580b8c5SShawn Guo mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); 597a580b8c5SShawn Guo if (!mxs_dma) 598a580b8c5SShawn Guo return -ENOMEM; 599a580b8c5SShawn Guo 600a580b8c5SShawn Guo mxs_dma->dev_id = id_entry->driver_data; 601a580b8c5SShawn Guo 602a580b8c5SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 603a580b8c5SShawn Guo 604a580b8c5SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 605a580b8c5SShawn Guo pdev->name)) { 606a580b8c5SShawn Guo ret = -EBUSY; 607a580b8c5SShawn Guo goto err_request_region; 608a580b8c5SShawn Guo } 609a580b8c5SShawn Guo 610a580b8c5SShawn Guo mxs_dma->base = ioremap(iores->start, resource_size(iores)); 611a580b8c5SShawn Guo if (!mxs_dma->base) { 612a580b8c5SShawn Guo ret = -ENOMEM; 613a580b8c5SShawn Guo goto err_ioremap; 614a580b8c5SShawn Guo } 615a580b8c5SShawn Guo 616a580b8c5SShawn Guo mxs_dma->clk = clk_get(&pdev->dev, NULL); 617a580b8c5SShawn Guo if (IS_ERR(mxs_dma->clk)) { 618a580b8c5SShawn Guo ret = PTR_ERR(mxs_dma->clk); 619a580b8c5SShawn Guo goto err_clk; 620a580b8c5SShawn Guo } 621a580b8c5SShawn Guo 622a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 623a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 624a580b8c5SShawn Guo 625a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 626a580b8c5SShawn Guo 627a580b8c5SShawn Guo /* Initialize channel parameters */ 628a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) { 629a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 630a580b8c5SShawn Guo 631a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma; 632a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device; 633a580b8c5SShawn Guo 634a580b8c5SShawn Guo tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 635a580b8c5SShawn Guo (unsigned long) mxs_chan); 636a580b8c5SShawn Guo 637a580b8c5SShawn Guo 638a580b8c5SShawn Guo /* Add the channel to mxs_chan list */ 639a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node, 640a580b8c5SShawn Guo &mxs_dma->dma_device.channels); 641a580b8c5SShawn Guo } 642a580b8c5SShawn Guo 643a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma); 644a580b8c5SShawn Guo if (ret) 645a580b8c5SShawn Guo goto err_init; 646a580b8c5SShawn Guo 647a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev; 648a580b8c5SShawn Guo 649a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */ 650a580b8c5SShawn Guo mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 651a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 652a580b8c5SShawn Guo 653a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 654a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 655a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 656a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 657a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 658a580b8c5SShawn Guo mxs_dma->dma_device.device_control = mxs_dma_control; 659a580b8c5SShawn Guo mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; 660a580b8c5SShawn Guo 661a580b8c5SShawn Guo ret = dma_async_device_register(&mxs_dma->dma_device); 662a580b8c5SShawn Guo if (ret) { 663a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 664a580b8c5SShawn Guo goto err_init; 665a580b8c5SShawn Guo } 666a580b8c5SShawn Guo 667a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n"); 668a580b8c5SShawn Guo 669a580b8c5SShawn Guo return 0; 670a580b8c5SShawn Guo 671a580b8c5SShawn Guo err_init: 672a580b8c5SShawn Guo clk_put(mxs_dma->clk); 673a580b8c5SShawn Guo err_clk: 674a580b8c5SShawn Guo iounmap(mxs_dma->base); 675a580b8c5SShawn Guo err_ioremap: 676a580b8c5SShawn Guo release_mem_region(iores->start, resource_size(iores)); 677a580b8c5SShawn Guo err_request_region: 678a580b8c5SShawn Guo kfree(mxs_dma); 679a580b8c5SShawn Guo return ret; 680a580b8c5SShawn Guo } 681a580b8c5SShawn Guo 682a580b8c5SShawn Guo static struct platform_device_id mxs_dma_type[] = { 683a580b8c5SShawn Guo { 684a580b8c5SShawn Guo .name = "mxs-dma-apbh", 685a580b8c5SShawn Guo .driver_data = MXS_DMA_APBH, 686a580b8c5SShawn Guo }, { 687a580b8c5SShawn Guo .name = "mxs-dma-apbx", 688a580b8c5SShawn Guo .driver_data = MXS_DMA_APBX, 6892a9778edSAxel Lin }, { 6902a9778edSAxel Lin /* end of list */ 691a580b8c5SShawn Guo } 692a580b8c5SShawn Guo }; 693a580b8c5SShawn Guo 694a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = { 695a580b8c5SShawn Guo .driver = { 696a580b8c5SShawn Guo .name = "mxs-dma", 697a580b8c5SShawn Guo }, 698a580b8c5SShawn Guo .id_table = mxs_dma_type, 699a580b8c5SShawn Guo }; 700a580b8c5SShawn Guo 701a580b8c5SShawn Guo static int __init mxs_dma_module_init(void) 702a580b8c5SShawn Guo { 703a580b8c5SShawn Guo return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 704a580b8c5SShawn Guo } 705a580b8c5SShawn Guo subsys_initcall(mxs_dma_module_init); 706