1a580b8c5SShawn Guo /* 2a580b8c5SShawn Guo * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3a580b8c5SShawn Guo * 4a580b8c5SShawn Guo * Refer to drivers/dma/imx-sdma.c 5a580b8c5SShawn Guo * 6a580b8c5SShawn Guo * This program is free software; you can redistribute it and/or modify 7a580b8c5SShawn Guo * it under the terms of the GNU General Public License version 2 as 8a580b8c5SShawn Guo * published by the Free Software Foundation. 9a580b8c5SShawn Guo */ 10a580b8c5SShawn Guo 11a580b8c5SShawn Guo #include <linux/init.h> 12a580b8c5SShawn Guo #include <linux/types.h> 13a580b8c5SShawn Guo #include <linux/mm.h> 14a580b8c5SShawn Guo #include <linux/interrupt.h> 15a580b8c5SShawn Guo #include <linux/clk.h> 16a580b8c5SShawn Guo #include <linux/wait.h> 17a580b8c5SShawn Guo #include <linux/sched.h> 18a580b8c5SShawn Guo #include <linux/semaphore.h> 19a580b8c5SShawn Guo #include <linux/device.h> 20a580b8c5SShawn Guo #include <linux/dma-mapping.h> 21a580b8c5SShawn Guo #include <linux/slab.h> 22a580b8c5SShawn Guo #include <linux/platform_device.h> 23a580b8c5SShawn Guo #include <linux/dmaengine.h> 24a580b8c5SShawn Guo #include <linux/delay.h> 25a580b8c5SShawn Guo 26a580b8c5SShawn Guo #include <asm/irq.h> 27a580b8c5SShawn Guo #include <mach/mxs.h> 28a580b8c5SShawn Guo #include <mach/dma.h> 29a580b8c5SShawn Guo #include <mach/common.h> 30a580b8c5SShawn Guo 31a580b8c5SShawn Guo /* 32a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means 33a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 34a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices. 35a580b8c5SShawn Guo */ 36a580b8c5SShawn Guo 37a580b8c5SShawn Guo #define MXS_DMA_APBH 0 38a580b8c5SShawn Guo #define MXS_DMA_APBX 1 39a580b8c5SShawn Guo #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) 40a580b8c5SShawn Guo 41a580b8c5SShawn Guo #define APBH_VERSION_LATEST 3 42a580b8c5SShawn Guo #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) 43a580b8c5SShawn Guo 44a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000 45a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 46a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 47a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16 48a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010 49a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020 50a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030 51a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 52a580b8c5SShawn Guo #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) 53a580b8c5SShawn Guo #define HW_APBX_VERSION 0x800 54a580b8c5SShawn Guo #define BP_APBHX_VERSION_MAJOR 24 55a580b8c5SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(n) \ 56a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) 57a580b8c5SShawn Guo #define HW_APBHX_CHn_SEMA(n) \ 58a580b8c5SShawn Guo (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) 59a580b8c5SShawn Guo 60a580b8c5SShawn Guo /* 61a580b8c5SShawn Guo * ccw bits definitions 62a580b8c5SShawn Guo * 63a580b8c5SShawn Guo * COMMAND: 0..1 (2) 64a580b8c5SShawn Guo * CHAIN: 2 (1) 65a580b8c5SShawn Guo * IRQ: 3 (1) 66a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented 67a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented 68a580b8c5SShawn Guo * DEC_SEM: 6 (1) 69a580b8c5SShawn Guo * WAIT4END: 7 (1) 70a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1) 71a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1) 72a580b8c5SShawn Guo * RESERVED: 10..11 (2) 73a580b8c5SShawn Guo * PIO_NUM: 12..15 (4) 74a580b8c5SShawn Guo */ 75a580b8c5SShawn Guo #define BP_CCW_COMMAND 0 76a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0) 77a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2) 78a580b8c5SShawn Guo #define CCW_IRQ (1 << 3) 79a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6) 80a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7) 81a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8) 82a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9) 83a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12 84a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12) 85a580b8c5SShawn Guo 86a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 87a580b8c5SShawn Guo 88a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0 89a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1 90a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2 91a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 92a580b8c5SShawn Guo 93a580b8c5SShawn Guo struct mxs_dma_ccw { 94a580b8c5SShawn Guo u32 next; 95a580b8c5SShawn Guo u16 bits; 96a580b8c5SShawn Guo u16 xfer_bytes; 97a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00 98a580b8c5SShawn Guo u32 bufaddr; 99a580b8c5SShawn Guo #define MXS_PIO_WORDS 16 100a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS]; 101a580b8c5SShawn Guo }; 102a580b8c5SShawn Guo 103a580b8c5SShawn Guo #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) 104a580b8c5SShawn Guo 105a580b8c5SShawn Guo struct mxs_dma_chan { 106a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 107a580b8c5SShawn Guo struct dma_chan chan; 108a580b8c5SShawn Guo struct dma_async_tx_descriptor desc; 109a580b8c5SShawn Guo struct tasklet_struct tasklet; 110a580b8c5SShawn Guo int chan_irq; 111a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 112a580b8c5SShawn Guo dma_addr_t ccw_phys; 1136d23ea4bSLothar Waßmann int desc_count; 114a580b8c5SShawn Guo enum dma_status status; 115a580b8c5SShawn Guo unsigned int flags; 116a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0) 117a580b8c5SShawn Guo }; 118a580b8c5SShawn Guo 119a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16 120a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff 121a580b8c5SShawn Guo 122a580b8c5SShawn Guo struct mxs_dma_engine { 123a580b8c5SShawn Guo int dev_id; 124a580b8c5SShawn Guo unsigned int version; 125a580b8c5SShawn Guo void __iomem *base; 126a580b8c5SShawn Guo struct clk *clk; 127a580b8c5SShawn Guo struct dma_device dma_device; 128a580b8c5SShawn Guo struct device_dma_parameters dma_parms; 129a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 130a580b8c5SShawn Guo }; 131a580b8c5SShawn Guo 132a580b8c5SShawn Guo static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) 133a580b8c5SShawn Guo { 134a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 135a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 136a580b8c5SShawn Guo 137a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 138a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 139a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 140a580b8c5SShawn Guo else 141a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 142a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 143a580b8c5SShawn Guo } 144a580b8c5SShawn Guo 145a580b8c5SShawn Guo static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) 146a580b8c5SShawn Guo { 147a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 148a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 149a580b8c5SShawn Guo 150a580b8c5SShawn Guo /* set cmd_addr up */ 151a580b8c5SShawn Guo writel(mxs_chan->ccw_phys, 152a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); 153a580b8c5SShawn Guo 154a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */ 155a580b8c5SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); 156a580b8c5SShawn Guo } 157a580b8c5SShawn Guo 158a580b8c5SShawn Guo static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) 159a580b8c5SShawn Guo { 160a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 161a580b8c5SShawn Guo } 162a580b8c5SShawn Guo 163a580b8c5SShawn Guo static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) 164a580b8c5SShawn Guo { 165a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 166a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 167a580b8c5SShawn Guo 168a580b8c5SShawn Guo /* freeze the channel */ 169a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 170a580b8c5SShawn Guo writel(1 << chan_id, 171a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 172a580b8c5SShawn Guo else 173a580b8c5SShawn Guo writel(1 << chan_id, 174a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); 175a580b8c5SShawn Guo 176a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED; 177a580b8c5SShawn Guo } 178a580b8c5SShawn Guo 179a580b8c5SShawn Guo static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) 180a580b8c5SShawn Guo { 181a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 182a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 183a580b8c5SShawn Guo 184a580b8c5SShawn Guo /* unfreeze the channel */ 185a580b8c5SShawn Guo if (dma_is_apbh() && apbh_is_old()) 186a580b8c5SShawn Guo writel(1 << chan_id, 187a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); 188a580b8c5SShawn Guo else 189a580b8c5SShawn Guo writel(1 << chan_id, 190a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); 191a580b8c5SShawn Guo 192a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 193a580b8c5SShawn Guo } 194a580b8c5SShawn Guo 195a580b8c5SShawn Guo static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan) 196a580b8c5SShawn Guo { 197a580b8c5SShawn Guo dma_cookie_t cookie = mxs_chan->chan.cookie; 198a580b8c5SShawn Guo 199a580b8c5SShawn Guo if (++cookie < 0) 200a580b8c5SShawn Guo cookie = 1; 201a580b8c5SShawn Guo 202a580b8c5SShawn Guo mxs_chan->chan.cookie = cookie; 203a580b8c5SShawn Guo mxs_chan->desc.cookie = cookie; 204a580b8c5SShawn Guo 205a580b8c5SShawn Guo return cookie; 206a580b8c5SShawn Guo } 207a580b8c5SShawn Guo 208a580b8c5SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 209a580b8c5SShawn Guo { 210a580b8c5SShawn Guo return container_of(chan, struct mxs_dma_chan, chan); 211a580b8c5SShawn Guo } 212a580b8c5SShawn Guo 213a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 214a580b8c5SShawn Guo { 215a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); 216a580b8c5SShawn Guo 217a580b8c5SShawn Guo mxs_dma_enable_chan(mxs_chan); 218a580b8c5SShawn Guo 219a580b8c5SShawn Guo return mxs_dma_assign_cookie(mxs_chan); 220a580b8c5SShawn Guo } 221a580b8c5SShawn Guo 222a580b8c5SShawn Guo static void mxs_dma_tasklet(unsigned long data) 223a580b8c5SShawn Guo { 224a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 225a580b8c5SShawn Guo 226a580b8c5SShawn Guo if (mxs_chan->desc.callback) 227a580b8c5SShawn Guo mxs_chan->desc.callback(mxs_chan->desc.callback_param); 228a580b8c5SShawn Guo } 229a580b8c5SShawn Guo 230a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 231a580b8c5SShawn Guo { 232a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id; 233a580b8c5SShawn Guo u32 stat1, stat2; 234a580b8c5SShawn Guo 235a580b8c5SShawn Guo /* completion status */ 236a580b8c5SShawn Guo stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); 237a580b8c5SShawn Guo stat1 &= MXS_DMA_CHANNELS_MASK; 238a580b8c5SShawn Guo writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); 239a580b8c5SShawn Guo 240a580b8c5SShawn Guo /* error status */ 241a580b8c5SShawn Guo stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); 242a580b8c5SShawn Guo writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); 243a580b8c5SShawn Guo 244a580b8c5SShawn Guo /* 245a580b8c5SShawn Guo * When both completion and error of termination bits set at the 246a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes 24740031220SLothar Waßmann * an error we need to handle here in case of either it's (1) a bus 248a580b8c5SShawn Guo * error or (2) a termination error with no completion. 249a580b8c5SShawn Guo */ 250a580b8c5SShawn Guo stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ 251a580b8c5SShawn Guo (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ 252a580b8c5SShawn Guo 253a580b8c5SShawn Guo /* combine error and completion status for checking */ 254a580b8c5SShawn Guo stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; 255a580b8c5SShawn Guo while (stat1) { 256a580b8c5SShawn Guo int channel = fls(stat1) - 1; 257a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = 258a580b8c5SShawn Guo &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; 259a580b8c5SShawn Guo 260a580b8c5SShawn Guo if (channel >= MXS_DMA_CHANNELS) { 261a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev, 262a580b8c5SShawn Guo "%s: error in channel %d\n", __func__, 263a580b8c5SShawn Guo channel - MXS_DMA_CHANNELS); 264a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 265a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 266a580b8c5SShawn Guo } else { 267a580b8c5SShawn Guo if (mxs_chan->flags & MXS_DMA_SG_LOOP) 268a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 269a580b8c5SShawn Guo else 270a580b8c5SShawn Guo mxs_chan->status = DMA_SUCCESS; 271a580b8c5SShawn Guo } 272a580b8c5SShawn Guo 273a580b8c5SShawn Guo stat1 &= ~(1 << channel); 274a580b8c5SShawn Guo 275a580b8c5SShawn Guo if (mxs_chan->status == DMA_SUCCESS) 2764d4e58deSRussell King - ARM Linux mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie; 277a580b8c5SShawn Guo 278a580b8c5SShawn Guo /* schedule tasklet on this channel */ 279a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet); 280a580b8c5SShawn Guo } 281a580b8c5SShawn Guo 282a580b8c5SShawn Guo return IRQ_HANDLED; 283a580b8c5SShawn Guo } 284a580b8c5SShawn Guo 285a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 286a580b8c5SShawn Guo { 287a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 288a580b8c5SShawn Guo struct mxs_dma_data *data = chan->private; 289a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 290a580b8c5SShawn Guo int ret; 291a580b8c5SShawn Guo 292a580b8c5SShawn Guo if (!data) 293a580b8c5SShawn Guo return -EINVAL; 294a580b8c5SShawn Guo 295a580b8c5SShawn Guo mxs_chan->chan_irq = data->chan_irq; 296a580b8c5SShawn Guo 297a580b8c5SShawn Guo mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 298a580b8c5SShawn Guo &mxs_chan->ccw_phys, GFP_KERNEL); 299a580b8c5SShawn Guo if (!mxs_chan->ccw) { 300a580b8c5SShawn Guo ret = -ENOMEM; 301a580b8c5SShawn Guo goto err_alloc; 302a580b8c5SShawn Guo } 303a580b8c5SShawn Guo 304a580b8c5SShawn Guo memset(mxs_chan->ccw, 0, PAGE_SIZE); 305a580b8c5SShawn Guo 30695bfea16SShawn Guo if (mxs_chan->chan_irq != NO_IRQ) { 307a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 308a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma); 309a580b8c5SShawn Guo if (ret) 310a580b8c5SShawn Guo goto err_irq; 31195bfea16SShawn Guo } 312a580b8c5SShawn Guo 313759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 314a580b8c5SShawn Guo if (ret) 315a580b8c5SShawn Guo goto err_clk; 316a580b8c5SShawn Guo 317a580b8c5SShawn Guo mxs_dma_reset_chan(mxs_chan); 318a580b8c5SShawn Guo 319a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 320a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 321a580b8c5SShawn Guo 322a580b8c5SShawn Guo /* the descriptor is ready */ 323a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc); 324a580b8c5SShawn Guo 325a580b8c5SShawn Guo return 0; 326a580b8c5SShawn Guo 327a580b8c5SShawn Guo err_clk: 328a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 329a580b8c5SShawn Guo err_irq: 330a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 331a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 332a580b8c5SShawn Guo err_alloc: 333a580b8c5SShawn Guo return ret; 334a580b8c5SShawn Guo } 335a580b8c5SShawn Guo 336a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan) 337a580b8c5SShawn Guo { 338a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 339a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 340a580b8c5SShawn Guo 341a580b8c5SShawn Guo mxs_dma_disable_chan(mxs_chan); 342a580b8c5SShawn Guo 343a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 344a580b8c5SShawn Guo 345a580b8c5SShawn Guo dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, 346a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 347a580b8c5SShawn Guo 348759a2e30SShawn Guo clk_disable_unprepare(mxs_dma->clk); 349a580b8c5SShawn Guo } 350a580b8c5SShawn Guo 351a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 352a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl, 353db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 354a580b8c5SShawn Guo unsigned long append) 355a580b8c5SShawn Guo { 356a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 357a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 358a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 359a580b8c5SShawn Guo struct scatterlist *sg; 360a580b8c5SShawn Guo int i, j; 361a580b8c5SShawn Guo u32 *pio; 3626d23ea4bSLothar Waßmann int idx = append ? mxs_chan->desc_count : 0; 363a580b8c5SShawn Guo 364a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS && !append) 365a580b8c5SShawn Guo return NULL; 366a580b8c5SShawn Guo 367a580b8c5SShawn Guo if (sg_len + (append ? idx : 0) > NUM_CCW) { 368a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 369a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 370a580b8c5SShawn Guo sg_len, NUM_CCW); 371a580b8c5SShawn Guo goto err_out; 372a580b8c5SShawn Guo } 373a580b8c5SShawn Guo 374a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 375a580b8c5SShawn Guo mxs_chan->flags = 0; 376a580b8c5SShawn Guo 377a580b8c5SShawn Guo /* 378a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg 379a580b8c5SShawn Guo * will be appended to the last prepared sg. 380a580b8c5SShawn Guo */ 381a580b8c5SShawn Guo if (append) { 382a580b8c5SShawn Guo BUG_ON(idx < 1); 383a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1]; 384a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 385a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 386a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ; 387a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM; 388a580b8c5SShawn Guo ccw->bits &= ~CCW_WAIT4END; 389a580b8c5SShawn Guo } else { 390a580b8c5SShawn Guo idx = 0; 391a580b8c5SShawn Guo } 392a580b8c5SShawn Guo 39362268ce9SShawn Guo if (direction == DMA_TRANS_NONE) { 394a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 395a580b8c5SShawn Guo pio = (u32 *) sgl; 396a580b8c5SShawn Guo 397a580b8c5SShawn Guo for (j = 0; j < sg_len;) 398a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++; 399a580b8c5SShawn Guo 400a580b8c5SShawn Guo ccw->bits = 0; 401a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 402a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 403a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 404a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 405a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 406a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM); 407a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 408a580b8c5SShawn Guo } else { 409a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) { 410a580b8c5SShawn Guo if (sg->length > MAX_XFER_BYTES) { 411a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 412a580b8c5SShawn Guo sg->length, MAX_XFER_BYTES); 413a580b8c5SShawn Guo goto err_out; 414a580b8c5SShawn Guo } 415a580b8c5SShawn Guo 416a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 417a580b8c5SShawn Guo 418a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 419a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address; 420a580b8c5SShawn Guo ccw->xfer_bytes = sg->length; 421a580b8c5SShawn Guo 422a580b8c5SShawn Guo ccw->bits = 0; 423a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 424a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 425a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 426db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 427a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 428a580b8c5SShawn Guo COMMAND); 429a580b8c5SShawn Guo 430a580b8c5SShawn Guo if (i + 1 == sg_len) { 431a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN; 432a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 433a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 434a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 435a580b8c5SShawn Guo } 436a580b8c5SShawn Guo } 437a580b8c5SShawn Guo } 4386d23ea4bSLothar Waßmann mxs_chan->desc_count = idx; 439a580b8c5SShawn Guo 440a580b8c5SShawn Guo return &mxs_chan->desc; 441a580b8c5SShawn Guo 442a580b8c5SShawn Guo err_out: 443a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 444a580b8c5SShawn Guo return NULL; 445a580b8c5SShawn Guo } 446a580b8c5SShawn Guo 447a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 448a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 449db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 450a580b8c5SShawn Guo { 451a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 452a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 453a580b8c5SShawn Guo int num_periods = buf_len / period_len; 454a580b8c5SShawn Guo int i = 0, buf = 0; 455a580b8c5SShawn Guo 456a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS) 457a580b8c5SShawn Guo return NULL; 458a580b8c5SShawn Guo 459a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 460a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP; 461a580b8c5SShawn Guo 462a580b8c5SShawn Guo if (num_periods > NUM_CCW) { 463a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 464a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 465a580b8c5SShawn Guo num_periods, NUM_CCW); 466a580b8c5SShawn Guo goto err_out; 467a580b8c5SShawn Guo } 468a580b8c5SShawn Guo 469a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) { 470a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 471a580b8c5SShawn Guo "maximum period size exceeded: %d > %d\n", 472a580b8c5SShawn Guo period_len, MAX_XFER_BYTES); 473a580b8c5SShawn Guo goto err_out; 474a580b8c5SShawn Guo } 475a580b8c5SShawn Guo 476a580b8c5SShawn Guo while (buf < buf_len) { 477a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 478a580b8c5SShawn Guo 479a580b8c5SShawn Guo if (i + 1 == num_periods) 480a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys; 481a580b8c5SShawn Guo else 482a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 483a580b8c5SShawn Guo 484a580b8c5SShawn Guo ccw->bufaddr = dma_addr; 485a580b8c5SShawn Guo ccw->xfer_bytes = period_len; 486a580b8c5SShawn Guo 487a580b8c5SShawn Guo ccw->bits = 0; 488a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 489a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 490a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 491a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 492db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 493a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 494a580b8c5SShawn Guo 495a580b8c5SShawn Guo dma_addr += period_len; 496a580b8c5SShawn Guo buf += period_len; 497a580b8c5SShawn Guo 498a580b8c5SShawn Guo i++; 499a580b8c5SShawn Guo } 5006d23ea4bSLothar Waßmann mxs_chan->desc_count = i; 501a580b8c5SShawn Guo 502a580b8c5SShawn Guo return &mxs_chan->desc; 503a580b8c5SShawn Guo 504a580b8c5SShawn Guo err_out: 505a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 506a580b8c5SShawn Guo return NULL; 507a580b8c5SShawn Guo } 508a580b8c5SShawn Guo 509a580b8c5SShawn Guo static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 510a580b8c5SShawn Guo unsigned long arg) 511a580b8c5SShawn Guo { 512a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 513a580b8c5SShawn Guo int ret = 0; 514a580b8c5SShawn Guo 515a580b8c5SShawn Guo switch (cmd) { 516a580b8c5SShawn Guo case DMA_TERMINATE_ALL: 517a62bae98SDong Aisheng mxs_dma_reset_chan(mxs_chan); 5187ad7a345SLothar Waßmann mxs_dma_disable_chan(mxs_chan); 519a580b8c5SShawn Guo break; 520a580b8c5SShawn Guo case DMA_PAUSE: 521a580b8c5SShawn Guo mxs_dma_pause_chan(mxs_chan); 522a580b8c5SShawn Guo break; 523a580b8c5SShawn Guo case DMA_RESUME: 524a580b8c5SShawn Guo mxs_dma_resume_chan(mxs_chan); 525a580b8c5SShawn Guo break; 526a580b8c5SShawn Guo default: 527a580b8c5SShawn Guo ret = -ENOSYS; 528a580b8c5SShawn Guo } 529a580b8c5SShawn Guo 530a580b8c5SShawn Guo return ret; 531a580b8c5SShawn Guo } 532a580b8c5SShawn Guo 533a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 534a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate) 535a580b8c5SShawn Guo { 536a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 537a580b8c5SShawn Guo dma_cookie_t last_used; 538a580b8c5SShawn Guo 539a580b8c5SShawn Guo last_used = chan->cookie; 5404d4e58deSRussell King - ARM Linux dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); 541a580b8c5SShawn Guo 542a580b8c5SShawn Guo return mxs_chan->status; 543a580b8c5SShawn Guo } 544a580b8c5SShawn Guo 545a580b8c5SShawn Guo static void mxs_dma_issue_pending(struct dma_chan *chan) 546a580b8c5SShawn Guo { 547a580b8c5SShawn Guo /* 548a580b8c5SShawn Guo * Nothing to do. We only have a single descriptor. 549a580b8c5SShawn Guo */ 550a580b8c5SShawn Guo } 551a580b8c5SShawn Guo 552a580b8c5SShawn Guo static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 553a580b8c5SShawn Guo { 554a580b8c5SShawn Guo int ret; 555a580b8c5SShawn Guo 556759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 557a580b8c5SShawn Guo if (ret) 558feb397deSLothar Waßmann return ret; 559a580b8c5SShawn Guo 560a580b8c5SShawn Guo ret = mxs_reset_block(mxs_dma->base); 561a580b8c5SShawn Guo if (ret) 562a580b8c5SShawn Guo goto err_out; 563a580b8c5SShawn Guo 564a580b8c5SShawn Guo /* only major version matters */ 565a580b8c5SShawn Guo mxs_dma->version = readl(mxs_dma->base + 566a580b8c5SShawn Guo ((mxs_dma->dev_id == MXS_DMA_APBX) ? 567a580b8c5SShawn Guo HW_APBX_VERSION : HW_APBH_VERSION)) >> 568a580b8c5SShawn Guo BP_APBHX_VERSION_MAJOR; 569a580b8c5SShawn Guo 570a580b8c5SShawn Guo /* enable apbh burst */ 571a580b8c5SShawn Guo if (dma_is_apbh()) { 572a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN, 573a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 574a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN, 575a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); 576a580b8c5SShawn Guo } 577a580b8c5SShawn Guo 578a580b8c5SShawn Guo /* enable irq for all the channels */ 579a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 580a580b8c5SShawn Guo mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); 581a580b8c5SShawn Guo 582a580b8c5SShawn Guo err_out: 58357f2685cSLinus Torvalds clk_disable_unprepare(mxs_dma->clk); 584a580b8c5SShawn Guo return ret; 585a580b8c5SShawn Guo } 586a580b8c5SShawn Guo 587a580b8c5SShawn Guo static int __init mxs_dma_probe(struct platform_device *pdev) 588a580b8c5SShawn Guo { 589a580b8c5SShawn Guo const struct platform_device_id *id_entry = 590a580b8c5SShawn Guo platform_get_device_id(pdev); 591a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 592a580b8c5SShawn Guo struct resource *iores; 593a580b8c5SShawn Guo int ret, i; 594a580b8c5SShawn Guo 595a580b8c5SShawn Guo mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); 596a580b8c5SShawn Guo if (!mxs_dma) 597a580b8c5SShawn Guo return -ENOMEM; 598a580b8c5SShawn Guo 599a580b8c5SShawn Guo mxs_dma->dev_id = id_entry->driver_data; 600a580b8c5SShawn Guo 601a580b8c5SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 602a580b8c5SShawn Guo 603a580b8c5SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 604a580b8c5SShawn Guo pdev->name)) { 605a580b8c5SShawn Guo ret = -EBUSY; 606a580b8c5SShawn Guo goto err_request_region; 607a580b8c5SShawn Guo } 608a580b8c5SShawn Guo 609a580b8c5SShawn Guo mxs_dma->base = ioremap(iores->start, resource_size(iores)); 610a580b8c5SShawn Guo if (!mxs_dma->base) { 611a580b8c5SShawn Guo ret = -ENOMEM; 612a580b8c5SShawn Guo goto err_ioremap; 613a580b8c5SShawn Guo } 614a580b8c5SShawn Guo 615a580b8c5SShawn Guo mxs_dma->clk = clk_get(&pdev->dev, NULL); 616a580b8c5SShawn Guo if (IS_ERR(mxs_dma->clk)) { 617a580b8c5SShawn Guo ret = PTR_ERR(mxs_dma->clk); 618a580b8c5SShawn Guo goto err_clk; 619a580b8c5SShawn Guo } 620a580b8c5SShawn Guo 621a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 622a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 623a580b8c5SShawn Guo 624a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 625a580b8c5SShawn Guo 626a580b8c5SShawn Guo /* Initialize channel parameters */ 627a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) { 628a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 629a580b8c5SShawn Guo 630a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma; 631a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device; 632a580b8c5SShawn Guo 633a580b8c5SShawn Guo tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 634a580b8c5SShawn Guo (unsigned long) mxs_chan); 635a580b8c5SShawn Guo 636a580b8c5SShawn Guo 637a580b8c5SShawn Guo /* Add the channel to mxs_chan list */ 638a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node, 639a580b8c5SShawn Guo &mxs_dma->dma_device.channels); 640a580b8c5SShawn Guo } 641a580b8c5SShawn Guo 642a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma); 643a580b8c5SShawn Guo if (ret) 644a580b8c5SShawn Guo goto err_init; 645a580b8c5SShawn Guo 646a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev; 647a580b8c5SShawn Guo 648a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */ 649a580b8c5SShawn Guo mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 650a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 651a580b8c5SShawn Guo 652a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 653a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 654a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 655a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 656a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 657a580b8c5SShawn Guo mxs_dma->dma_device.device_control = mxs_dma_control; 658a580b8c5SShawn Guo mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; 659a580b8c5SShawn Guo 660a580b8c5SShawn Guo ret = dma_async_device_register(&mxs_dma->dma_device); 661a580b8c5SShawn Guo if (ret) { 662a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 663a580b8c5SShawn Guo goto err_init; 664a580b8c5SShawn Guo } 665a580b8c5SShawn Guo 666a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n"); 667a580b8c5SShawn Guo 668a580b8c5SShawn Guo return 0; 669a580b8c5SShawn Guo 670a580b8c5SShawn Guo err_init: 671a580b8c5SShawn Guo clk_put(mxs_dma->clk); 672a580b8c5SShawn Guo err_clk: 673a580b8c5SShawn Guo iounmap(mxs_dma->base); 674a580b8c5SShawn Guo err_ioremap: 675a580b8c5SShawn Guo release_mem_region(iores->start, resource_size(iores)); 676a580b8c5SShawn Guo err_request_region: 677a580b8c5SShawn Guo kfree(mxs_dma); 678a580b8c5SShawn Guo return ret; 679a580b8c5SShawn Guo } 680a580b8c5SShawn Guo 681a580b8c5SShawn Guo static struct platform_device_id mxs_dma_type[] = { 682a580b8c5SShawn Guo { 683a580b8c5SShawn Guo .name = "mxs-dma-apbh", 684a580b8c5SShawn Guo .driver_data = MXS_DMA_APBH, 685a580b8c5SShawn Guo }, { 686a580b8c5SShawn Guo .name = "mxs-dma-apbx", 687a580b8c5SShawn Guo .driver_data = MXS_DMA_APBX, 6882a9778edSAxel Lin }, { 6892a9778edSAxel Lin /* end of list */ 690a580b8c5SShawn Guo } 691a580b8c5SShawn Guo }; 692a580b8c5SShawn Guo 693a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = { 694a580b8c5SShawn Guo .driver = { 695a580b8c5SShawn Guo .name = "mxs-dma", 696a580b8c5SShawn Guo }, 697a580b8c5SShawn Guo .id_table = mxs_dma_type, 698a580b8c5SShawn Guo }; 699a580b8c5SShawn Guo 700a580b8c5SShawn Guo static int __init mxs_dma_module_init(void) 701a580b8c5SShawn Guo { 702a580b8c5SShawn Guo return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 703a580b8c5SShawn Guo } 704a580b8c5SShawn Guo subsys_initcall(mxs_dma_module_init); 705