1a580b8c5SShawn Guo /* 2a580b8c5SShawn Guo * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3a580b8c5SShawn Guo * 4a580b8c5SShawn Guo * Refer to drivers/dma/imx-sdma.c 5a580b8c5SShawn Guo * 6a580b8c5SShawn Guo * This program is free software; you can redistribute it and/or modify 7a580b8c5SShawn Guo * it under the terms of the GNU General Public License version 2 as 8a580b8c5SShawn Guo * published by the Free Software Foundation. 9a580b8c5SShawn Guo */ 10a580b8c5SShawn Guo 11a580b8c5SShawn Guo #include <linux/init.h> 12a580b8c5SShawn Guo #include <linux/types.h> 13a580b8c5SShawn Guo #include <linux/mm.h> 14a580b8c5SShawn Guo #include <linux/interrupt.h> 15a580b8c5SShawn Guo #include <linux/clk.h> 16a580b8c5SShawn Guo #include <linux/wait.h> 17a580b8c5SShawn Guo #include <linux/sched.h> 18a580b8c5SShawn Guo #include <linux/semaphore.h> 19a580b8c5SShawn Guo #include <linux/device.h> 20a580b8c5SShawn Guo #include <linux/dma-mapping.h> 21a580b8c5SShawn Guo #include <linux/slab.h> 22a580b8c5SShawn Guo #include <linux/platform_device.h> 23a580b8c5SShawn Guo #include <linux/dmaengine.h> 24a580b8c5SShawn Guo #include <linux/delay.h> 2590c9abc5SDong Aisheng #include <linux/module.h> 26f5b7efccSDong Aisheng #include <linux/stmp_device.h> 2790c9abc5SDong Aisheng #include <linux/of.h> 2890c9abc5SDong Aisheng #include <linux/of_device.h> 29d84f638bSShawn Guo #include <linux/of_dma.h> 30b2d63989SMarkus Pargmann #include <linux/list.h> 31a580b8c5SShawn Guo 32a580b8c5SShawn Guo #include <asm/irq.h> 33a580b8c5SShawn Guo 34d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 35d2ebfb33SRussell King - ARM Linux 36a580b8c5SShawn Guo /* 37a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means 38a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, 39a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices. 40a580b8c5SShawn Guo */ 41a580b8c5SShawn Guo 428c920136SShawn Guo #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) 438c920136SShawn Guo #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) 44a580b8c5SShawn Guo 45a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000 46a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) 47a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) 48a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16 49a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010 50a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020 51a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030 52a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 53bb11fb63SShawn Guo /* 54bb11fb63SShawn Guo * The offset of NXTCMDAR register is different per both dma type and version, 55bb11fb63SShawn Guo * while stride for each channel is all the same 0x70. 56bb11fb63SShawn Guo */ 57bb11fb63SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(d, n) \ 58bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) 59bb11fb63SShawn Guo #define HW_APBHX_CHn_SEMA(d, n) \ 60bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) 617b11304aSMarkus Pargmann #define HW_APBHX_CHn_BAR(d, n) \ 627b11304aSMarkus Pargmann (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70) 63702e94d6SMarkus Pargmann #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70) 64a580b8c5SShawn Guo 65a580b8c5SShawn Guo /* 66a580b8c5SShawn Guo * ccw bits definitions 67a580b8c5SShawn Guo * 68a580b8c5SShawn Guo * COMMAND: 0..1 (2) 69a580b8c5SShawn Guo * CHAIN: 2 (1) 70a580b8c5SShawn Guo * IRQ: 3 (1) 71a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented 72a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented 73a580b8c5SShawn Guo * DEC_SEM: 6 (1) 74a580b8c5SShawn Guo * WAIT4END: 7 (1) 75a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1) 76a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1) 77a580b8c5SShawn Guo * RESERVED: 10..11 (2) 78a580b8c5SShawn Guo * PIO_NUM: 12..15 (4) 79a580b8c5SShawn Guo */ 80a580b8c5SShawn Guo #define BP_CCW_COMMAND 0 81a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0) 82a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2) 83a580b8c5SShawn Guo #define CCW_IRQ (1 << 3) 84a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6) 85a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7) 86a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8) 87a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9) 88a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12 89a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12) 90a580b8c5SShawn Guo 91a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) 92a580b8c5SShawn Guo 93a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0 94a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1 95a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2 96a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ 97a580b8c5SShawn Guo 98a580b8c5SShawn Guo struct mxs_dma_ccw { 99a580b8c5SShawn Guo u32 next; 100a580b8c5SShawn Guo u16 bits; 101a580b8c5SShawn Guo u16 xfer_bytes; 102a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00 103a580b8c5SShawn Guo u32 bufaddr; 104a580b8c5SShawn Guo #define MXS_PIO_WORDS 16 105a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS]; 106a580b8c5SShawn Guo }; 107a580b8c5SShawn Guo 1085e97fa91SMarek Vasut #define CCW_BLOCK_SIZE (4 * PAGE_SIZE) 1095e97fa91SMarek Vasut #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw)) 110a580b8c5SShawn Guo 111a580b8c5SShawn Guo struct mxs_dma_chan { 112a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 113a580b8c5SShawn Guo struct dma_chan chan; 114a580b8c5SShawn Guo struct dma_async_tx_descriptor desc; 115a580b8c5SShawn Guo struct tasklet_struct tasklet; 116f2ad6992SFabio Estevam unsigned int chan_irq; 117a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 118a580b8c5SShawn Guo dma_addr_t ccw_phys; 1196d23ea4bSLothar Waßmann int desc_count; 120a580b8c5SShawn Guo enum dma_status status; 121a580b8c5SShawn Guo unsigned int flags; 1222dcbdce3SMarkus Pargmann bool reset; 123a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0) 1242dcbdce3SMarkus Pargmann #define MXS_DMA_USE_SEMAPHORE (1 << 1) 125a580b8c5SShawn Guo }; 126a580b8c5SShawn Guo 127a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16 128a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff 129a580b8c5SShawn Guo 1308c920136SShawn Guo enum mxs_dma_devtype { 1318c920136SShawn Guo MXS_DMA_APBH, 1328c920136SShawn Guo MXS_DMA_APBX, 1338c920136SShawn Guo }; 1348c920136SShawn Guo 1358c920136SShawn Guo enum mxs_dma_id { 1368c920136SShawn Guo IMX23_DMA, 1378c920136SShawn Guo IMX28_DMA, 1388c920136SShawn Guo }; 1398c920136SShawn Guo 140a580b8c5SShawn Guo struct mxs_dma_engine { 1418c920136SShawn Guo enum mxs_dma_id dev_id; 1428c920136SShawn Guo enum mxs_dma_devtype type; 143a580b8c5SShawn Guo void __iomem *base; 144a580b8c5SShawn Guo struct clk *clk; 145a580b8c5SShawn Guo struct dma_device dma_device; 146a580b8c5SShawn Guo struct device_dma_parameters dma_parms; 147a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; 148d84f638bSShawn Guo struct platform_device *pdev; 149d84f638bSShawn Guo unsigned int nr_channels; 150a580b8c5SShawn Guo }; 151a580b8c5SShawn Guo 1528c920136SShawn Guo struct mxs_dma_type { 1538c920136SShawn Guo enum mxs_dma_id id; 1548c920136SShawn Guo enum mxs_dma_devtype type; 1558c920136SShawn Guo }; 1568c920136SShawn Guo 1578c920136SShawn Guo static struct mxs_dma_type mxs_dma_types[] = { 1588c920136SShawn Guo { 1598c920136SShawn Guo .id = IMX23_DMA, 1608c920136SShawn Guo .type = MXS_DMA_APBH, 1618c920136SShawn Guo }, { 1628c920136SShawn Guo .id = IMX23_DMA, 1638c920136SShawn Guo .type = MXS_DMA_APBX, 1648c920136SShawn Guo }, { 1658c920136SShawn Guo .id = IMX28_DMA, 1668c920136SShawn Guo .type = MXS_DMA_APBH, 1678c920136SShawn Guo }, { 1688c920136SShawn Guo .id = IMX28_DMA, 1698c920136SShawn Guo .type = MXS_DMA_APBX, 1708c920136SShawn Guo } 1718c920136SShawn Guo }; 1728c920136SShawn Guo 1730d850504SKrzysztof Kozlowski static const struct platform_device_id mxs_dma_ids[] = { 1748c920136SShawn Guo { 1758c920136SShawn Guo .name = "imx23-dma-apbh", 1768c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[0], 1778c920136SShawn Guo }, { 1788c920136SShawn Guo .name = "imx23-dma-apbx", 1798c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[1], 1808c920136SShawn Guo }, { 1818c920136SShawn Guo .name = "imx28-dma-apbh", 1828c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[2], 1838c920136SShawn Guo }, { 1848c920136SShawn Guo .name = "imx28-dma-apbx", 1858c920136SShawn Guo .driver_data = (kernel_ulong_t) &mxs_dma_types[3], 1868c920136SShawn Guo }, { 1878c920136SShawn Guo /* end of list */ 1888c920136SShawn Guo } 1898c920136SShawn Guo }; 1908c920136SShawn Guo 19190c9abc5SDong Aisheng static const struct of_device_id mxs_dma_dt_ids[] = { 19290c9abc5SDong Aisheng { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], }, 19390c9abc5SDong Aisheng { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, 19490c9abc5SDong Aisheng { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, 19590c9abc5SDong Aisheng { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, 19690c9abc5SDong Aisheng { /* sentinel */ } 19790c9abc5SDong Aisheng }; 19890c9abc5SDong Aisheng MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); 19990c9abc5SDong Aisheng 2008c920136SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) 2018c920136SShawn Guo { 2028c920136SShawn Guo return container_of(chan, struct mxs_dma_chan, chan); 2038c920136SShawn Guo } 2048c920136SShawn Guo 2055c9d2e37SMaxime Ripard static void mxs_dma_reset_chan(struct dma_chan *chan) 206a580b8c5SShawn Guo { 2075c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 208a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 209a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 210a580b8c5SShawn Guo 2112dcbdce3SMarkus Pargmann /* 2122dcbdce3SMarkus Pargmann * mxs dma channel resets can cause a channel stall. To recover from a 2132dcbdce3SMarkus Pargmann * channel stall, we have to reset the whole DMA engine. To avoid this, 2142dcbdce3SMarkus Pargmann * we use cyclic DMA with semaphores, that are enhanced in 2152dcbdce3SMarkus Pargmann * mxs_dma_int_handler. To reset the channel, we can simply stop writing 2162dcbdce3SMarkus Pargmann * into the semaphore counter. 2172dcbdce3SMarkus Pargmann */ 2182dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 2192dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 2202dcbdce3SMarkus Pargmann mxs_chan->reset = true; 2212dcbdce3SMarkus Pargmann } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) { 222a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), 223f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 224702e94d6SMarkus Pargmann } else { 225702e94d6SMarkus Pargmann unsigned long elapsed = 0; 226702e94d6SMarkus Pargmann const unsigned long max_wait = 50000; /* 50ms */ 227702e94d6SMarkus Pargmann void __iomem *reg_dbg1 = mxs_dma->base + 228702e94d6SMarkus Pargmann HW_APBX_CHn_DEBUG1(mxs_dma, chan_id); 229702e94d6SMarkus Pargmann 230702e94d6SMarkus Pargmann /* 231702e94d6SMarkus Pargmann * On i.MX28 APBX, the DMA channel can stop working if we reset 232702e94d6SMarkus Pargmann * the channel while it is in READ_FLUSH (0x08) state. 233702e94d6SMarkus Pargmann * We wait here until we leave the state. Then we trigger the 234702e94d6SMarkus Pargmann * reset. Waiting a maximum of 50ms, the kernel shouldn't crash 235702e94d6SMarkus Pargmann * because of this. 236702e94d6SMarkus Pargmann */ 237702e94d6SMarkus Pargmann while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) { 238702e94d6SMarkus Pargmann udelay(100); 239702e94d6SMarkus Pargmann elapsed += 100; 240702e94d6SMarkus Pargmann } 241702e94d6SMarkus Pargmann 242702e94d6SMarkus Pargmann if (elapsed >= max_wait) 243702e94d6SMarkus Pargmann dev_err(&mxs_chan->mxs_dma->pdev->dev, 244702e94d6SMarkus Pargmann "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n", 245702e94d6SMarkus Pargmann chan_id); 246702e94d6SMarkus Pargmann 247a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), 248f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 249a580b8c5SShawn Guo } 250bb3660f1SMarkus Pargmann 251bb3660f1SMarkus Pargmann mxs_chan->status = DMA_COMPLETE; 252702e94d6SMarkus Pargmann } 253a580b8c5SShawn Guo 2545c9d2e37SMaxime Ripard static void mxs_dma_enable_chan(struct dma_chan *chan) 255a580b8c5SShawn Guo { 2565c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 257a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 258a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 259a580b8c5SShawn Guo 260a580b8c5SShawn Guo /* set cmd_addr up */ 261a580b8c5SShawn Guo writel(mxs_chan->ccw_phys, 262bb11fb63SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); 263a580b8c5SShawn Guo 264a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */ 2652dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE && 2662dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 2672dcbdce3SMarkus Pargmann /* A cyclic DMA consists of at least 2 segments, so initialize 2682dcbdce3SMarkus Pargmann * the semaphore with 2 so we have enough time to add 1 to the 2692dcbdce3SMarkus Pargmann * semaphore if we need to */ 2702dcbdce3SMarkus Pargmann writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 2712dcbdce3SMarkus Pargmann } else { 272bb11fb63SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); 273a580b8c5SShawn Guo } 2742dcbdce3SMarkus Pargmann mxs_chan->reset = false; 2752dcbdce3SMarkus Pargmann } 276a580b8c5SShawn Guo 2775c9d2e37SMaxime Ripard static void mxs_dma_disable_chan(struct dma_chan *chan) 278a580b8c5SShawn Guo { 2795c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 2805c9d2e37SMaxime Ripard 2812737583eSVinod Koul mxs_chan->status = DMA_COMPLETE; 282a580b8c5SShawn Guo } 283a580b8c5SShawn Guo 284a29c3956SVinod Koul static int mxs_dma_pause_chan(struct dma_chan *chan) 285a580b8c5SShawn Guo { 2865c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 287a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 288a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 289a580b8c5SShawn Guo 290a580b8c5SShawn Guo /* freeze the channel */ 291bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 292a580b8c5SShawn Guo writel(1 << chan_id, 293f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 294a580b8c5SShawn Guo else 295a580b8c5SShawn Guo writel(1 << chan_id, 296f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); 297a580b8c5SShawn Guo 298a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED; 299a29c3956SVinod Koul return 0; 300a580b8c5SShawn Guo } 301a580b8c5SShawn Guo 302a29c3956SVinod Koul static int mxs_dma_resume_chan(struct dma_chan *chan) 303a580b8c5SShawn Guo { 3045c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 305a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 306a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id; 307a580b8c5SShawn Guo 308a580b8c5SShawn Guo /* unfreeze the channel */ 309bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) 310a580b8c5SShawn Guo writel(1 << chan_id, 311f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); 312a580b8c5SShawn Guo else 313a580b8c5SShawn Guo writel(1 << chan_id, 314f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); 315a580b8c5SShawn Guo 316a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 317a29c3956SVinod Koul return 0; 318a580b8c5SShawn Guo } 319a580b8c5SShawn Guo 320a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) 321a580b8c5SShawn Guo { 322884485e1SRussell King - ARM Linux return dma_cookie_assign(tx); 323a580b8c5SShawn Guo } 324a580b8c5SShawn Guo 325a580b8c5SShawn Guo static void mxs_dma_tasklet(unsigned long data) 326a580b8c5SShawn Guo { 327a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; 328a580b8c5SShawn Guo 329064370c6SDave Jiang dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL); 330a580b8c5SShawn Guo } 331a580b8c5SShawn Guo 332b2d63989SMarkus Pargmann static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq) 333b2d63989SMarkus Pargmann { 334b2d63989SMarkus Pargmann int i; 335b2d63989SMarkus Pargmann 336b2d63989SMarkus Pargmann for (i = 0; i != mxs_dma->nr_channels; ++i) 337b2d63989SMarkus Pargmann if (mxs_dma->mxs_chans[i].chan_irq == irq) 338b2d63989SMarkus Pargmann return i; 339b2d63989SMarkus Pargmann 340b2d63989SMarkus Pargmann return -EINVAL; 341b2d63989SMarkus Pargmann } 342b2d63989SMarkus Pargmann 343a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) 344a580b8c5SShawn Guo { 345a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id; 346b2d63989SMarkus Pargmann struct mxs_dma_chan *mxs_chan; 347b2d63989SMarkus Pargmann u32 completed; 348b2d63989SMarkus Pargmann u32 err; 349b2d63989SMarkus Pargmann int chan = mxs_dma_irq_to_chan(mxs_dma, irq); 350b2d63989SMarkus Pargmann 351b2d63989SMarkus Pargmann if (chan < 0) 352b2d63989SMarkus Pargmann return IRQ_NONE; 353a580b8c5SShawn Guo 354a580b8c5SShawn Guo /* completion status */ 355b2d63989SMarkus Pargmann completed = readl(mxs_dma->base + HW_APBHX_CTRL1); 356b2d63989SMarkus Pargmann completed = (completed >> chan) & 0x1; 357b2d63989SMarkus Pargmann 358b2d63989SMarkus Pargmann /* Clear interrupt */ 359b2d63989SMarkus Pargmann writel((1 << chan), 360b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); 361a580b8c5SShawn Guo 362a580b8c5SShawn Guo /* error status */ 363b2d63989SMarkus Pargmann err = readl(mxs_dma->base + HW_APBHX_CTRL2); 364b2d63989SMarkus Pargmann err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan); 365b2d63989SMarkus Pargmann 366b2d63989SMarkus Pargmann /* 367b2d63989SMarkus Pargmann * error status bit is in the upper 16 bits, error irq bit in the lower 368b2d63989SMarkus Pargmann * 16 bits. We transform it into a simpler error code: 369b2d63989SMarkus Pargmann * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR 370b2d63989SMarkus Pargmann */ 371b2d63989SMarkus Pargmann err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan); 372b2d63989SMarkus Pargmann 373b2d63989SMarkus Pargmann /* Clear error irq */ 374b2d63989SMarkus Pargmann writel((1 << chan), 375b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); 376a580b8c5SShawn Guo 377a580b8c5SShawn Guo /* 378a580b8c5SShawn Guo * When both completion and error of termination bits set at the 379a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes 380b2d63989SMarkus Pargmann * an error we need to handle here in case of either it's a bus 381b2d63989SMarkus Pargmann * error or a termination error with no completion. 0x01 is termination 382b2d63989SMarkus Pargmann * error, so we can subtract err & completed to get the real error case. 383a580b8c5SShawn Guo */ 384b2d63989SMarkus Pargmann err -= err & completed; 385a580b8c5SShawn Guo 386b2d63989SMarkus Pargmann mxs_chan = &mxs_dma->mxs_chans[chan]; 387a580b8c5SShawn Guo 388b2d63989SMarkus Pargmann if (err) { 389a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev, 390a580b8c5SShawn Guo "%s: error in channel %d\n", __func__, 391b2d63989SMarkus Pargmann chan); 392a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 393e0cad7a0SVinod Koul mxs_dma_reset_chan(&mxs_chan->chan); 394bb3660f1SMarkus Pargmann } else if (mxs_chan->status != DMA_COMPLETE) { 3952dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_SG_LOOP) { 396a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 3972dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE) 3982dcbdce3SMarkus Pargmann writel(1, mxs_dma->base + 3992dcbdce3SMarkus Pargmann HW_APBHX_CHn_SEMA(mxs_dma, chan)); 4002dcbdce3SMarkus Pargmann } else { 4012737583eSVinod Koul mxs_chan->status = DMA_COMPLETE; 402a580b8c5SShawn Guo } 4032dcbdce3SMarkus Pargmann } 404a580b8c5SShawn Guo 4052dcbdce3SMarkus Pargmann if (mxs_chan->status == DMA_COMPLETE) { 4062dcbdce3SMarkus Pargmann if (mxs_chan->reset) 4072dcbdce3SMarkus Pargmann return IRQ_HANDLED; 408f7fbce07SRussell King - ARM Linux dma_cookie_complete(&mxs_chan->desc); 4092dcbdce3SMarkus Pargmann } 410a580b8c5SShawn Guo 411a580b8c5SShawn Guo /* schedule tasklet on this channel */ 412a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet); 413a580b8c5SShawn Guo 414a580b8c5SShawn Guo return IRQ_HANDLED; 415a580b8c5SShawn Guo } 416a580b8c5SShawn Guo 417a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) 418a580b8c5SShawn Guo { 419a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 420a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 421a580b8c5SShawn Guo int ret; 422a580b8c5SShawn Guo 4239f92d223SJoe Perches mxs_chan->ccw = dma_zalloc_coherent(mxs_dma->dma_device.dev, 4249f92d223SJoe Perches CCW_BLOCK_SIZE, 4259f92d223SJoe Perches &mxs_chan->ccw_phys, GFP_KERNEL); 426a580b8c5SShawn Guo if (!mxs_chan->ccw) { 427a580b8c5SShawn Guo ret = -ENOMEM; 428a580b8c5SShawn Guo goto err_alloc; 429a580b8c5SShawn Guo } 430a580b8c5SShawn Guo 431a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, 432a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma); 433a580b8c5SShawn Guo if (ret) 434a580b8c5SShawn Guo goto err_irq; 435a580b8c5SShawn Guo 436759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 437a580b8c5SShawn Guo if (ret) 438a580b8c5SShawn Guo goto err_clk; 439a580b8c5SShawn Guo 4405c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan); 441a580b8c5SShawn Guo 442a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan); 443a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit; 444a580b8c5SShawn Guo 445a580b8c5SShawn Guo /* the descriptor is ready */ 446a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc); 447a580b8c5SShawn Guo 448a580b8c5SShawn Guo return 0; 449a580b8c5SShawn Guo 450a580b8c5SShawn Guo err_clk: 451a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 452a580b8c5SShawn Guo err_irq: 4535e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 454a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 455a580b8c5SShawn Guo err_alloc: 456a580b8c5SShawn Guo return ret; 457a580b8c5SShawn Guo } 458a580b8c5SShawn Guo 459a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan) 460a580b8c5SShawn Guo { 461a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 462a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 463a580b8c5SShawn Guo 4645c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan); 465a580b8c5SShawn Guo 466a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma); 467a580b8c5SShawn Guo 4685e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, 469a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys); 470a580b8c5SShawn Guo 471759a2e30SShawn Guo clk_disable_unprepare(mxs_dma->clk); 472a580b8c5SShawn Guo } 473a580b8c5SShawn Guo 474921de864SHuang Shijie /* 475921de864SHuang Shijie * How to use the flags for ->device_prep_slave_sg() : 476921de864SHuang Shijie * [1] If there is only one DMA command in the DMA chain, the code should be: 477921de864SHuang Shijie * ...... 478921de864SHuang Shijie * ->device_prep_slave_sg(DMA_CTRL_ACK); 479921de864SHuang Shijie * ...... 480921de864SHuang Shijie * [2] If there are two DMA commands in the DMA chain, the code should be 481921de864SHuang Shijie * ...... 482921de864SHuang Shijie * ->device_prep_slave_sg(0); 483921de864SHuang Shijie * ...... 484921de864SHuang Shijie * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 485921de864SHuang Shijie * ...... 486921de864SHuang Shijie * [3] If there are more than two DMA commands in the DMA chain, the code 487921de864SHuang Shijie * should be: 488921de864SHuang Shijie * ...... 489921de864SHuang Shijie * ->device_prep_slave_sg(0); // First 490921de864SHuang Shijie * ...... 491921de864SHuang Shijie * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]); 492921de864SHuang Shijie * ...... 493921de864SHuang Shijie * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last 494921de864SHuang Shijie * ...... 495921de864SHuang Shijie */ 496a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 497a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl, 498db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 499623ff773SLinus Torvalds unsigned long flags, void *context) 500a580b8c5SShawn Guo { 501a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 502a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 503a580b8c5SShawn Guo struct mxs_dma_ccw *ccw; 504a580b8c5SShawn Guo struct scatterlist *sg; 505f2ad6992SFabio Estevam u32 i, j; 506a580b8c5SShawn Guo u32 *pio; 507921de864SHuang Shijie bool append = flags & DMA_PREP_INTERRUPT; 5086d23ea4bSLothar Waßmann int idx = append ? mxs_chan->desc_count : 0; 509a580b8c5SShawn Guo 510a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS && !append) 511a580b8c5SShawn Guo return NULL; 512a580b8c5SShawn Guo 513a580b8c5SShawn Guo if (sg_len + (append ? idx : 0) > NUM_CCW) { 514a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 515a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 516a580b8c5SShawn Guo sg_len, NUM_CCW); 517a580b8c5SShawn Guo goto err_out; 518a580b8c5SShawn Guo } 519a580b8c5SShawn Guo 520a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 521a580b8c5SShawn Guo mxs_chan->flags = 0; 522a580b8c5SShawn Guo 523a580b8c5SShawn Guo /* 524a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg 525a580b8c5SShawn Guo * will be appended to the last prepared sg. 526a580b8c5SShawn Guo */ 527a580b8c5SShawn Guo if (append) { 528a580b8c5SShawn Guo BUG_ON(idx < 1); 529a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1]; 530a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 531a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 532a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ; 533a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM; 534a580b8c5SShawn Guo } else { 535a580b8c5SShawn Guo idx = 0; 536a580b8c5SShawn Guo } 537a580b8c5SShawn Guo 53862268ce9SShawn Guo if (direction == DMA_TRANS_NONE) { 539a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 540a580b8c5SShawn Guo pio = (u32 *) sgl; 541a580b8c5SShawn Guo 542a580b8c5SShawn Guo for (j = 0; j < sg_len;) 543a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++; 544a580b8c5SShawn Guo 545a580b8c5SShawn Guo ccw->bits = 0; 546a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 547a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 548921de864SHuang Shijie if (flags & DMA_CTRL_ACK) 549a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 550a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 551a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 552a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM); 553a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 554a580b8c5SShawn Guo } else { 555a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) { 556fdaf9c4bSLars-Peter Clausen if (sg_dma_len(sg) > MAX_XFER_BYTES) { 557a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 558fdaf9c4bSLars-Peter Clausen sg_dma_len(sg), MAX_XFER_BYTES); 559a580b8c5SShawn Guo goto err_out; 560a580b8c5SShawn Guo } 561a580b8c5SShawn Guo 562a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++]; 563a580b8c5SShawn Guo 564a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 565a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address; 566fdaf9c4bSLars-Peter Clausen ccw->xfer_bytes = sg_dma_len(sg); 567a580b8c5SShawn Guo 568a580b8c5SShawn Guo ccw->bits = 0; 569a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 570a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 571a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 572db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 573a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 574a580b8c5SShawn Guo COMMAND); 575a580b8c5SShawn Guo 576a580b8c5SShawn Guo if (i + 1 == sg_len) { 577a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN; 578a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 579a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM; 580921de864SHuang Shijie if (flags & DMA_CTRL_ACK) 581a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END; 582a580b8c5SShawn Guo } 583a580b8c5SShawn Guo } 584a580b8c5SShawn Guo } 5856d23ea4bSLothar Waßmann mxs_chan->desc_count = idx; 586a580b8c5SShawn Guo 587a580b8c5SShawn Guo return &mxs_chan->desc; 588a580b8c5SShawn Guo 589a580b8c5SShawn Guo err_out: 590a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 591a580b8c5SShawn Guo return NULL; 592a580b8c5SShawn Guo } 593a580b8c5SShawn Guo 594a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 595a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 596185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 59731c1e5a1SLaurent Pinchart unsigned long flags) 598a580b8c5SShawn Guo { 599a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 600a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 601f2ad6992SFabio Estevam u32 num_periods = buf_len / period_len; 602f2ad6992SFabio Estevam u32 i = 0, buf = 0; 603a580b8c5SShawn Guo 604a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS) 605a580b8c5SShawn Guo return NULL; 606a580b8c5SShawn Guo 607a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS; 608a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP; 6092dcbdce3SMarkus Pargmann mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE; 610a580b8c5SShawn Guo 611a580b8c5SShawn Guo if (num_periods > NUM_CCW) { 612a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 613a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n", 614a580b8c5SShawn Guo num_periods, NUM_CCW); 615a580b8c5SShawn Guo goto err_out; 616a580b8c5SShawn Guo } 617a580b8c5SShawn Guo 618a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) { 619a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, 6204aff2f93SFabio Estevam "maximum period size exceeded: %zu > %d\n", 621a580b8c5SShawn Guo period_len, MAX_XFER_BYTES); 622a580b8c5SShawn Guo goto err_out; 623a580b8c5SShawn Guo } 624a580b8c5SShawn Guo 625a580b8c5SShawn Guo while (buf < buf_len) { 626a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; 627a580b8c5SShawn Guo 628a580b8c5SShawn Guo if (i + 1 == num_periods) 629a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys; 630a580b8c5SShawn Guo else 631a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); 632a580b8c5SShawn Guo 633a580b8c5SShawn Guo ccw->bufaddr = dma_addr; 634a580b8c5SShawn Guo ccw->xfer_bytes = period_len; 635a580b8c5SShawn Guo 636a580b8c5SShawn Guo ccw->bits = 0; 637a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN; 638a580b8c5SShawn Guo ccw->bits |= CCW_IRQ; 639a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM; 640a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH; 6412dcbdce3SMarkus Pargmann ccw->bits |= CCW_DEC_SEM; 642db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? 643a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 644a580b8c5SShawn Guo 645a580b8c5SShawn Guo dma_addr += period_len; 646a580b8c5SShawn Guo buf += period_len; 647a580b8c5SShawn Guo 648a580b8c5SShawn Guo i++; 649a580b8c5SShawn Guo } 6506d23ea4bSLothar Waßmann mxs_chan->desc_count = i; 651a580b8c5SShawn Guo 652a580b8c5SShawn Guo return &mxs_chan->desc; 653a580b8c5SShawn Guo 654a580b8c5SShawn Guo err_out: 655a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR; 656a580b8c5SShawn Guo return NULL; 657a580b8c5SShawn Guo } 658a580b8c5SShawn Guo 6595c9d2e37SMaxime Ripard static int mxs_dma_terminate_all(struct dma_chan *chan) 660a580b8c5SShawn Guo { 6615c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan); 6625c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan); 663a580b8c5SShawn Guo 6645c9d2e37SMaxime Ripard return 0; 665a580b8c5SShawn Guo } 666a580b8c5SShawn Guo 667a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, 668a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate) 669a580b8c5SShawn Guo { 670a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 6717b11304aSMarkus Pargmann struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 6727b11304aSMarkus Pargmann u32 residue = 0; 673a580b8c5SShawn Guo 6747b11304aSMarkus Pargmann if (mxs_chan->status == DMA_IN_PROGRESS && 6757b11304aSMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) { 6767b11304aSMarkus Pargmann struct mxs_dma_ccw *last_ccw; 6777b11304aSMarkus Pargmann u32 bar; 6787b11304aSMarkus Pargmann 6797b11304aSMarkus Pargmann last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1]; 6807b11304aSMarkus Pargmann residue = last_ccw->xfer_bytes + last_ccw->bufaddr; 6817b11304aSMarkus Pargmann 6827b11304aSMarkus Pargmann bar = readl(mxs_dma->base + 6837b11304aSMarkus Pargmann HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id)); 6847b11304aSMarkus Pargmann residue -= bar; 6857b11304aSMarkus Pargmann } 6867b11304aSMarkus Pargmann 6877b11304aSMarkus Pargmann dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 6887b11304aSMarkus Pargmann residue); 689a580b8c5SShawn Guo 690a580b8c5SShawn Guo return mxs_chan->status; 691a580b8c5SShawn Guo } 692a580b8c5SShawn Guo 693a580b8c5SShawn Guo static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) 694a580b8c5SShawn Guo { 695a580b8c5SShawn Guo int ret; 696a580b8c5SShawn Guo 697759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk); 698a580b8c5SShawn Guo if (ret) 699feb397deSLothar Waßmann return ret; 700a580b8c5SShawn Guo 701f5b7efccSDong Aisheng ret = stmp_reset_block(mxs_dma->base); 702a580b8c5SShawn Guo if (ret) 703a580b8c5SShawn Guo goto err_out; 704a580b8c5SShawn Guo 705a580b8c5SShawn Guo /* enable apbh burst */ 706bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma)) { 707a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN, 708f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 709a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN, 710f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); 711a580b8c5SShawn Guo } 712a580b8c5SShawn Guo 713a580b8c5SShawn Guo /* enable irq for all the channels */ 714a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, 715f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); 716a580b8c5SShawn Guo 717a580b8c5SShawn Guo err_out: 71857f2685cSLinus Torvalds clk_disable_unprepare(mxs_dma->clk); 719a580b8c5SShawn Guo return ret; 720a580b8c5SShawn Guo } 721a580b8c5SShawn Guo 722d84f638bSShawn Guo struct mxs_dma_filter_param { 723d84f638bSShawn Guo struct device_node *of_node; 724d84f638bSShawn Guo unsigned int chan_id; 725d84f638bSShawn Guo }; 726d84f638bSShawn Guo 727d84f638bSShawn Guo static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) 728d84f638bSShawn Guo { 729d84f638bSShawn Guo struct mxs_dma_filter_param *param = fn_param; 730d84f638bSShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 731d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 732d84f638bSShawn Guo int chan_irq; 733d84f638bSShawn Guo 734d84f638bSShawn Guo if (mxs_dma->dma_device.dev->of_node != param->of_node) 735d84f638bSShawn Guo return false; 736d84f638bSShawn Guo 737d84f638bSShawn Guo if (chan->chan_id != param->chan_id) 738d84f638bSShawn Guo return false; 739d84f638bSShawn Guo 740d84f638bSShawn Guo chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id); 741d84f638bSShawn Guo if (chan_irq < 0) 742d84f638bSShawn Guo return false; 743d84f638bSShawn Guo 744d84f638bSShawn Guo mxs_chan->chan_irq = chan_irq; 745d84f638bSShawn Guo 746d84f638bSShawn Guo return true; 747d84f638bSShawn Guo } 748d84f638bSShawn Guo 7493208b370SFabio Estevam static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, 750d84f638bSShawn Guo struct of_dma *ofdma) 751d84f638bSShawn Guo { 752d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data; 753d84f638bSShawn Guo dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; 754d84f638bSShawn Guo struct mxs_dma_filter_param param; 755d84f638bSShawn Guo 756d84f638bSShawn Guo if (dma_spec->args_count != 1) 757d84f638bSShawn Guo return NULL; 758d84f638bSShawn Guo 759d84f638bSShawn Guo param.of_node = ofdma->of_node; 760d84f638bSShawn Guo param.chan_id = dma_spec->args[0]; 761d84f638bSShawn Guo 762d84f638bSShawn Guo if (param.chan_id >= mxs_dma->nr_channels) 763d84f638bSShawn Guo return NULL; 764d84f638bSShawn Guo 765d84f638bSShawn Guo return dma_request_channel(mask, mxs_dma_filter_fn, ¶m); 766d84f638bSShawn Guo } 767d84f638bSShawn Guo 768a580b8c5SShawn Guo static int __init mxs_dma_probe(struct platform_device *pdev) 769a580b8c5SShawn Guo { 770d84f638bSShawn Guo struct device_node *np = pdev->dev.of_node; 77190c9abc5SDong Aisheng const struct platform_device_id *id_entry; 77290c9abc5SDong Aisheng const struct of_device_id *of_id; 77390c9abc5SDong Aisheng const struct mxs_dma_type *dma_type; 774a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma; 775a580b8c5SShawn Guo struct resource *iores; 776a580b8c5SShawn Guo int ret, i; 777a580b8c5SShawn Guo 778aaa20517SShawn Guo mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); 779a580b8c5SShawn Guo if (!mxs_dma) 780a580b8c5SShawn Guo return -ENOMEM; 781a580b8c5SShawn Guo 782d84f638bSShawn Guo ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); 783d84f638bSShawn Guo if (ret) { 784d84f638bSShawn Guo dev_err(&pdev->dev, "failed to read dma-channels\n"); 785d84f638bSShawn Guo return ret; 786d84f638bSShawn Guo } 787d84f638bSShawn Guo 78890c9abc5SDong Aisheng of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev); 78990c9abc5SDong Aisheng if (of_id) 79090c9abc5SDong Aisheng id_entry = of_id->data; 79190c9abc5SDong Aisheng else 79290c9abc5SDong Aisheng id_entry = platform_get_device_id(pdev); 79390c9abc5SDong Aisheng 79490c9abc5SDong Aisheng dma_type = (struct mxs_dma_type *)id_entry->driver_data; 7958c920136SShawn Guo mxs_dma->type = dma_type->type; 79690c9abc5SDong Aisheng mxs_dma->dev_id = dma_type->id; 797a580b8c5SShawn Guo 798a580b8c5SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 799aaa20517SShawn Guo mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); 800aaa20517SShawn Guo if (IS_ERR(mxs_dma->base)) 801aaa20517SShawn Guo return PTR_ERR(mxs_dma->base); 802a580b8c5SShawn Guo 803aaa20517SShawn Guo mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); 804aaa20517SShawn Guo if (IS_ERR(mxs_dma->clk)) 805aaa20517SShawn Guo return PTR_ERR(mxs_dma->clk); 806a580b8c5SShawn Guo 807a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); 808a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); 809a580b8c5SShawn Guo 810a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels); 811a580b8c5SShawn Guo 812a580b8c5SShawn Guo /* Initialize channel parameters */ 813a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) { 814a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; 815a580b8c5SShawn Guo 816a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma; 817a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device; 8188ac69546SRussell King - ARM Linux dma_cookie_init(&mxs_chan->chan); 819a580b8c5SShawn Guo 820a580b8c5SShawn Guo tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, 821a580b8c5SShawn Guo (unsigned long) mxs_chan); 822a580b8c5SShawn Guo 823a580b8c5SShawn Guo 824a580b8c5SShawn Guo /* Add the channel to mxs_chan list */ 825a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node, 826a580b8c5SShawn Guo &mxs_dma->dma_device.channels); 827a580b8c5SShawn Guo } 828a580b8c5SShawn Guo 829a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma); 830a580b8c5SShawn Guo if (ret) 831aaa20517SShawn Guo return ret; 832a580b8c5SShawn Guo 833d84f638bSShawn Guo mxs_dma->pdev = pdev; 834a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev; 835a580b8c5SShawn Guo 836a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */ 837a580b8c5SShawn Guo mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; 838a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 839a580b8c5SShawn Guo 840a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 841a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; 842a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; 843a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; 844a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; 8455c9d2e37SMaxime Ripard mxs_dma->dma_device.device_pause = mxs_dma_pause_chan; 8465c9d2e37SMaxime Ripard mxs_dma->dma_device.device_resume = mxs_dma_resume_chan; 8475c9d2e37SMaxime Ripard mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all; 848ef9d2a92SFabio Estevam mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 849ef9d2a92SFabio Estevam mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 850ef9d2a92SFabio Estevam mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 851ef9d2a92SFabio Estevam mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 8525c9d2e37SMaxime Ripard mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan; 853a580b8c5SShawn Guo 854a580b8c5SShawn Guo ret = dma_async_device_register(&mxs_dma->dma_device); 855a580b8c5SShawn Guo if (ret) { 856a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 857aaa20517SShawn Guo return ret; 858a580b8c5SShawn Guo } 859a580b8c5SShawn Guo 860d84f638bSShawn Guo ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); 861d84f638bSShawn Guo if (ret) { 862d84f638bSShawn Guo dev_err(mxs_dma->dma_device.dev, 863d84f638bSShawn Guo "failed to register controller\n"); 864d84f638bSShawn Guo dma_async_device_unregister(&mxs_dma->dma_device); 865d84f638bSShawn Guo } 866d84f638bSShawn Guo 867a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n"); 868a580b8c5SShawn Guo 869a580b8c5SShawn Guo return 0; 870a580b8c5SShawn Guo } 871a580b8c5SShawn Guo 872a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = { 873a580b8c5SShawn Guo .driver = { 874a580b8c5SShawn Guo .name = "mxs-dma", 87590c9abc5SDong Aisheng .of_match_table = mxs_dma_dt_ids, 876a580b8c5SShawn Guo }, 8778c920136SShawn Guo .id_table = mxs_dma_ids, 878a580b8c5SShawn Guo }; 879a580b8c5SShawn Guo 880a580b8c5SShawn Guo static int __init mxs_dma_module_init(void) 881a580b8c5SShawn Guo { 882a580b8c5SShawn Guo return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); 883a580b8c5SShawn Guo } 884a580b8c5SShawn Guo subsys_initcall(mxs_dma_module_init); 885