1d9617a3fSFabio Estevam // SPDX-License-Identifier: GPL-2.0
2d9617a3fSFabio Estevam //
3d9617a3fSFabio Estevam // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4d9617a3fSFabio Estevam //
5d9617a3fSFabio Estevam // Refer to drivers/dma/imx-sdma.c
6a580b8c5SShawn Guo
7a580b8c5SShawn Guo #include <linux/init.h>
8a580b8c5SShawn Guo #include <linux/types.h>
9a580b8c5SShawn Guo #include <linux/mm.h>
10a580b8c5SShawn Guo #include <linux/interrupt.h>
11a580b8c5SShawn Guo #include <linux/clk.h>
12a580b8c5SShawn Guo #include <linux/wait.h>
13a580b8c5SShawn Guo #include <linux/sched.h>
14a580b8c5SShawn Guo #include <linux/semaphore.h>
15a580b8c5SShawn Guo #include <linux/device.h>
16a580b8c5SShawn Guo #include <linux/dma-mapping.h>
17a580b8c5SShawn Guo #include <linux/slab.h>
18a580b8c5SShawn Guo #include <linux/platform_device.h>
19a580b8c5SShawn Guo #include <linux/dmaengine.h>
20a580b8c5SShawn Guo #include <linux/delay.h>
2190c9abc5SDong Aisheng #include <linux/module.h>
22f5b7efccSDong Aisheng #include <linux/stmp_device.h>
2390c9abc5SDong Aisheng #include <linux/of.h>
24d84f638bSShawn Guo #include <linux/of_dma.h>
25b2d63989SMarkus Pargmann #include <linux/list.h>
26e0ddaab7SSascha Hauer #include <linux/dma/mxs-dma.h>
27a580b8c5SShawn Guo
28a580b8c5SShawn Guo #include <asm/irq.h>
29a580b8c5SShawn Guo
30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h"
31d2ebfb33SRussell King - ARM Linux
32a580b8c5SShawn Guo /*
33a580b8c5SShawn Guo * NOTE: The term "PIO" throughout the mxs-dma implementation means
34a580b8c5SShawn Guo * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
35a580b8c5SShawn Guo * dma can program the controller registers of peripheral devices.
36a580b8c5SShawn Guo */
37a580b8c5SShawn Guo
388c920136SShawn Guo #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
398c920136SShawn Guo #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
40a580b8c5SShawn Guo
41a580b8c5SShawn Guo #define HW_APBHX_CTRL0 0x000
42a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
43a580b8c5SShawn Guo #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
44a580b8c5SShawn Guo #define BP_APBH_CTRL0_RESET_CHANNEL 16
45a580b8c5SShawn Guo #define HW_APBHX_CTRL1 0x010
46a580b8c5SShawn Guo #define HW_APBHX_CTRL2 0x020
47a580b8c5SShawn Guo #define HW_APBHX_CHANNEL_CTRL 0x030
48a580b8c5SShawn Guo #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
49bb11fb63SShawn Guo /*
50bb11fb63SShawn Guo * The offset of NXTCMDAR register is different per both dma type and version,
51bb11fb63SShawn Guo * while stride for each channel is all the same 0x70.
52bb11fb63SShawn Guo */
53bb11fb63SShawn Guo #define HW_APBHX_CHn_NXTCMDAR(d, n) \
54bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
55bb11fb63SShawn Guo #define HW_APBHX_CHn_SEMA(d, n) \
56bb11fb63SShawn Guo (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
577b11304aSMarkus Pargmann #define HW_APBHX_CHn_BAR(d, n) \
587b11304aSMarkus Pargmann (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
59702e94d6SMarkus Pargmann #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
60a580b8c5SShawn Guo
61a580b8c5SShawn Guo /*
62a580b8c5SShawn Guo * ccw bits definitions
63a580b8c5SShawn Guo *
64a580b8c5SShawn Guo * COMMAND: 0..1 (2)
65a580b8c5SShawn Guo * CHAIN: 2 (1)
66a580b8c5SShawn Guo * IRQ: 3 (1)
67a580b8c5SShawn Guo * NAND_LOCK: 4 (1) - not implemented
68a580b8c5SShawn Guo * NAND_WAIT4READY: 5 (1) - not implemented
69a580b8c5SShawn Guo * DEC_SEM: 6 (1)
70a580b8c5SShawn Guo * WAIT4END: 7 (1)
71a580b8c5SShawn Guo * HALT_ON_TERMINATE: 8 (1)
72a580b8c5SShawn Guo * TERMINATE_FLUSH: 9 (1)
73a580b8c5SShawn Guo * RESERVED: 10..11 (2)
74a580b8c5SShawn Guo * PIO_NUM: 12..15 (4)
75a580b8c5SShawn Guo */
76a580b8c5SShawn Guo #define BP_CCW_COMMAND 0
77a580b8c5SShawn Guo #define BM_CCW_COMMAND (3 << 0)
78a580b8c5SShawn Guo #define CCW_CHAIN (1 << 2)
79a580b8c5SShawn Guo #define CCW_IRQ (1 << 3)
80ef347c0cSSascha Hauer #define CCW_WAIT4RDY (1 << 5)
81a580b8c5SShawn Guo #define CCW_DEC_SEM (1 << 6)
82a580b8c5SShawn Guo #define CCW_WAIT4END (1 << 7)
83a580b8c5SShawn Guo #define CCW_HALT_ON_TERM (1 << 8)
84a580b8c5SShawn Guo #define CCW_TERM_FLUSH (1 << 9)
85a580b8c5SShawn Guo #define BP_CCW_PIO_NUM 12
86a580b8c5SShawn Guo #define BM_CCW_PIO_NUM (0xf << 12)
87a580b8c5SShawn Guo
88a580b8c5SShawn Guo #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
89a580b8c5SShawn Guo
90a580b8c5SShawn Guo #define MXS_DMA_CMD_NO_XFER 0
91a580b8c5SShawn Guo #define MXS_DMA_CMD_WRITE 1
92a580b8c5SShawn Guo #define MXS_DMA_CMD_READ 2
93a580b8c5SShawn Guo #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
94a580b8c5SShawn Guo
95a580b8c5SShawn Guo struct mxs_dma_ccw {
96a580b8c5SShawn Guo u32 next;
97a580b8c5SShawn Guo u16 bits;
98a580b8c5SShawn Guo u16 xfer_bytes;
99a580b8c5SShawn Guo #define MAX_XFER_BYTES 0xff00
100a580b8c5SShawn Guo u32 bufaddr;
101a580b8c5SShawn Guo #define MXS_PIO_WORDS 16
102a580b8c5SShawn Guo u32 pio_words[MXS_PIO_WORDS];
103a580b8c5SShawn Guo };
104a580b8c5SShawn Guo
1055e97fa91SMarek Vasut #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
1065e97fa91SMarek Vasut #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
107a580b8c5SShawn Guo
108a580b8c5SShawn Guo struct mxs_dma_chan {
109a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma;
110a580b8c5SShawn Guo struct dma_chan chan;
111a580b8c5SShawn Guo struct dma_async_tx_descriptor desc;
112a580b8c5SShawn Guo struct tasklet_struct tasklet;
113f2ad6992SFabio Estevam unsigned int chan_irq;
114a580b8c5SShawn Guo struct mxs_dma_ccw *ccw;
115a580b8c5SShawn Guo dma_addr_t ccw_phys;
1166d23ea4bSLothar Waßmann int desc_count;
117a580b8c5SShawn Guo enum dma_status status;
118a580b8c5SShawn Guo unsigned int flags;
1192dcbdce3SMarkus Pargmann bool reset;
120a580b8c5SShawn Guo #define MXS_DMA_SG_LOOP (1 << 0)
1212dcbdce3SMarkus Pargmann #define MXS_DMA_USE_SEMAPHORE (1 << 1)
122a580b8c5SShawn Guo };
123a580b8c5SShawn Guo
124a580b8c5SShawn Guo #define MXS_DMA_CHANNELS 16
125a580b8c5SShawn Guo #define MXS_DMA_CHANNELS_MASK 0xffff
126a580b8c5SShawn Guo
1278c920136SShawn Guo enum mxs_dma_devtype {
1288c920136SShawn Guo MXS_DMA_APBH,
1298c920136SShawn Guo MXS_DMA_APBX,
1308c920136SShawn Guo };
1318c920136SShawn Guo
1328c920136SShawn Guo enum mxs_dma_id {
1338c920136SShawn Guo IMX23_DMA,
1348c920136SShawn Guo IMX28_DMA,
1358c920136SShawn Guo };
1368c920136SShawn Guo
137a580b8c5SShawn Guo struct mxs_dma_engine {
1388c920136SShawn Guo enum mxs_dma_id dev_id;
1398c920136SShawn Guo enum mxs_dma_devtype type;
140a580b8c5SShawn Guo void __iomem *base;
141a580b8c5SShawn Guo struct clk *clk;
142a580b8c5SShawn Guo struct dma_device dma_device;
143a580b8c5SShawn Guo struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
144d84f638bSShawn Guo struct platform_device *pdev;
145d84f638bSShawn Guo unsigned int nr_channels;
146a580b8c5SShawn Guo };
147a580b8c5SShawn Guo
1488c920136SShawn Guo struct mxs_dma_type {
1498c920136SShawn Guo enum mxs_dma_id id;
1508c920136SShawn Guo enum mxs_dma_devtype type;
1518c920136SShawn Guo };
1528c920136SShawn Guo
1538c920136SShawn Guo static struct mxs_dma_type mxs_dma_types[] = {
1548c920136SShawn Guo {
1558c920136SShawn Guo .id = IMX23_DMA,
1568c920136SShawn Guo .type = MXS_DMA_APBH,
1578c920136SShawn Guo }, {
1588c920136SShawn Guo .id = IMX23_DMA,
1598c920136SShawn Guo .type = MXS_DMA_APBX,
1608c920136SShawn Guo }, {
1618c920136SShawn Guo .id = IMX28_DMA,
1628c920136SShawn Guo .type = MXS_DMA_APBH,
1638c920136SShawn Guo }, {
1648c920136SShawn Guo .id = IMX28_DMA,
1658c920136SShawn Guo .type = MXS_DMA_APBX,
1668c920136SShawn Guo }
1678c920136SShawn Guo };
1688c920136SShawn Guo
16990c9abc5SDong Aisheng static const struct of_device_id mxs_dma_dt_ids[] = {
170cc2afb0dSFabio Estevam { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_types[0], },
171cc2afb0dSFabio Estevam { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_types[1], },
172cc2afb0dSFabio Estevam { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_types[2], },
173cc2afb0dSFabio Estevam { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_types[3], },
17490c9abc5SDong Aisheng { /* sentinel */ }
17590c9abc5SDong Aisheng };
17690c9abc5SDong Aisheng MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
17790c9abc5SDong Aisheng
to_mxs_dma_chan(struct dma_chan * chan)1788c920136SShawn Guo static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
1798c920136SShawn Guo {
1808c920136SShawn Guo return container_of(chan, struct mxs_dma_chan, chan);
1818c920136SShawn Guo }
1828c920136SShawn Guo
mxs_dma_reset_chan(struct dma_chan * chan)1835c9d2e37SMaxime Ripard static void mxs_dma_reset_chan(struct dma_chan *chan)
184a580b8c5SShawn Guo {
1855c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
186a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
187a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id;
188a580b8c5SShawn Guo
1892dcbdce3SMarkus Pargmann /*
1902dcbdce3SMarkus Pargmann * mxs dma channel resets can cause a channel stall. To recover from a
1912dcbdce3SMarkus Pargmann * channel stall, we have to reset the whole DMA engine. To avoid this,
1922dcbdce3SMarkus Pargmann * we use cyclic DMA with semaphores, that are enhanced in
1932dcbdce3SMarkus Pargmann * mxs_dma_int_handler. To reset the channel, we can simply stop writing
1942dcbdce3SMarkus Pargmann * into the semaphore counter.
1952dcbdce3SMarkus Pargmann */
1962dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
1972dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) {
1982dcbdce3SMarkus Pargmann mxs_chan->reset = true;
1992dcbdce3SMarkus Pargmann } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
200a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
201f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
202702e94d6SMarkus Pargmann } else {
203702e94d6SMarkus Pargmann unsigned long elapsed = 0;
204702e94d6SMarkus Pargmann const unsigned long max_wait = 50000; /* 50ms */
205702e94d6SMarkus Pargmann void __iomem *reg_dbg1 = mxs_dma->base +
206702e94d6SMarkus Pargmann HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
207702e94d6SMarkus Pargmann
208702e94d6SMarkus Pargmann /*
209702e94d6SMarkus Pargmann * On i.MX28 APBX, the DMA channel can stop working if we reset
210702e94d6SMarkus Pargmann * the channel while it is in READ_FLUSH (0x08) state.
211702e94d6SMarkus Pargmann * We wait here until we leave the state. Then we trigger the
212702e94d6SMarkus Pargmann * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
213702e94d6SMarkus Pargmann * because of this.
214702e94d6SMarkus Pargmann */
215702e94d6SMarkus Pargmann while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
216702e94d6SMarkus Pargmann udelay(100);
217702e94d6SMarkus Pargmann elapsed += 100;
218702e94d6SMarkus Pargmann }
219702e94d6SMarkus Pargmann
220702e94d6SMarkus Pargmann if (elapsed >= max_wait)
221702e94d6SMarkus Pargmann dev_err(&mxs_chan->mxs_dma->pdev->dev,
222702e94d6SMarkus Pargmann "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
223702e94d6SMarkus Pargmann chan_id);
224702e94d6SMarkus Pargmann
225a580b8c5SShawn Guo writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
226f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
227a580b8c5SShawn Guo }
228bb3660f1SMarkus Pargmann
229bb3660f1SMarkus Pargmann mxs_chan->status = DMA_COMPLETE;
230702e94d6SMarkus Pargmann }
231a580b8c5SShawn Guo
mxs_dma_enable_chan(struct dma_chan * chan)2325c9d2e37SMaxime Ripard static void mxs_dma_enable_chan(struct dma_chan *chan)
233a580b8c5SShawn Guo {
2345c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
235a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
236a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id;
237a580b8c5SShawn Guo
238a580b8c5SShawn Guo /* set cmd_addr up */
239a580b8c5SShawn Guo writel(mxs_chan->ccw_phys,
240bb11fb63SShawn Guo mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
241a580b8c5SShawn Guo
242a580b8c5SShawn Guo /* write 1 to SEMA to kick off the channel */
2432dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
2442dcbdce3SMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) {
2452dcbdce3SMarkus Pargmann /* A cyclic DMA consists of at least 2 segments, so initialize
2462dcbdce3SMarkus Pargmann * the semaphore with 2 so we have enough time to add 1 to the
2472dcbdce3SMarkus Pargmann * semaphore if we need to */
2482dcbdce3SMarkus Pargmann writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
2492dcbdce3SMarkus Pargmann } else {
250bb11fb63SShawn Guo writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
251a580b8c5SShawn Guo }
2522dcbdce3SMarkus Pargmann mxs_chan->reset = false;
2532dcbdce3SMarkus Pargmann }
254a580b8c5SShawn Guo
mxs_dma_disable_chan(struct dma_chan * chan)2555c9d2e37SMaxime Ripard static void mxs_dma_disable_chan(struct dma_chan *chan)
256a580b8c5SShawn Guo {
2575c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
2585c9d2e37SMaxime Ripard
2592737583eSVinod Koul mxs_chan->status = DMA_COMPLETE;
260a580b8c5SShawn Guo }
261a580b8c5SShawn Guo
mxs_dma_pause_chan(struct dma_chan * chan)262a29c3956SVinod Koul static int mxs_dma_pause_chan(struct dma_chan *chan)
263a580b8c5SShawn Guo {
2645c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
265a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
266a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id;
267a580b8c5SShawn Guo
268a580b8c5SShawn Guo /* freeze the channel */
269bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
270a580b8c5SShawn Guo writel(1 << chan_id,
271f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
272a580b8c5SShawn Guo else
273a580b8c5SShawn Guo writel(1 << chan_id,
274f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
275a580b8c5SShawn Guo
276a580b8c5SShawn Guo mxs_chan->status = DMA_PAUSED;
277a29c3956SVinod Koul return 0;
278a580b8c5SShawn Guo }
279a580b8c5SShawn Guo
mxs_dma_resume_chan(struct dma_chan * chan)280a29c3956SVinod Koul static int mxs_dma_resume_chan(struct dma_chan *chan)
281a580b8c5SShawn Guo {
2825c9d2e37SMaxime Ripard struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
283a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
284a580b8c5SShawn Guo int chan_id = mxs_chan->chan.chan_id;
285a580b8c5SShawn Guo
286a580b8c5SShawn Guo /* unfreeze the channel */
287bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
288a580b8c5SShawn Guo writel(1 << chan_id,
289f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
290a580b8c5SShawn Guo else
291a580b8c5SShawn Guo writel(1 << chan_id,
292f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
293a580b8c5SShawn Guo
294a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS;
295a29c3956SVinod Koul return 0;
296a580b8c5SShawn Guo }
297a580b8c5SShawn Guo
mxs_dma_tx_submit(struct dma_async_tx_descriptor * tx)298a580b8c5SShawn Guo static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
299a580b8c5SShawn Guo {
300884485e1SRussell King - ARM Linux return dma_cookie_assign(tx);
301a580b8c5SShawn Guo }
302a580b8c5SShawn Guo
mxs_dma_tasklet(struct tasklet_struct * t)3036afe8778SAllen Pais static void mxs_dma_tasklet(struct tasklet_struct *t)
304a580b8c5SShawn Guo {
3056afe8778SAllen Pais struct mxs_dma_chan *mxs_chan = from_tasklet(mxs_chan, t, tasklet);
306a580b8c5SShawn Guo
307064370c6SDave Jiang dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL);
308a580b8c5SShawn Guo }
309a580b8c5SShawn Guo
mxs_dma_irq_to_chan(struct mxs_dma_engine * mxs_dma,int irq)310b2d63989SMarkus Pargmann static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
311b2d63989SMarkus Pargmann {
312b2d63989SMarkus Pargmann int i;
313b2d63989SMarkus Pargmann
314b2d63989SMarkus Pargmann for (i = 0; i != mxs_dma->nr_channels; ++i)
315b2d63989SMarkus Pargmann if (mxs_dma->mxs_chans[i].chan_irq == irq)
316b2d63989SMarkus Pargmann return i;
317b2d63989SMarkus Pargmann
318b2d63989SMarkus Pargmann return -EINVAL;
319b2d63989SMarkus Pargmann }
320b2d63989SMarkus Pargmann
mxs_dma_int_handler(int irq,void * dev_id)321a580b8c5SShawn Guo static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
322a580b8c5SShawn Guo {
323a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = dev_id;
324b2d63989SMarkus Pargmann struct mxs_dma_chan *mxs_chan;
325b2d63989SMarkus Pargmann u32 completed;
326b2d63989SMarkus Pargmann u32 err;
327b2d63989SMarkus Pargmann int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
328b2d63989SMarkus Pargmann
329b2d63989SMarkus Pargmann if (chan < 0)
330b2d63989SMarkus Pargmann return IRQ_NONE;
331a580b8c5SShawn Guo
332a580b8c5SShawn Guo /* completion status */
333b2d63989SMarkus Pargmann completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
334b2d63989SMarkus Pargmann completed = (completed >> chan) & 0x1;
335b2d63989SMarkus Pargmann
336b2d63989SMarkus Pargmann /* Clear interrupt */
337b2d63989SMarkus Pargmann writel((1 << chan),
338b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
339a580b8c5SShawn Guo
340a580b8c5SShawn Guo /* error status */
341b2d63989SMarkus Pargmann err = readl(mxs_dma->base + HW_APBHX_CTRL2);
342b2d63989SMarkus Pargmann err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
343b2d63989SMarkus Pargmann
344b2d63989SMarkus Pargmann /*
345b2d63989SMarkus Pargmann * error status bit is in the upper 16 bits, error irq bit in the lower
346b2d63989SMarkus Pargmann * 16 bits. We transform it into a simpler error code:
347b2d63989SMarkus Pargmann * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
348b2d63989SMarkus Pargmann */
349b2d63989SMarkus Pargmann err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
350b2d63989SMarkus Pargmann
351b2d63989SMarkus Pargmann /* Clear error irq */
352b2d63989SMarkus Pargmann writel((1 << chan),
353b2d63989SMarkus Pargmann mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
354a580b8c5SShawn Guo
355a580b8c5SShawn Guo /*
356a580b8c5SShawn Guo * When both completion and error of termination bits set at the
357a580b8c5SShawn Guo * same time, we do not take it as an error. IOW, it only becomes
358b2d63989SMarkus Pargmann * an error we need to handle here in case of either it's a bus
359b2d63989SMarkus Pargmann * error or a termination error with no completion. 0x01 is termination
360b2d63989SMarkus Pargmann * error, so we can subtract err & completed to get the real error case.
361a580b8c5SShawn Guo */
362b2d63989SMarkus Pargmann err -= err & completed;
363a580b8c5SShawn Guo
364b2d63989SMarkus Pargmann mxs_chan = &mxs_dma->mxs_chans[chan];
365a580b8c5SShawn Guo
366b2d63989SMarkus Pargmann if (err) {
367a580b8c5SShawn Guo dev_dbg(mxs_dma->dma_device.dev,
368a580b8c5SShawn Guo "%s: error in channel %d\n", __func__,
369b2d63989SMarkus Pargmann chan);
370a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR;
371e0cad7a0SVinod Koul mxs_dma_reset_chan(&mxs_chan->chan);
372bb3660f1SMarkus Pargmann } else if (mxs_chan->status != DMA_COMPLETE) {
3732dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
374a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS;
3752dcbdce3SMarkus Pargmann if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
3762dcbdce3SMarkus Pargmann writel(1, mxs_dma->base +
3772dcbdce3SMarkus Pargmann HW_APBHX_CHn_SEMA(mxs_dma, chan));
3782dcbdce3SMarkus Pargmann } else {
3792737583eSVinod Koul mxs_chan->status = DMA_COMPLETE;
380a580b8c5SShawn Guo }
3812dcbdce3SMarkus Pargmann }
382a580b8c5SShawn Guo
3832dcbdce3SMarkus Pargmann if (mxs_chan->status == DMA_COMPLETE) {
3842dcbdce3SMarkus Pargmann if (mxs_chan->reset)
3852dcbdce3SMarkus Pargmann return IRQ_HANDLED;
386f7fbce07SRussell King - ARM Linux dma_cookie_complete(&mxs_chan->desc);
3872dcbdce3SMarkus Pargmann }
388a580b8c5SShawn Guo
389a580b8c5SShawn Guo /* schedule tasklet on this channel */
390a580b8c5SShawn Guo tasklet_schedule(&mxs_chan->tasklet);
391a580b8c5SShawn Guo
392a580b8c5SShawn Guo return IRQ_HANDLED;
393a580b8c5SShawn Guo }
394a580b8c5SShawn Guo
mxs_dma_alloc_chan_resources(struct dma_chan * chan)395a580b8c5SShawn Guo static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
396a580b8c5SShawn Guo {
397a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
398a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
399a580b8c5SShawn Guo int ret;
400a580b8c5SShawn Guo
401750afb08SLuis Chamberlain mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
4029f92d223SJoe Perches CCW_BLOCK_SIZE,
4039f92d223SJoe Perches &mxs_chan->ccw_phys, GFP_KERNEL);
404a580b8c5SShawn Guo if (!mxs_chan->ccw) {
405a580b8c5SShawn Guo ret = -ENOMEM;
406a580b8c5SShawn Guo goto err_alloc;
407a580b8c5SShawn Guo }
408a580b8c5SShawn Guo
409a580b8c5SShawn Guo ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
410a580b8c5SShawn Guo 0, "mxs-dma", mxs_dma);
411a580b8c5SShawn Guo if (ret)
412a580b8c5SShawn Guo goto err_irq;
413a580b8c5SShawn Guo
414759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk);
415a580b8c5SShawn Guo if (ret)
416a580b8c5SShawn Guo goto err_clk;
417a580b8c5SShawn Guo
4185c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan);
419a580b8c5SShawn Guo
420a580b8c5SShawn Guo dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
421a580b8c5SShawn Guo mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
422a580b8c5SShawn Guo
423a580b8c5SShawn Guo /* the descriptor is ready */
424a580b8c5SShawn Guo async_tx_ack(&mxs_chan->desc);
425a580b8c5SShawn Guo
426a580b8c5SShawn Guo return 0;
427a580b8c5SShawn Guo
428a580b8c5SShawn Guo err_clk:
429a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma);
430a580b8c5SShawn Guo err_irq:
4315e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
432a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys);
433a580b8c5SShawn Guo err_alloc:
434a580b8c5SShawn Guo return ret;
435a580b8c5SShawn Guo }
436a580b8c5SShawn Guo
mxs_dma_free_chan_resources(struct dma_chan * chan)437a580b8c5SShawn Guo static void mxs_dma_free_chan_resources(struct dma_chan *chan)
438a580b8c5SShawn Guo {
439a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
440a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
441a580b8c5SShawn Guo
4425c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan);
443a580b8c5SShawn Guo
444a580b8c5SShawn Guo free_irq(mxs_chan->chan_irq, mxs_dma);
445a580b8c5SShawn Guo
4465e97fa91SMarek Vasut dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
447a580b8c5SShawn Guo mxs_chan->ccw, mxs_chan->ccw_phys);
448a580b8c5SShawn Guo
449759a2e30SShawn Guo clk_disable_unprepare(mxs_dma->clk);
450a580b8c5SShawn Guo }
451a580b8c5SShawn Guo
452921de864SHuang Shijie /*
453921de864SHuang Shijie * How to use the flags for ->device_prep_slave_sg() :
454921de864SHuang Shijie * [1] If there is only one DMA command in the DMA chain, the code should be:
455921de864SHuang Shijie * ......
456921de864SHuang Shijie * ->device_prep_slave_sg(DMA_CTRL_ACK);
457921de864SHuang Shijie * ......
458921de864SHuang Shijie * [2] If there are two DMA commands in the DMA chain, the code should be
459921de864SHuang Shijie * ......
460921de864SHuang Shijie * ->device_prep_slave_sg(0);
461921de864SHuang Shijie * ......
462d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK);
463921de864SHuang Shijie * ......
464921de864SHuang Shijie * [3] If there are more than two DMA commands in the DMA chain, the code
465921de864SHuang Shijie * should be:
466921de864SHuang Shijie * ......
467921de864SHuang Shijie * ->device_prep_slave_sg(0); // First
468921de864SHuang Shijie * ......
469d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK]);
470921de864SHuang Shijie * ......
471d443cb25SSascha Hauer * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last
472921de864SHuang Shijie * ......
473921de864SHuang Shijie */
mxs_dma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)474a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
475a580b8c5SShawn Guo struct dma_chan *chan, struct scatterlist *sgl,
476db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction,
477623ff773SLinus Torvalds unsigned long flags, void *context)
478a580b8c5SShawn Guo {
479a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
480a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
481a580b8c5SShawn Guo struct mxs_dma_ccw *ccw;
482a580b8c5SShawn Guo struct scatterlist *sg;
483f2ad6992SFabio Estevam u32 i, j;
484a580b8c5SShawn Guo u32 *pio;
485d443cb25SSascha Hauer int idx = 0;
486a580b8c5SShawn Guo
487d443cb25SSascha Hauer if (mxs_chan->status == DMA_IN_PROGRESS)
488d443cb25SSascha Hauer idx = mxs_chan->desc_count;
489a580b8c5SShawn Guo
490d443cb25SSascha Hauer if (sg_len + idx > NUM_CCW) {
491a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev,
492a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n",
493a580b8c5SShawn Guo sg_len, NUM_CCW);
494a580b8c5SShawn Guo goto err_out;
495a580b8c5SShawn Guo }
496a580b8c5SShawn Guo
497a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS;
498a580b8c5SShawn Guo mxs_chan->flags = 0;
499a580b8c5SShawn Guo
500a580b8c5SShawn Guo /*
501a580b8c5SShawn Guo * If the sg is prepared with append flag set, the sg
502a580b8c5SShawn Guo * will be appended to the last prepared sg.
503a580b8c5SShawn Guo */
504d443cb25SSascha Hauer if (idx) {
505a580b8c5SShawn Guo BUG_ON(idx < 1);
506a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx - 1];
507a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
508a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN;
509a580b8c5SShawn Guo ccw->bits &= ~CCW_IRQ;
510a580b8c5SShawn Guo ccw->bits &= ~CCW_DEC_SEM;
511a580b8c5SShawn Guo } else {
512a580b8c5SShawn Guo idx = 0;
513a580b8c5SShawn Guo }
514a580b8c5SShawn Guo
51562268ce9SShawn Guo if (direction == DMA_TRANS_NONE) {
516a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++];
517a580b8c5SShawn Guo pio = (u32 *) sgl;
518a580b8c5SShawn Guo
519a580b8c5SShawn Guo for (j = 0; j < sg_len;)
520a580b8c5SShawn Guo ccw->pio_words[j++] = *pio++;
521a580b8c5SShawn Guo
522a580b8c5SShawn Guo ccw->bits = 0;
523a580b8c5SShawn Guo ccw->bits |= CCW_IRQ;
524a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM;
525ceeeb99cSSascha Hauer if (flags & MXS_DMA_CTRL_WAIT4END)
526a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END;
527a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM;
528a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH;
529a580b8c5SShawn Guo ccw->bits |= BF_CCW(sg_len, PIO_NUM);
530a580b8c5SShawn Guo ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
531ef347c0cSSascha Hauer if (flags & MXS_DMA_CTRL_WAIT4RDY)
532ef347c0cSSascha Hauer ccw->bits |= CCW_WAIT4RDY;
533a580b8c5SShawn Guo } else {
534a580b8c5SShawn Guo for_each_sg(sgl, sg, sg_len, i) {
535fdaf9c4bSLars-Peter Clausen if (sg_dma_len(sg) > MAX_XFER_BYTES) {
536a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
537fdaf9c4bSLars-Peter Clausen sg_dma_len(sg), MAX_XFER_BYTES);
538a580b8c5SShawn Guo goto err_out;
539a580b8c5SShawn Guo }
540a580b8c5SShawn Guo
541a580b8c5SShawn Guo ccw = &mxs_chan->ccw[idx++];
542a580b8c5SShawn Guo
543a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
544a580b8c5SShawn Guo ccw->bufaddr = sg->dma_address;
545fdaf9c4bSLars-Peter Clausen ccw->xfer_bytes = sg_dma_len(sg);
546a580b8c5SShawn Guo
547a580b8c5SShawn Guo ccw->bits = 0;
548a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN;
549a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM;
550a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH;
551db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
552a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
553a580b8c5SShawn Guo COMMAND);
554a580b8c5SShawn Guo
555a580b8c5SShawn Guo if (i + 1 == sg_len) {
556a580b8c5SShawn Guo ccw->bits &= ~CCW_CHAIN;
557a580b8c5SShawn Guo ccw->bits |= CCW_IRQ;
558a580b8c5SShawn Guo ccw->bits |= CCW_DEC_SEM;
559ceeeb99cSSascha Hauer if (flags & MXS_DMA_CTRL_WAIT4END)
560a580b8c5SShawn Guo ccw->bits |= CCW_WAIT4END;
561a580b8c5SShawn Guo }
562a580b8c5SShawn Guo }
563a580b8c5SShawn Guo }
5646d23ea4bSLothar Waßmann mxs_chan->desc_count = idx;
565a580b8c5SShawn Guo
566a580b8c5SShawn Guo return &mxs_chan->desc;
567a580b8c5SShawn Guo
568a580b8c5SShawn Guo err_out:
569a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR;
570a580b8c5SShawn Guo return NULL;
571a580b8c5SShawn Guo }
572a580b8c5SShawn Guo
mxs_dma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)573a580b8c5SShawn Guo static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
574a580b8c5SShawn Guo struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
575185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction,
57631c1e5a1SLaurent Pinchart unsigned long flags)
577a580b8c5SShawn Guo {
578a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
579a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
580f2ad6992SFabio Estevam u32 num_periods = buf_len / period_len;
581f2ad6992SFabio Estevam u32 i = 0, buf = 0;
582a580b8c5SShawn Guo
583a580b8c5SShawn Guo if (mxs_chan->status == DMA_IN_PROGRESS)
584a580b8c5SShawn Guo return NULL;
585a580b8c5SShawn Guo
586a580b8c5SShawn Guo mxs_chan->status = DMA_IN_PROGRESS;
587a580b8c5SShawn Guo mxs_chan->flags |= MXS_DMA_SG_LOOP;
5882dcbdce3SMarkus Pargmann mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
589a580b8c5SShawn Guo
590a580b8c5SShawn Guo if (num_periods > NUM_CCW) {
591a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev,
592a580b8c5SShawn Guo "maximum number of sg exceeded: %d > %d\n",
593a580b8c5SShawn Guo num_periods, NUM_CCW);
594a580b8c5SShawn Guo goto err_out;
595a580b8c5SShawn Guo }
596a580b8c5SShawn Guo
597a580b8c5SShawn Guo if (period_len > MAX_XFER_BYTES) {
598a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev,
5994aff2f93SFabio Estevam "maximum period size exceeded: %zu > %d\n",
600a580b8c5SShawn Guo period_len, MAX_XFER_BYTES);
601a580b8c5SShawn Guo goto err_out;
602a580b8c5SShawn Guo }
603a580b8c5SShawn Guo
604a580b8c5SShawn Guo while (buf < buf_len) {
605a580b8c5SShawn Guo struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
606a580b8c5SShawn Guo
607a580b8c5SShawn Guo if (i + 1 == num_periods)
608a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys;
609a580b8c5SShawn Guo else
610a580b8c5SShawn Guo ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
611a580b8c5SShawn Guo
612a580b8c5SShawn Guo ccw->bufaddr = dma_addr;
613a580b8c5SShawn Guo ccw->xfer_bytes = period_len;
614a580b8c5SShawn Guo
615a580b8c5SShawn Guo ccw->bits = 0;
616a580b8c5SShawn Guo ccw->bits |= CCW_CHAIN;
617a580b8c5SShawn Guo ccw->bits |= CCW_IRQ;
618a580b8c5SShawn Guo ccw->bits |= CCW_HALT_ON_TERM;
619a580b8c5SShawn Guo ccw->bits |= CCW_TERM_FLUSH;
6202dcbdce3SMarkus Pargmann ccw->bits |= CCW_DEC_SEM;
621db8196dfSVinod Koul ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
622a580b8c5SShawn Guo MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
623a580b8c5SShawn Guo
624a580b8c5SShawn Guo dma_addr += period_len;
625a580b8c5SShawn Guo buf += period_len;
626a580b8c5SShawn Guo
627a580b8c5SShawn Guo i++;
628a580b8c5SShawn Guo }
6296d23ea4bSLothar Waßmann mxs_chan->desc_count = i;
630a580b8c5SShawn Guo
631a580b8c5SShawn Guo return &mxs_chan->desc;
632a580b8c5SShawn Guo
633a580b8c5SShawn Guo err_out:
634a580b8c5SShawn Guo mxs_chan->status = DMA_ERROR;
635a580b8c5SShawn Guo return NULL;
636a580b8c5SShawn Guo }
637a580b8c5SShawn Guo
mxs_dma_terminate_all(struct dma_chan * chan)6385c9d2e37SMaxime Ripard static int mxs_dma_terminate_all(struct dma_chan *chan)
639a580b8c5SShawn Guo {
6405c9d2e37SMaxime Ripard mxs_dma_reset_chan(chan);
6415c9d2e37SMaxime Ripard mxs_dma_disable_chan(chan);
642a580b8c5SShawn Guo
6435c9d2e37SMaxime Ripard return 0;
644a580b8c5SShawn Guo }
645a580b8c5SShawn Guo
mxs_dma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)646a580b8c5SShawn Guo static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
647a580b8c5SShawn Guo dma_cookie_t cookie, struct dma_tx_state *txstate)
648a580b8c5SShawn Guo {
649a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
6507b11304aSMarkus Pargmann struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
6517b11304aSMarkus Pargmann u32 residue = 0;
652a580b8c5SShawn Guo
6537b11304aSMarkus Pargmann if (mxs_chan->status == DMA_IN_PROGRESS &&
6547b11304aSMarkus Pargmann mxs_chan->flags & MXS_DMA_SG_LOOP) {
6557b11304aSMarkus Pargmann struct mxs_dma_ccw *last_ccw;
6567b11304aSMarkus Pargmann u32 bar;
6577b11304aSMarkus Pargmann
6587b11304aSMarkus Pargmann last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
6597b11304aSMarkus Pargmann residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
6607b11304aSMarkus Pargmann
6617b11304aSMarkus Pargmann bar = readl(mxs_dma->base +
6627b11304aSMarkus Pargmann HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
6637b11304aSMarkus Pargmann residue -= bar;
6647b11304aSMarkus Pargmann }
6657b11304aSMarkus Pargmann
6667b11304aSMarkus Pargmann dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
6677b11304aSMarkus Pargmann residue);
668a580b8c5SShawn Guo
669a580b8c5SShawn Guo return mxs_chan->status;
670a580b8c5SShawn Guo }
671a580b8c5SShawn Guo
mxs_dma_init(struct mxs_dma_engine * mxs_dma)67226696d46SDario Binacchi static int mxs_dma_init(struct mxs_dma_engine *mxs_dma)
673a580b8c5SShawn Guo {
674a580b8c5SShawn Guo int ret;
675a580b8c5SShawn Guo
676759a2e30SShawn Guo ret = clk_prepare_enable(mxs_dma->clk);
677a580b8c5SShawn Guo if (ret)
678feb397deSLothar Waßmann return ret;
679a580b8c5SShawn Guo
680f5b7efccSDong Aisheng ret = stmp_reset_block(mxs_dma->base);
681a580b8c5SShawn Guo if (ret)
682a580b8c5SShawn Guo goto err_out;
683a580b8c5SShawn Guo
684a580b8c5SShawn Guo /* enable apbh burst */
685bb11fb63SShawn Guo if (dma_is_apbh(mxs_dma)) {
686a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST_EN,
687f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
688a580b8c5SShawn Guo writel(BM_APBH_CTRL0_APB_BURST8_EN,
689f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
690a580b8c5SShawn Guo }
691a580b8c5SShawn Guo
692a580b8c5SShawn Guo /* enable irq for all the channels */
693a580b8c5SShawn Guo writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
694f5b7efccSDong Aisheng mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
695a580b8c5SShawn Guo
696a580b8c5SShawn Guo err_out:
69757f2685cSLinus Torvalds clk_disable_unprepare(mxs_dma->clk);
698a580b8c5SShawn Guo return ret;
699a580b8c5SShawn Guo }
700a580b8c5SShawn Guo
701d84f638bSShawn Guo struct mxs_dma_filter_param {
702d84f638bSShawn Guo unsigned int chan_id;
703d84f638bSShawn Guo };
704d84f638bSShawn Guo
mxs_dma_filter_fn(struct dma_chan * chan,void * fn_param)705d84f638bSShawn Guo static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
706d84f638bSShawn Guo {
707d84f638bSShawn Guo struct mxs_dma_filter_param *param = fn_param;
708d84f638bSShawn Guo struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
709d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
710d84f638bSShawn Guo int chan_irq;
711d84f638bSShawn Guo
712d84f638bSShawn Guo if (chan->chan_id != param->chan_id)
713d84f638bSShawn Guo return false;
714d84f638bSShawn Guo
715d84f638bSShawn Guo chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
716d84f638bSShawn Guo if (chan_irq < 0)
717d84f638bSShawn Guo return false;
718d84f638bSShawn Guo
719d84f638bSShawn Guo mxs_chan->chan_irq = chan_irq;
720d84f638bSShawn Guo
721d84f638bSShawn Guo return true;
722d84f638bSShawn Guo }
723d84f638bSShawn Guo
mxs_dma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)7243208b370SFabio Estevam static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
725d84f638bSShawn Guo struct of_dma *ofdma)
726d84f638bSShawn Guo {
727d84f638bSShawn Guo struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
728d84f638bSShawn Guo dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
729d84f638bSShawn Guo struct mxs_dma_filter_param param;
730d84f638bSShawn Guo
731d84f638bSShawn Guo if (dma_spec->args_count != 1)
732d84f638bSShawn Guo return NULL;
733d84f638bSShawn Guo
734d84f638bSShawn Guo param.chan_id = dma_spec->args[0];
735d84f638bSShawn Guo
736d84f638bSShawn Guo if (param.chan_id >= mxs_dma->nr_channels)
737d84f638bSShawn Guo return NULL;
738d84f638bSShawn Guo
739caf5e3e6SBaolin Wang return __dma_request_channel(&mask, mxs_dma_filter_fn, ¶m,
740caf5e3e6SBaolin Wang ofdma->of_node);
741d84f638bSShawn Guo }
742d84f638bSShawn Guo
mxs_dma_probe(struct platform_device * pdev)74326696d46SDario Binacchi static int mxs_dma_probe(struct platform_device *pdev)
744a580b8c5SShawn Guo {
745d84f638bSShawn Guo struct device_node *np = pdev->dev.of_node;
74690c9abc5SDong Aisheng const struct mxs_dma_type *dma_type;
747a580b8c5SShawn Guo struct mxs_dma_engine *mxs_dma;
748a580b8c5SShawn Guo int ret, i;
749a580b8c5SShawn Guo
750aaa20517SShawn Guo mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
751a580b8c5SShawn Guo if (!mxs_dma)
752a580b8c5SShawn Guo return -ENOMEM;
753a580b8c5SShawn Guo
754d84f638bSShawn Guo ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
755d84f638bSShawn Guo if (ret) {
756d84f638bSShawn Guo dev_err(&pdev->dev, "failed to read dma-channels\n");
757d84f638bSShawn Guo return ret;
758d84f638bSShawn Guo }
759d84f638bSShawn Guo
760cc2afb0dSFabio Estevam dma_type = (struct mxs_dma_type *)of_device_get_match_data(&pdev->dev);
7618c920136SShawn Guo mxs_dma->type = dma_type->type;
76290c9abc5SDong Aisheng mxs_dma->dev_id = dma_type->id;
763a580b8c5SShawn Guo
764*4b23603aSTudor Ambarus mxs_dma->base = devm_platform_ioremap_resource(pdev, 0);
765aaa20517SShawn Guo if (IS_ERR(mxs_dma->base))
766aaa20517SShawn Guo return PTR_ERR(mxs_dma->base);
767a580b8c5SShawn Guo
768aaa20517SShawn Guo mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
769aaa20517SShawn Guo if (IS_ERR(mxs_dma->clk))
770aaa20517SShawn Guo return PTR_ERR(mxs_dma->clk);
771a580b8c5SShawn Guo
772a580b8c5SShawn Guo dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
773a580b8c5SShawn Guo dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
774a580b8c5SShawn Guo
775a580b8c5SShawn Guo INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
776a580b8c5SShawn Guo
777a580b8c5SShawn Guo /* Initialize channel parameters */
778a580b8c5SShawn Guo for (i = 0; i < MXS_DMA_CHANNELS; i++) {
779a580b8c5SShawn Guo struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
780a580b8c5SShawn Guo
781a580b8c5SShawn Guo mxs_chan->mxs_dma = mxs_dma;
782a580b8c5SShawn Guo mxs_chan->chan.device = &mxs_dma->dma_device;
7838ac69546SRussell King - ARM Linux dma_cookie_init(&mxs_chan->chan);
784a580b8c5SShawn Guo
7856afe8778SAllen Pais tasklet_setup(&mxs_chan->tasklet, mxs_dma_tasklet);
786a580b8c5SShawn Guo
787a580b8c5SShawn Guo
788a580b8c5SShawn Guo /* Add the channel to mxs_chan list */
789a580b8c5SShawn Guo list_add_tail(&mxs_chan->chan.device_node,
790a580b8c5SShawn Guo &mxs_dma->dma_device.channels);
791a580b8c5SShawn Guo }
792a580b8c5SShawn Guo
793a580b8c5SShawn Guo ret = mxs_dma_init(mxs_dma);
794a580b8c5SShawn Guo if (ret)
795aaa20517SShawn Guo return ret;
796a580b8c5SShawn Guo
797d84f638bSShawn Guo mxs_dma->pdev = pdev;
798a580b8c5SShawn Guo mxs_dma->dma_device.dev = &pdev->dev;
799a580b8c5SShawn Guo
800a580b8c5SShawn Guo /* mxs_dma gets 65535 bytes maximum sg size */
801a580b8c5SShawn Guo dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
802a580b8c5SShawn Guo
803a580b8c5SShawn Guo mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
804a580b8c5SShawn Guo mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
805a580b8c5SShawn Guo mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
806a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
807a580b8c5SShawn Guo mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
8085c9d2e37SMaxime Ripard mxs_dma->dma_device.device_pause = mxs_dma_pause_chan;
8095c9d2e37SMaxime Ripard mxs_dma->dma_device.device_resume = mxs_dma_resume_chan;
8105c9d2e37SMaxime Ripard mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all;
811ef9d2a92SFabio Estevam mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
812ef9d2a92SFabio Estevam mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
813ef9d2a92SFabio Estevam mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
814ef9d2a92SFabio Estevam mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
8155c9d2e37SMaxime Ripard mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan;
816a580b8c5SShawn Guo
817fbb69eceSHuang Shijie ret = dmaenginem_async_device_register(&mxs_dma->dma_device);
818a580b8c5SShawn Guo if (ret) {
819a580b8c5SShawn Guo dev_err(mxs_dma->dma_device.dev, "unable to register\n");
820aaa20517SShawn Guo return ret;
821a580b8c5SShawn Guo }
822a580b8c5SShawn Guo
823d84f638bSShawn Guo ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
824d84f638bSShawn Guo if (ret) {
825d84f638bSShawn Guo dev_err(mxs_dma->dma_device.dev,
826d84f638bSShawn Guo "failed to register controller\n");
827d84f638bSShawn Guo }
828d84f638bSShawn Guo
829a580b8c5SShawn Guo dev_info(mxs_dma->dma_device.dev, "initialized\n");
830a580b8c5SShawn Guo
831a580b8c5SShawn Guo return 0;
832a580b8c5SShawn Guo }
833a580b8c5SShawn Guo
834a580b8c5SShawn Guo static struct platform_driver mxs_dma_driver = {
835a580b8c5SShawn Guo .driver = {
836a580b8c5SShawn Guo .name = "mxs-dma",
83790c9abc5SDong Aisheng .of_match_table = mxs_dma_dt_ids,
838a580b8c5SShawn Guo },
83926696d46SDario Binacchi .probe = mxs_dma_probe,
840a580b8c5SShawn Guo };
841a580b8c5SShawn Guo
84226696d46SDario Binacchi builtin_platform_driver(mxs_dma_driver);
843