1 /* 2 * Copyright (C) 2007, 2008, Marvell International Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 * for more details. 12 */ 13 14 #ifndef MV_XOR_H 15 #define MV_XOR_H 16 17 #include <linux/types.h> 18 #include <linux/io.h> 19 #include <linux/dmaengine.h> 20 #include <linux/interrupt.h> 21 22 #define MV_XOR_POOL_SIZE (MV_XOR_SLOT_SIZE * 3072) 23 #define MV_XOR_SLOT_SIZE 64 24 #define MV_XOR_THRESHOLD 1 25 #define MV_XOR_MAX_CHANNELS 2 26 27 #define MV_XOR_MIN_BYTE_COUNT SZ_128 28 #define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1) 29 30 /* Values for the XOR_CONFIG register */ 31 #define XOR_OPERATION_MODE_XOR 0 32 #define XOR_OPERATION_MODE_MEMCPY 2 33 #define XOR_OPERATION_MODE_IN_DESC 7 34 #define XOR_DESCRIPTOR_SWAP BIT(14) 35 #define XOR_DESC_SUCCESS 0x40000000 36 37 #define XOR_DESC_OPERATION_XOR (0 << 24) 38 #define XOR_DESC_OPERATION_CRC32C (1 << 24) 39 #define XOR_DESC_OPERATION_MEMCPY (2 << 24) 40 41 #define XOR_DESC_DMA_OWNED BIT(31) 42 #define XOR_DESC_EOD_INT_EN BIT(31) 43 44 #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) 45 #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) 46 #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) 47 #define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4)) 48 #define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4)) 49 #define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0) 50 #define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4) 51 52 #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4)) 53 #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4)) 54 #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30) 55 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) 56 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) 57 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) 58 59 #define XOR_INT_END_OF_DESC BIT(0) 60 #define XOR_INT_END_OF_CHAIN BIT(1) 61 #define XOR_INT_STOPPED BIT(2) 62 #define XOR_INT_PAUSED BIT(3) 63 #define XOR_INT_ERR_DECODE BIT(4) 64 #define XOR_INT_ERR_RDPROT BIT(5) 65 #define XOR_INT_ERR_WRPROT BIT(6) 66 #define XOR_INT_ERR_OWN BIT(7) 67 #define XOR_INT_ERR_PAR BIT(8) 68 #define XOR_INT_ERR_MBUS BIT(9) 69 70 #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \ 71 XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \ 72 XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS) 73 74 #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \ 75 XOR_INT_STOPPED | XOR_INTR_ERRORS) 76 77 #define WINDOW_BASE(w) (0x50 + ((w) << 2)) 78 #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) 79 #define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2)) 80 #define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2)) 81 #define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2)) 82 83 struct mv_xor_device { 84 void __iomem *xor_base; 85 void __iomem *xor_high_base; 86 struct clk *clk; 87 struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS]; 88 int xor_type; 89 }; 90 91 /** 92 * struct mv_xor_chan - internal representation of a XOR channel 93 * @pending: allows batching of hardware operations 94 * @lock: serializes enqueue/dequeue operations to the descriptors pool 95 * @mmr_base: memory mapped register base 96 * @idx: the index of the xor channel 97 * @chain: device chain view of the descriptors 98 * @free_slots: free slots usable by the channel 99 * @allocated_slots: slots allocated by the driver 100 * @completed_slots: slots completed by HW but still need to be acked 101 * @device: parent device 102 * @common: common dmaengine channel object members 103 * @slots_allocated: records the actual size of the descriptor slot pool 104 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs 105 * @op_in_desc: new mode of driver, each op is writen to descriptor. 106 */ 107 struct mv_xor_chan { 108 int pending; 109 spinlock_t lock; /* protects the descriptor slot pool */ 110 void __iomem *mmr_base; 111 void __iomem *mmr_high_base; 112 unsigned int idx; 113 int irq; 114 struct list_head chain; 115 struct list_head free_slots; 116 struct list_head allocated_slots; 117 struct list_head completed_slots; 118 dma_addr_t dma_desc_pool; 119 void *dma_desc_pool_virt; 120 size_t pool_size; 121 struct dma_device dmadev; 122 struct dma_chan dmachan; 123 int slots_allocated; 124 struct tasklet_struct irq_tasklet; 125 int op_in_desc; 126 char dummy_src[MV_XOR_MIN_BYTE_COUNT]; 127 char dummy_dst[MV_XOR_MIN_BYTE_COUNT]; 128 dma_addr_t dummy_src_addr, dummy_dst_addr; 129 u32 saved_config_reg, saved_int_mask_reg; 130 }; 131 132 /** 133 * struct mv_xor_desc_slot - software descriptor 134 * @node: node on the mv_xor_chan lists 135 * @hw_desc: virtual address of the hardware descriptor chain 136 * @phys: hardware address of the hardware descriptor chain 137 * @slot_used: slot in use or not 138 * @idx: pool index 139 * @tx_list: list of slots that make up a multi-descriptor transaction 140 * @async_tx: support for the async_tx api 141 */ 142 struct mv_xor_desc_slot { 143 struct list_head node; 144 enum dma_transaction_type type; 145 void *hw_desc; 146 u16 idx; 147 struct dma_async_tx_descriptor async_tx; 148 }; 149 150 /* 151 * This structure describes XOR descriptor size 64bytes. The 152 * mv_phy_src_idx() macro must be used when indexing the values of the 153 * phy_src_addr[] array. This is due to the fact that the 'descriptor 154 * swap' feature, used on big endian systems, swaps descriptors data 155 * within blocks of 8 bytes. So two consecutive values of the 156 * phy_src_addr[] array are actually swapped in big-endian, which 157 * explains the different mv_phy_src_idx() implementation. 158 */ 159 #if defined(__LITTLE_ENDIAN) 160 struct mv_xor_desc { 161 u32 status; /* descriptor execution status */ 162 u32 crc32_result; /* result of CRC-32 calculation */ 163 u32 desc_command; /* type of operation to be carried out */ 164 u32 phy_next_desc; /* next descriptor address pointer */ 165 u32 byte_count; /* size of src/dst blocks in bytes */ 166 u32 phy_dest_addr; /* destination block address */ 167 u32 phy_src_addr[8]; /* source block addresses */ 168 u32 reserved0; 169 u32 reserved1; 170 }; 171 #define mv_phy_src_idx(src_idx) (src_idx) 172 #else 173 struct mv_xor_desc { 174 u32 crc32_result; /* result of CRC-32 calculation */ 175 u32 status; /* descriptor execution status */ 176 u32 phy_next_desc; /* next descriptor address pointer */ 177 u32 desc_command; /* type of operation to be carried out */ 178 u32 phy_dest_addr; /* destination block address */ 179 u32 byte_count; /* size of src/dst blocks in bytes */ 180 u32 phy_src_addr[8]; /* source block addresses */ 181 u32 reserved1; 182 u32 reserved0; 183 }; 184 #define mv_phy_src_idx(src_idx) (src_idx ^ 1) 185 #endif 186 187 #define to_mv_sw_desc(addr_hw_desc) \ 188 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc) 189 190 #define mv_hw_desc_slot_idx(hw_desc, idx) \ 191 ((void *)(((unsigned long)hw_desc) + ((idx) << 5))) 192 193 #endif 194