1 /* 2 * Copyright (C) 2007, 2008, Marvell International Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 * for more details. 12 */ 13 14 #ifndef MV_XOR_H 15 #define MV_XOR_H 16 17 #include <linux/types.h> 18 #include <linux/io.h> 19 #include <linux/dmaengine.h> 20 #include <linux/interrupt.h> 21 22 #define MV_XOR_POOL_SIZE PAGE_SIZE 23 #define MV_XOR_SLOT_SIZE 64 24 #define MV_XOR_THRESHOLD 1 25 #define MV_XOR_MAX_CHANNELS 2 26 27 #define MV_XOR_MIN_BYTE_COUNT SZ_128 28 #define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1) 29 30 /* Values for the XOR_CONFIG register */ 31 #define XOR_OPERATION_MODE_XOR 0 32 #define XOR_OPERATION_MODE_MEMCPY 2 33 #define XOR_DESCRIPTOR_SWAP BIT(14) 34 35 #define XOR_DESC_DMA_OWNED BIT(31) 36 #define XOR_DESC_EOD_INT_EN BIT(31) 37 38 #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) 39 #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) 40 #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) 41 #define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4)) 42 #define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4)) 43 #define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0) 44 #define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4) 45 46 #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4)) 47 #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4)) 48 #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30) 49 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) 50 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) 51 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) 52 53 #define XOR_INT_END_OF_DESC BIT(0) 54 #define XOR_INT_END_OF_CHAIN BIT(1) 55 #define XOR_INT_STOPPED BIT(2) 56 #define XOR_INT_PAUSED BIT(3) 57 #define XOR_INT_ERR_DECODE BIT(4) 58 #define XOR_INT_ERR_RDPROT BIT(5) 59 #define XOR_INT_ERR_WRPROT BIT(6) 60 #define XOR_INT_ERR_OWN BIT(7) 61 #define XOR_INT_ERR_PAR BIT(8) 62 #define XOR_INT_ERR_MBUS BIT(9) 63 64 #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \ 65 XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \ 66 XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS) 67 68 #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \ 69 XOR_INT_STOPPED | XOR_INTR_ERRORS) 70 71 #define WINDOW_BASE(w) (0x50 + ((w) << 2)) 72 #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) 73 #define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2)) 74 #define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2)) 75 #define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2)) 76 77 struct mv_xor_device { 78 void __iomem *xor_base; 79 void __iomem *xor_high_base; 80 struct clk *clk; 81 struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS]; 82 }; 83 84 /** 85 * struct mv_xor_chan - internal representation of a XOR channel 86 * @pending: allows batching of hardware operations 87 * @lock: serializes enqueue/dequeue operations to the descriptors pool 88 * @mmr_base: memory mapped register base 89 * @idx: the index of the xor channel 90 * @chain: device chain view of the descriptors 91 * @completed_slots: slots completed by HW but still need to be acked 92 * @device: parent device 93 * @common: common dmaengine channel object members 94 * @last_used: place holder for allocation to continue from where it left off 95 * @all_slots: complete domain of slots usable by the channel 96 * @slots_allocated: records the actual size of the descriptor slot pool 97 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs 98 */ 99 struct mv_xor_chan { 100 int pending; 101 spinlock_t lock; /* protects the descriptor slot pool */ 102 void __iomem *mmr_base; 103 void __iomem *mmr_high_base; 104 unsigned int idx; 105 int irq; 106 enum dma_transaction_type current_type; 107 struct list_head chain; 108 struct list_head completed_slots; 109 dma_addr_t dma_desc_pool; 110 void *dma_desc_pool_virt; 111 size_t pool_size; 112 struct dma_device dmadev; 113 struct dma_chan dmachan; 114 struct mv_xor_desc_slot *last_used; 115 struct list_head all_slots; 116 int slots_allocated; 117 struct tasklet_struct irq_tasklet; 118 char dummy_src[MV_XOR_MIN_BYTE_COUNT]; 119 char dummy_dst[MV_XOR_MIN_BYTE_COUNT]; 120 dma_addr_t dummy_src_addr, dummy_dst_addr; 121 }; 122 123 /** 124 * struct mv_xor_desc_slot - software descriptor 125 * @slot_node: node on the mv_xor_chan.all_slots list 126 * @chain_node: node on the mv_xor_chan.chain list 127 * @completed_node: node on the mv_xor_chan.completed_slots list 128 * @hw_desc: virtual address of the hardware descriptor chain 129 * @phys: hardware address of the hardware descriptor chain 130 * @slot_used: slot in use or not 131 * @idx: pool index 132 * @tx_list: list of slots that make up a multi-descriptor transaction 133 * @async_tx: support for the async_tx api 134 */ 135 struct mv_xor_desc_slot { 136 struct list_head slot_node; 137 struct list_head chain_node; 138 struct list_head completed_node; 139 enum dma_transaction_type type; 140 void *hw_desc; 141 u16 slot_used; 142 u16 idx; 143 struct dma_async_tx_descriptor async_tx; 144 }; 145 146 /* 147 * This structure describes XOR descriptor size 64bytes. The 148 * mv_phy_src_idx() macro must be used when indexing the values of the 149 * phy_src_addr[] array. This is due to the fact that the 'descriptor 150 * swap' feature, used on big endian systems, swaps descriptors data 151 * within blocks of 8 bytes. So two consecutive values of the 152 * phy_src_addr[] array are actually swapped in big-endian, which 153 * explains the different mv_phy_src_idx() implementation. 154 */ 155 #if defined(__LITTLE_ENDIAN) 156 struct mv_xor_desc { 157 u32 status; /* descriptor execution status */ 158 u32 crc32_result; /* result of CRC-32 calculation */ 159 u32 desc_command; /* type of operation to be carried out */ 160 u32 phy_next_desc; /* next descriptor address pointer */ 161 u32 byte_count; /* size of src/dst blocks in bytes */ 162 u32 phy_dest_addr; /* destination block address */ 163 u32 phy_src_addr[8]; /* source block addresses */ 164 u32 reserved0; 165 u32 reserved1; 166 }; 167 #define mv_phy_src_idx(src_idx) (src_idx) 168 #else 169 struct mv_xor_desc { 170 u32 crc32_result; /* result of CRC-32 calculation */ 171 u32 status; /* descriptor execution status */ 172 u32 phy_next_desc; /* next descriptor address pointer */ 173 u32 desc_command; /* type of operation to be carried out */ 174 u32 phy_dest_addr; /* destination block address */ 175 u32 byte_count; /* size of src/dst blocks in bytes */ 176 u32 phy_src_addr[8]; /* source block addresses */ 177 u32 reserved1; 178 u32 reserved0; 179 }; 180 #define mv_phy_src_idx(src_idx) (src_idx ^ 1) 181 #endif 182 183 #define to_mv_sw_desc(addr_hw_desc) \ 184 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc) 185 186 #define mv_hw_desc_slot_idx(hw_desc, idx) \ 187 ((void *)(((unsigned long)hw_desc) + ((idx) << 5))) 188 189 #endif 190