10fb6f739SPiotr Ziecik /* 20fb6f739SPiotr Ziecik * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008. 30fb6f739SPiotr Ziecik * Copyright (C) Semihalf 2009 4ba2eea25SIlya Yanok * Copyright (C) Ilya Yanok, Emcraft Systems 2010 563da8e0dSAlexander Popov * Copyright (C) Alexander Popov, Promcontroller 2014 6899ed9ddSMario Six * Copyright (C) Mario Six, Guntermann & Drunck GmbH, 2016 70fb6f739SPiotr Ziecik * 80fb6f739SPiotr Ziecik * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description 90fb6f739SPiotr Ziecik * (defines, structures and comments) was taken from MPC5121 DMA driver 100fb6f739SPiotr Ziecik * written by Hongjun Chen <hong-jun.chen@freescale.com>. 110fb6f739SPiotr Ziecik * 120fb6f739SPiotr Ziecik * Approved as OSADL project by a majority of OSADL members and funded 130fb6f739SPiotr Ziecik * by OSADL membership fees in 2009; for details see www.osadl.org. 140fb6f739SPiotr Ziecik * 150fb6f739SPiotr Ziecik * This program is free software; you can redistribute it and/or modify it 160fb6f739SPiotr Ziecik * under the terms of the GNU General Public License as published by the Free 170fb6f739SPiotr Ziecik * Software Foundation; either version 2 of the License, or (at your option) 180fb6f739SPiotr Ziecik * any later version. 190fb6f739SPiotr Ziecik * 200fb6f739SPiotr Ziecik * This program is distributed in the hope that it will be useful, but WITHOUT 210fb6f739SPiotr Ziecik * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 220fb6f739SPiotr Ziecik * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 230fb6f739SPiotr Ziecik * more details. 240fb6f739SPiotr Ziecik * 250fb6f739SPiotr Ziecik * The full GNU General Public License is included in this distribution in the 260fb6f739SPiotr Ziecik * file called COPYING. 270fb6f739SPiotr Ziecik */ 280fb6f739SPiotr Ziecik 290fb6f739SPiotr Ziecik /* 30899ed9ddSMario Six * MPC512x and MPC8308 DMA driver. It supports memory to memory data transfers 31899ed9ddSMario Six * (tested using dmatest module) and data transfers between memory and 32899ed9ddSMario Six * peripheral I/O memory by means of slave scatter/gather with these 33899ed9ddSMario Six * limitations: 34899ed9ddSMario Six * - chunked transfers (described by s/g lists with more than one item) are 35899ed9ddSMario Six * refused as long as proper support for scatter/gather is missing 36899ed9ddSMario Six * - transfers on MPC8308 always start from software as this SoC does not have 37899ed9ddSMario Six * external request lines for peripheral flow control 38899ed9ddSMario Six * - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for 39899ed9ddSMario Six * MPC512x), and 32 bytes are supported, and, consequently, source 40899ed9ddSMario Six * addresses and destination addresses must be aligned accordingly; 41899ed9ddSMario Six * furthermore, for MPC512x SoCs, the transfer size must be aligned on 42899ed9ddSMario Six * (chunk size * maxburst) 430fb6f739SPiotr Ziecik */ 440fb6f739SPiotr Ziecik 450fb6f739SPiotr Ziecik #include <linux/module.h> 460fb6f739SPiotr Ziecik #include <linux/dmaengine.h> 470fb6f739SPiotr Ziecik #include <linux/dma-mapping.h> 480fb6f739SPiotr Ziecik #include <linux/interrupt.h> 490fb6f739SPiotr Ziecik #include <linux/io.h> 505a0e3ad6STejun Heo #include <linux/slab.h> 515af50730SRob Herring #include <linux/of_address.h> 520fb6f739SPiotr Ziecik #include <linux/of_device.h> 535af50730SRob Herring #include <linux/of_irq.h> 54ec1f0c96SAlexander Popov #include <linux/of_dma.h> 550fb6f739SPiotr Ziecik #include <linux/of_platform.h> 560fb6f739SPiotr Ziecik 570fb6f739SPiotr Ziecik #include <linux/random.h> 580fb6f739SPiotr Ziecik 59d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 60d2ebfb33SRussell King - ARM Linux 610fb6f739SPiotr Ziecik /* Number of DMA Transfer descriptors allocated per channel */ 620fb6f739SPiotr Ziecik #define MPC_DMA_DESCRIPTORS 64 630fb6f739SPiotr Ziecik 640fb6f739SPiotr Ziecik /* Macro definitions */ 650fb6f739SPiotr Ziecik #define MPC_DMA_TCD_OFFSET 0x1000 660fb6f739SPiotr Ziecik 6778a4f036SAlexander Popov /* 6878a4f036SAlexander Popov * Maximum channel counts for individual hardware variants 6978a4f036SAlexander Popov * and the maximum channel count over all supported controllers, 7078a4f036SAlexander Popov * used for data structure size 7178a4f036SAlexander Popov */ 7278a4f036SAlexander Popov #define MPC8308_DMACHAN_MAX 16 7378a4f036SAlexander Popov #define MPC512x_DMACHAN_MAX 64 7478a4f036SAlexander Popov #define MPC_DMA_CHANNELS 64 7578a4f036SAlexander Popov 760fb6f739SPiotr Ziecik /* Arbitration mode of group and channel */ 770fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_EDCG (1 << 31) 780fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERGA (1 << 3) 790fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERCA (1 << 2) 800fb6f739SPiotr Ziecik 810fb6f739SPiotr Ziecik /* Error codes */ 820fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_VLD (1 << 31) 830fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_GPE (1 << 15) 840fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_CPE (1 << 14) 850fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_ERRCHN(err) \ 860fb6f739SPiotr Ziecik (((err) >> 8) & 0x3f) 870fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SAE (1 << 7) 880fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SOE (1 << 6) 890fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DAE (1 << 5) 900fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DOE (1 << 4) 910fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_NCE (1 << 3) 920fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SGE (1 << 2) 930fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SBE (1 << 1) 940fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DBE (1 << 0) 950fb6f739SPiotr Ziecik 96ba2eea25SIlya Yanok #define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6) 97ba2eea25SIlya Yanok 980fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_1 0x00 990fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_2 0x01 1000fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_4 0x02 1010fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_16 0x04 1020fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_32 0x05 1030fb6f739SPiotr Ziecik 1040fb6f739SPiotr Ziecik /* MPC5121 DMA engine registers */ 1050fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_regs { 1060fb6f739SPiotr Ziecik /* 0x00 */ 1070fb6f739SPiotr Ziecik u32 dmacr; /* DMA control register */ 1080fb6f739SPiotr Ziecik u32 dmaes; /* DMA error status */ 1090fb6f739SPiotr Ziecik /* 0x08 */ 1100fb6f739SPiotr Ziecik u32 dmaerqh; /* DMA enable request high(channels 63~32) */ 1110fb6f739SPiotr Ziecik u32 dmaerql; /* DMA enable request low(channels 31~0) */ 1120fb6f739SPiotr Ziecik u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */ 1130fb6f739SPiotr Ziecik u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */ 1140fb6f739SPiotr Ziecik /* 0x18 */ 1150fb6f739SPiotr Ziecik u8 dmaserq; /* DMA set enable request */ 1160fb6f739SPiotr Ziecik u8 dmacerq; /* DMA clear enable request */ 1170fb6f739SPiotr Ziecik u8 dmaseei; /* DMA set enable error interrupt */ 1180fb6f739SPiotr Ziecik u8 dmaceei; /* DMA clear enable error interrupt */ 1190fb6f739SPiotr Ziecik /* 0x1c */ 1200fb6f739SPiotr Ziecik u8 dmacint; /* DMA clear interrupt request */ 1210fb6f739SPiotr Ziecik u8 dmacerr; /* DMA clear error */ 1220fb6f739SPiotr Ziecik u8 dmassrt; /* DMA set start bit */ 1230fb6f739SPiotr Ziecik u8 dmacdne; /* DMA clear DONE status bit */ 1240fb6f739SPiotr Ziecik /* 0x20 */ 1250fb6f739SPiotr Ziecik u32 dmainth; /* DMA interrupt request high(ch63~32) */ 1260fb6f739SPiotr Ziecik u32 dmaintl; /* DMA interrupt request low(ch31~0) */ 1270fb6f739SPiotr Ziecik u32 dmaerrh; /* DMA error high(ch63~32) */ 1280fb6f739SPiotr Ziecik u32 dmaerrl; /* DMA error low(ch31~0) */ 1290fb6f739SPiotr Ziecik /* 0x30 */ 1300fb6f739SPiotr Ziecik u32 dmahrsh; /* DMA hw request status high(ch63~32) */ 1310fb6f739SPiotr Ziecik u32 dmahrsl; /* DMA hardware request status low(ch31~0) */ 132ba2eea25SIlya Yanok union { 1330fb6f739SPiotr Ziecik u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */ 134ba2eea25SIlya Yanok u32 dmagpor; /* (General purpose register on MPC8308) */ 135ba2eea25SIlya Yanok }; 1360fb6f739SPiotr Ziecik u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */ 1370fb6f739SPiotr Ziecik /* 0x40 ~ 0xff */ 1380fb6f739SPiotr Ziecik u32 reserve0[48]; /* Reserved */ 1390fb6f739SPiotr Ziecik /* 0x100 */ 1400fb6f739SPiotr Ziecik u8 dchpri[MPC_DMA_CHANNELS]; 1410fb6f739SPiotr Ziecik /* DMA channels(0~63) priority */ 1420fb6f739SPiotr Ziecik }; 1430fb6f739SPiotr Ziecik 1440fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_tcd { 1450fb6f739SPiotr Ziecik /* 0x00 */ 1460fb6f739SPiotr Ziecik u32 saddr; /* Source address */ 1470fb6f739SPiotr Ziecik 1480fb6f739SPiotr Ziecik u32 smod:5; /* Source address modulo */ 1490fb6f739SPiotr Ziecik u32 ssize:3; /* Source data transfer size */ 1500fb6f739SPiotr Ziecik u32 dmod:5; /* Destination address modulo */ 1510fb6f739SPiotr Ziecik u32 dsize:3; /* Destination data transfer size */ 1520fb6f739SPiotr Ziecik u32 soff:16; /* Signed source address offset */ 1530fb6f739SPiotr Ziecik 1540fb6f739SPiotr Ziecik /* 0x08 */ 1550fb6f739SPiotr Ziecik u32 nbytes; /* Inner "minor" byte count */ 1560fb6f739SPiotr Ziecik u32 slast; /* Last source address adjustment */ 1570fb6f739SPiotr Ziecik u32 daddr; /* Destination address */ 1580fb6f739SPiotr Ziecik 1590fb6f739SPiotr Ziecik /* 0x14 */ 1600fb6f739SPiotr Ziecik u32 citer_elink:1; /* Enable channel-to-channel linking on 1610fb6f739SPiotr Ziecik * minor loop complete 1620fb6f739SPiotr Ziecik */ 1630fb6f739SPiotr Ziecik u32 citer_linkch:6; /* Link channel for minor loop complete */ 1640fb6f739SPiotr Ziecik u32 citer:9; /* Current "major" iteration count */ 1650fb6f739SPiotr Ziecik u32 doff:16; /* Signed destination address offset */ 1660fb6f739SPiotr Ziecik 1670fb6f739SPiotr Ziecik /* 0x18 */ 1680fb6f739SPiotr Ziecik u32 dlast_sga; /* Last Destination address adjustment/scatter 1690fb6f739SPiotr Ziecik * gather address 1700fb6f739SPiotr Ziecik */ 1710fb6f739SPiotr Ziecik 1720fb6f739SPiotr Ziecik /* 0x1c */ 1730fb6f739SPiotr Ziecik u32 biter_elink:1; /* Enable channel-to-channel linking on major 1740fb6f739SPiotr Ziecik * loop complete 1750fb6f739SPiotr Ziecik */ 1760fb6f739SPiotr Ziecik u32 biter_linkch:6; 1770fb6f739SPiotr Ziecik u32 biter:9; /* Beginning "major" iteration count */ 1780fb6f739SPiotr Ziecik u32 bwc:2; /* Bandwidth control */ 1790fb6f739SPiotr Ziecik u32 major_linkch:6; /* Link channel number */ 1800fb6f739SPiotr Ziecik u32 done:1; /* Channel done */ 1810fb6f739SPiotr Ziecik u32 active:1; /* Channel active */ 1820fb6f739SPiotr Ziecik u32 major_elink:1; /* Enable channel-to-channel linking on major 1830fb6f739SPiotr Ziecik * loop complete 1840fb6f739SPiotr Ziecik */ 1850fb6f739SPiotr Ziecik u32 e_sg:1; /* Enable scatter/gather processing */ 1860fb6f739SPiotr Ziecik u32 d_req:1; /* Disable request */ 1870fb6f739SPiotr Ziecik u32 int_half:1; /* Enable an interrupt when major counter is 1880fb6f739SPiotr Ziecik * half complete 1890fb6f739SPiotr Ziecik */ 1900fb6f739SPiotr Ziecik u32 int_maj:1; /* Enable an interrupt when major iteration 1910fb6f739SPiotr Ziecik * count completes 1920fb6f739SPiotr Ziecik */ 1930fb6f739SPiotr Ziecik u32 start:1; /* Channel start */ 1940fb6f739SPiotr Ziecik }; 1950fb6f739SPiotr Ziecik 1960fb6f739SPiotr Ziecik struct mpc_dma_desc { 1970fb6f739SPiotr Ziecik struct dma_async_tx_descriptor desc; 1980fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 1990fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 2000fb6f739SPiotr Ziecik int error; 2010fb6f739SPiotr Ziecik struct list_head node; 20263da8e0dSAlexander Popov int will_access_peripheral; 2030fb6f739SPiotr Ziecik }; 2040fb6f739SPiotr Ziecik 2050fb6f739SPiotr Ziecik struct mpc_dma_chan { 2060fb6f739SPiotr Ziecik struct dma_chan chan; 2070fb6f739SPiotr Ziecik struct list_head free; 2080fb6f739SPiotr Ziecik struct list_head prepared; 2090fb6f739SPiotr Ziecik struct list_head queued; 2100fb6f739SPiotr Ziecik struct list_head active; 2110fb6f739SPiotr Ziecik struct list_head completed; 2120fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 2130fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 2140fb6f739SPiotr Ziecik 21563da8e0dSAlexander Popov /* Settings for access to peripheral FIFO */ 21663da8e0dSAlexander Popov dma_addr_t src_per_paddr; 21763da8e0dSAlexander Popov u32 src_tcd_nunits; 218899ed9ddSMario Six u8 swidth; 21963da8e0dSAlexander Popov dma_addr_t dst_per_paddr; 22063da8e0dSAlexander Popov u32 dst_tcd_nunits; 221899ed9ddSMario Six u8 dwidth; 22263da8e0dSAlexander Popov 2230fb6f739SPiotr Ziecik /* Lock for this structure */ 2240fb6f739SPiotr Ziecik spinlock_t lock; 2250fb6f739SPiotr Ziecik }; 2260fb6f739SPiotr Ziecik 2270fb6f739SPiotr Ziecik struct mpc_dma { 2280fb6f739SPiotr Ziecik struct dma_device dma; 2290fb6f739SPiotr Ziecik struct tasklet_struct tasklet; 2300fb6f739SPiotr Ziecik struct mpc_dma_chan channels[MPC_DMA_CHANNELS]; 2310fb6f739SPiotr Ziecik struct mpc_dma_regs __iomem *regs; 2320fb6f739SPiotr Ziecik struct mpc_dma_tcd __iomem *tcd; 2330fb6f739SPiotr Ziecik int irq; 234ba2eea25SIlya Yanok int irq2; 2350fb6f739SPiotr Ziecik uint error_status; 236ba2eea25SIlya Yanok int is_mpc8308; 2370fb6f739SPiotr Ziecik 2380fb6f739SPiotr Ziecik /* Lock for error_status field in this structure */ 2390fb6f739SPiotr Ziecik spinlock_t error_status_lock; 2400fb6f739SPiotr Ziecik }; 2410fb6f739SPiotr Ziecik 2420fb6f739SPiotr Ziecik #define DRV_NAME "mpc512x_dma" 2430fb6f739SPiotr Ziecik 2440fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma_chan */ 2450fb6f739SPiotr Ziecik static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c) 2460fb6f739SPiotr Ziecik { 2470fb6f739SPiotr Ziecik return container_of(c, struct mpc_dma_chan, chan); 2480fb6f739SPiotr Ziecik } 2490fb6f739SPiotr Ziecik 2500fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma */ 2510fb6f739SPiotr Ziecik static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c) 2520fb6f739SPiotr Ziecik { 2530fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c); 25477fc3976SMario Six 2550fb6f739SPiotr Ziecik return container_of(mchan, struct mpc_dma, channels[c->chan_id]); 2560fb6f739SPiotr Ziecik } 2570fb6f739SPiotr Ziecik 2580fb6f739SPiotr Ziecik /* 2590fb6f739SPiotr Ziecik * Execute all queued DMA descriptors. 2600fb6f739SPiotr Ziecik * 2610fb6f739SPiotr Ziecik * Following requirements must be met while calling mpc_dma_execute(): 2620fb6f739SPiotr Ziecik * a) mchan->lock is acquired, 2630fb6f739SPiotr Ziecik * b) mchan->active list is empty, 2640fb6f739SPiotr Ziecik * c) mchan->queued list contains at least one entry. 2650fb6f739SPiotr Ziecik */ 2660fb6f739SPiotr Ziecik static void mpc_dma_execute(struct mpc_dma_chan *mchan) 2670fb6f739SPiotr Ziecik { 2680fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); 2690fb6f739SPiotr Ziecik struct mpc_dma_desc *first = NULL; 2700fb6f739SPiotr Ziecik struct mpc_dma_desc *prev = NULL; 2710fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 2720fb6f739SPiotr Ziecik int cid = mchan->chan.chan_id; 2730fb6f739SPiotr Ziecik 27463da8e0dSAlexander Popov while (!list_empty(&mchan->queued)) { 27563da8e0dSAlexander Popov mdesc = list_first_entry(&mchan->queued, 27663da8e0dSAlexander Popov struct mpc_dma_desc, node); 27763da8e0dSAlexander Popov /* 27863da8e0dSAlexander Popov * Grab either several mem-to-mem transfer descriptors 27963da8e0dSAlexander Popov * or one peripheral transfer descriptor, 28063da8e0dSAlexander Popov * don't mix mem-to-mem and peripheral transfer descriptors 28163da8e0dSAlexander Popov * within the same 'active' list. 28263da8e0dSAlexander Popov */ 28363da8e0dSAlexander Popov if (mdesc->will_access_peripheral) { 28463da8e0dSAlexander Popov if (list_empty(&mchan->active)) 28563da8e0dSAlexander Popov list_move_tail(&mdesc->node, &mchan->active); 28663da8e0dSAlexander Popov break; 28763da8e0dSAlexander Popov } else { 28863da8e0dSAlexander Popov list_move_tail(&mdesc->node, &mchan->active); 28963da8e0dSAlexander Popov } 29063da8e0dSAlexander Popov } 2910fb6f739SPiotr Ziecik 2920fb6f739SPiotr Ziecik /* Chain descriptors into one transaction */ 2930fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node) { 2940fb6f739SPiotr Ziecik if (!first) 2950fb6f739SPiotr Ziecik first = mdesc; 2960fb6f739SPiotr Ziecik 2970fb6f739SPiotr Ziecik if (!prev) { 2980fb6f739SPiotr Ziecik prev = mdesc; 2990fb6f739SPiotr Ziecik continue; 3000fb6f739SPiotr Ziecik } 3010fb6f739SPiotr Ziecik 3020fb6f739SPiotr Ziecik prev->tcd->dlast_sga = mdesc->tcd_paddr; 3030fb6f739SPiotr Ziecik prev->tcd->e_sg = 1; 3040fb6f739SPiotr Ziecik mdesc->tcd->start = 1; 3050fb6f739SPiotr Ziecik 3060fb6f739SPiotr Ziecik prev = mdesc; 3070fb6f739SPiotr Ziecik } 3080fb6f739SPiotr Ziecik 3090fb6f739SPiotr Ziecik prev->tcd->int_maj = 1; 3100fb6f739SPiotr Ziecik 3110fb6f739SPiotr Ziecik /* Send first descriptor in chain into hardware */ 3120fb6f739SPiotr Ziecik memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); 3136504cf34SIlya Yanok 3146504cf34SIlya Yanok if (first != prev) 3156504cf34SIlya Yanok mdma->tcd[cid].e_sg = 1; 31663da8e0dSAlexander Popov 31763da8e0dSAlexander Popov if (mdma->is_mpc8308) { 31863da8e0dSAlexander Popov /* MPC8308, no request lines, software initiated start */ 3190fb6f739SPiotr Ziecik out_8(&mdma->regs->dmassrt, cid); 32063da8e0dSAlexander Popov } else if (first->will_access_peripheral) { 32163da8e0dSAlexander Popov /* Peripherals involved, start by external request signal */ 32263da8e0dSAlexander Popov out_8(&mdma->regs->dmaserq, cid); 32363da8e0dSAlexander Popov } else { 32463da8e0dSAlexander Popov /* Memory to memory transfer, software initiated start */ 32563da8e0dSAlexander Popov out_8(&mdma->regs->dmassrt, cid); 32663da8e0dSAlexander Popov } 3270fb6f739SPiotr Ziecik } 3280fb6f739SPiotr Ziecik 3290fb6f739SPiotr Ziecik /* Handle interrupt on one half of DMA controller (32 channels) */ 3300fb6f739SPiotr Ziecik static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) 3310fb6f739SPiotr Ziecik { 3320fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 3330fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 3340fb6f739SPiotr Ziecik u32 status = is | es; 3350fb6f739SPiotr Ziecik int ch; 3360fb6f739SPiotr Ziecik 3370fb6f739SPiotr Ziecik while ((ch = fls(status) - 1) >= 0) { 3380fb6f739SPiotr Ziecik status &= ~(1 << ch); 3390fb6f739SPiotr Ziecik mchan = &mdma->channels[ch + off]; 3400fb6f739SPiotr Ziecik 3410fb6f739SPiotr Ziecik spin_lock(&mchan->lock); 3420fb6f739SPiotr Ziecik 3432862559eSIlya Yanok out_8(&mdma->regs->dmacint, ch + off); 3442862559eSIlya Yanok out_8(&mdma->regs->dmacerr, ch + off); 3452862559eSIlya Yanok 3460fb6f739SPiotr Ziecik /* Check error status */ 3470fb6f739SPiotr Ziecik if (es & (1 << ch)) 3480fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node) 3490fb6f739SPiotr Ziecik mdesc->error = -EIO; 3500fb6f739SPiotr Ziecik 3510fb6f739SPiotr Ziecik /* Execute queued descriptors */ 3520fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->active, &mchan->completed); 3530fb6f739SPiotr Ziecik if (!list_empty(&mchan->queued)) 3540fb6f739SPiotr Ziecik mpc_dma_execute(mchan); 3550fb6f739SPiotr Ziecik 3560fb6f739SPiotr Ziecik spin_unlock(&mchan->lock); 3570fb6f739SPiotr Ziecik } 3580fb6f739SPiotr Ziecik } 3590fb6f739SPiotr Ziecik 3600fb6f739SPiotr Ziecik /* Interrupt handler */ 3610fb6f739SPiotr Ziecik static irqreturn_t mpc_dma_irq(int irq, void *data) 3620fb6f739SPiotr Ziecik { 3630fb6f739SPiotr Ziecik struct mpc_dma *mdma = data; 3640fb6f739SPiotr Ziecik uint es; 3650fb6f739SPiotr Ziecik 3660fb6f739SPiotr Ziecik /* Save error status register */ 3670fb6f739SPiotr Ziecik es = in_be32(&mdma->regs->dmaes); 3680fb6f739SPiotr Ziecik spin_lock(&mdma->error_status_lock); 3690fb6f739SPiotr Ziecik if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0) 3700fb6f739SPiotr Ziecik mdma->error_status = es; 3710fb6f739SPiotr Ziecik spin_unlock(&mdma->error_status_lock); 3720fb6f739SPiotr Ziecik 3730fb6f739SPiotr Ziecik /* Handle interrupt on each channel */ 374ba2eea25SIlya Yanok if (mdma->dma.chancnt > 32) { 3750fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth), 3760fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrh), 32); 377ba2eea25SIlya Yanok } 3780fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl), 3790fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrl), 0); 3800fb6f739SPiotr Ziecik 3810fb6f739SPiotr Ziecik /* Schedule tasklet */ 3820fb6f739SPiotr Ziecik tasklet_schedule(&mdma->tasklet); 3830fb6f739SPiotr Ziecik 3840fb6f739SPiotr Ziecik return IRQ_HANDLED; 3850fb6f739SPiotr Ziecik } 3860fb6f739SPiotr Ziecik 38725985edcSLucas De Marchi /* process completed descriptors */ 388a2769913SIlya Yanok static void mpc_dma_process_completed(struct mpc_dma *mdma) 3890fb6f739SPiotr Ziecik { 3900fb6f739SPiotr Ziecik dma_cookie_t last_cookie = 0; 3910fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 3920fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 3930fb6f739SPiotr Ziecik struct dma_async_tx_descriptor *desc; 3940fb6f739SPiotr Ziecik unsigned long flags; 3950fb6f739SPiotr Ziecik LIST_HEAD(list); 3960fb6f739SPiotr Ziecik int i; 3970fb6f739SPiotr Ziecik 398a2769913SIlya Yanok for (i = 0; i < mdma->dma.chancnt; i++) { 399a2769913SIlya Yanok mchan = &mdma->channels[i]; 400a2769913SIlya Yanok 401a2769913SIlya Yanok /* Get all completed descriptors */ 402a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags); 403a2769913SIlya Yanok if (!list_empty(&mchan->completed)) 404a2769913SIlya Yanok list_splice_tail_init(&mchan->completed, &list); 405a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags); 406a2769913SIlya Yanok 407a2769913SIlya Yanok if (list_empty(&list)) 408a2769913SIlya Yanok continue; 409a2769913SIlya Yanok 410a2769913SIlya Yanok /* Execute callbacks and run dependencies */ 411a2769913SIlya Yanok list_for_each_entry(mdesc, &list, node) { 412a2769913SIlya Yanok desc = &mdesc->desc; 413a2769913SIlya Yanok 414a2769913SIlya Yanok if (desc->callback) 415a2769913SIlya Yanok desc->callback(desc->callback_param); 416a2769913SIlya Yanok 417a2769913SIlya Yanok last_cookie = desc->cookie; 418a2769913SIlya Yanok dma_run_dependencies(desc); 419a2769913SIlya Yanok } 420a2769913SIlya Yanok 421a2769913SIlya Yanok /* Free descriptors */ 422a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags); 423a2769913SIlya Yanok list_splice_tail_init(&list, &mchan->free); 4244d4e58deSRussell King - ARM Linux mchan->chan.completed_cookie = last_cookie; 425a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags); 426a2769913SIlya Yanok } 427a2769913SIlya Yanok } 428a2769913SIlya Yanok 429a2769913SIlya Yanok /* DMA Tasklet */ 430a2769913SIlya Yanok static void mpc_dma_tasklet(unsigned long data) 431a2769913SIlya Yanok { 432a2769913SIlya Yanok struct mpc_dma *mdma = (void *)data; 433a2769913SIlya Yanok unsigned long flags; 434a2769913SIlya Yanok uint es; 435a2769913SIlya Yanok 4360fb6f739SPiotr Ziecik spin_lock_irqsave(&mdma->error_status_lock, flags); 4370fb6f739SPiotr Ziecik es = mdma->error_status; 4380fb6f739SPiotr Ziecik mdma->error_status = 0; 4390fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mdma->error_status_lock, flags); 4400fb6f739SPiotr Ziecik 4410fb6f739SPiotr Ziecik /* Print nice error report */ 4420fb6f739SPiotr Ziecik if (es) { 4430fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, 4440fb6f739SPiotr Ziecik "Hardware reported following error(s) on channel %u:\n", 4450fb6f739SPiotr Ziecik MPC_DMA_DMAES_ERRCHN(es)); 4460fb6f739SPiotr Ziecik 4470fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_GPE) 4480fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Group Priority Error\n"); 4490fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_CPE) 4500fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Channel Priority Error\n"); 4510fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SAE) 4520fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Address Error\n"); 4530fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SOE) 45477fc3976SMario Six dev_err(mdma->dma.dev, "- Source Offset Configuration Error\n"); 4550fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DAE) 45677fc3976SMario Six dev_err(mdma->dma.dev, "- Destination Address Error\n"); 4570fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DOE) 45877fc3976SMario Six dev_err(mdma->dma.dev, "- Destination Offset Configuration Error\n"); 4590fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_NCE) 46077fc3976SMario Six dev_err(mdma->dma.dev, "- NBytes/Citter Configuration Error\n"); 4610fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SGE) 46277fc3976SMario Six dev_err(mdma->dma.dev, "- Scatter/Gather Configuration Error\n"); 4630fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SBE) 4640fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Bus Error\n"); 4650fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DBE) 4660fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Destination Bus Error\n"); 4670fb6f739SPiotr Ziecik } 4680fb6f739SPiotr Ziecik 469a2769913SIlya Yanok mpc_dma_process_completed(mdma); 4700fb6f739SPiotr Ziecik } 4710fb6f739SPiotr Ziecik 4720fb6f739SPiotr Ziecik /* Submit descriptor to hardware */ 4730fb6f739SPiotr Ziecik static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd) 4740fb6f739SPiotr Ziecik { 4750fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan); 4760fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 4770fb6f739SPiotr Ziecik unsigned long flags; 4780fb6f739SPiotr Ziecik dma_cookie_t cookie; 4790fb6f739SPiotr Ziecik 4800fb6f739SPiotr Ziecik mdesc = container_of(txd, struct mpc_dma_desc, desc); 4810fb6f739SPiotr Ziecik 4820fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 4830fb6f739SPiotr Ziecik 4840fb6f739SPiotr Ziecik /* Move descriptor to queue */ 4850fb6f739SPiotr Ziecik list_move_tail(&mdesc->node, &mchan->queued); 4860fb6f739SPiotr Ziecik 4870fb6f739SPiotr Ziecik /* If channel is idle, execute all queued descriptors */ 4880fb6f739SPiotr Ziecik if (list_empty(&mchan->active)) 4890fb6f739SPiotr Ziecik mpc_dma_execute(mchan); 4900fb6f739SPiotr Ziecik 4910fb6f739SPiotr Ziecik /* Update cookie */ 492884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(txd); 4930fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 4940fb6f739SPiotr Ziecik 4950fb6f739SPiotr Ziecik return cookie; 4960fb6f739SPiotr Ziecik } 4970fb6f739SPiotr Ziecik 4980fb6f739SPiotr Ziecik /* Alloc channel resources */ 4990fb6f739SPiotr Ziecik static int mpc_dma_alloc_chan_resources(struct dma_chan *chan) 5000fb6f739SPiotr Ziecik { 5010fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 5020fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 5030fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 5040fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 5050fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 5060fb6f739SPiotr Ziecik unsigned long flags; 5070fb6f739SPiotr Ziecik LIST_HEAD(descs); 5080fb6f739SPiotr Ziecik int i; 5090fb6f739SPiotr Ziecik 5100fb6f739SPiotr Ziecik /* Alloc DMA memory for Transfer Control Descriptors */ 5110fb6f739SPiotr Ziecik tcd = dma_alloc_coherent(mdma->dma.dev, 5120fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 5130fb6f739SPiotr Ziecik &tcd_paddr, GFP_KERNEL); 5140fb6f739SPiotr Ziecik if (!tcd) 5150fb6f739SPiotr Ziecik return -ENOMEM; 5160fb6f739SPiotr Ziecik 5170fb6f739SPiotr Ziecik /* Alloc descriptors for this channel */ 5180fb6f739SPiotr Ziecik for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) { 5190fb6f739SPiotr Ziecik mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL); 5200fb6f739SPiotr Ziecik if (!mdesc) { 52177fc3976SMario Six dev_notice(mdma->dma.dev, 52277fc3976SMario Six "Memory allocation error. Allocated only %u descriptors\n", i); 5230fb6f739SPiotr Ziecik break; 5240fb6f739SPiotr Ziecik } 5250fb6f739SPiotr Ziecik 5260fb6f739SPiotr Ziecik dma_async_tx_descriptor_init(&mdesc->desc, chan); 5270fb6f739SPiotr Ziecik mdesc->desc.flags = DMA_CTRL_ACK; 5280fb6f739SPiotr Ziecik mdesc->desc.tx_submit = mpc_dma_tx_submit; 5290fb6f739SPiotr Ziecik 5300fb6f739SPiotr Ziecik mdesc->tcd = &tcd[i]; 5310fb6f739SPiotr Ziecik mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd)); 5320fb6f739SPiotr Ziecik 5330fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &descs); 5340fb6f739SPiotr Ziecik } 5350fb6f739SPiotr Ziecik 5360fb6f739SPiotr Ziecik /* Return error only if no descriptors were allocated */ 5370fb6f739SPiotr Ziecik if (i == 0) { 5380fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev, 5390fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 5400fb6f739SPiotr Ziecik tcd, tcd_paddr); 5410fb6f739SPiotr Ziecik return -ENOMEM; 5420fb6f739SPiotr Ziecik } 5430fb6f739SPiotr Ziecik 5440fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 5450fb6f739SPiotr Ziecik mchan->tcd = tcd; 5460fb6f739SPiotr Ziecik mchan->tcd_paddr = tcd_paddr; 5470fb6f739SPiotr Ziecik list_splice_tail_init(&descs, &mchan->free); 5480fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 5490fb6f739SPiotr Ziecik 5500fb6f739SPiotr Ziecik /* Enable Error Interrupt */ 5510fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaseei, chan->chan_id); 5520fb6f739SPiotr Ziecik 5530fb6f739SPiotr Ziecik return 0; 5540fb6f739SPiotr Ziecik } 5550fb6f739SPiotr Ziecik 5560fb6f739SPiotr Ziecik /* Free channel resources */ 5570fb6f739SPiotr Ziecik static void mpc_dma_free_chan_resources(struct dma_chan *chan) 5580fb6f739SPiotr Ziecik { 5590fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 5600fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 5610fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc, *tmp; 5620fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 5630fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 5640fb6f739SPiotr Ziecik unsigned long flags; 5650fb6f739SPiotr Ziecik LIST_HEAD(descs); 5660fb6f739SPiotr Ziecik 5670fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 5680fb6f739SPiotr Ziecik 5690fb6f739SPiotr Ziecik /* Channel must be idle */ 5700fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->prepared)); 5710fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->queued)); 5720fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->active)); 5730fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->completed)); 5740fb6f739SPiotr Ziecik 5750fb6f739SPiotr Ziecik /* Move data */ 5760fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->free, &descs); 5770fb6f739SPiotr Ziecik tcd = mchan->tcd; 5780fb6f739SPiotr Ziecik tcd_paddr = mchan->tcd_paddr; 5790fb6f739SPiotr Ziecik 5800fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 5810fb6f739SPiotr Ziecik 5820fb6f739SPiotr Ziecik /* Free DMA memory used by descriptors */ 5830fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev, 5840fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 5850fb6f739SPiotr Ziecik tcd, tcd_paddr); 5860fb6f739SPiotr Ziecik 5870fb6f739SPiotr Ziecik /* Free descriptors */ 5880fb6f739SPiotr Ziecik list_for_each_entry_safe(mdesc, tmp, &descs, node) 5890fb6f739SPiotr Ziecik kfree(mdesc); 5900fb6f739SPiotr Ziecik 5910fb6f739SPiotr Ziecik /* Disable Error Interrupt */ 5920fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaceei, chan->chan_id); 5930fb6f739SPiotr Ziecik } 5940fb6f739SPiotr Ziecik 5950fb6f739SPiotr Ziecik /* Send all pending descriptor to hardware */ 5960fb6f739SPiotr Ziecik static void mpc_dma_issue_pending(struct dma_chan *chan) 5970fb6f739SPiotr Ziecik { 5980fb6f739SPiotr Ziecik /* 5990fb6f739SPiotr Ziecik * We are posting descriptors to the hardware as soon as 6000fb6f739SPiotr Ziecik * they are ready, so this function does nothing. 6010fb6f739SPiotr Ziecik */ 6020fb6f739SPiotr Ziecik } 6030fb6f739SPiotr Ziecik 6040fb6f739SPiotr Ziecik /* Check request completion status */ 6050fb6f739SPiotr Ziecik static enum dma_status 60607934481SLinus Walleij mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 60707934481SLinus Walleij struct dma_tx_state *txstate) 6080fb6f739SPiotr Ziecik { 609108fae84SAndy Shevchenko return dma_cookie_status(chan, cookie, txstate); 6100fb6f739SPiotr Ziecik } 6110fb6f739SPiotr Ziecik 6120fb6f739SPiotr Ziecik /* Prepare descriptor for memory to memory copy */ 6130fb6f739SPiotr Ziecik static struct dma_async_tx_descriptor * 6140fb6f739SPiotr Ziecik mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 6150fb6f739SPiotr Ziecik size_t len, unsigned long flags) 6160fb6f739SPiotr Ziecik { 617ba2eea25SIlya Yanok struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 6180fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 6190fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc = NULL; 6200fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 6210fb6f739SPiotr Ziecik unsigned long iflags; 6220fb6f739SPiotr Ziecik 6230fb6f739SPiotr Ziecik /* Get free descriptor */ 6240fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags); 6250fb6f739SPiotr Ziecik if (!list_empty(&mchan->free)) { 6260fb6f739SPiotr Ziecik mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc, 6270fb6f739SPiotr Ziecik node); 6280fb6f739SPiotr Ziecik list_del(&mdesc->node); 6290fb6f739SPiotr Ziecik } 6300fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags); 6310fb6f739SPiotr Ziecik 632a2769913SIlya Yanok if (!mdesc) { 633a2769913SIlya Yanok /* try to free completed descriptors */ 634a2769913SIlya Yanok mpc_dma_process_completed(mdma); 6350fb6f739SPiotr Ziecik return NULL; 636a2769913SIlya Yanok } 6370fb6f739SPiotr Ziecik 6380fb6f739SPiotr Ziecik mdesc->error = 0; 63963da8e0dSAlexander Popov mdesc->will_access_peripheral = 0; 6400fb6f739SPiotr Ziecik tcd = mdesc->tcd; 6410fb6f739SPiotr Ziecik 6420fb6f739SPiotr Ziecik /* Prepare Transfer Control Descriptor for this transaction */ 6430fb6f739SPiotr Ziecik memset(tcd, 0, sizeof(struct mpc_dma_tcd)); 6440fb6f739SPiotr Ziecik 6450fb6f739SPiotr Ziecik if (IS_ALIGNED(src | dst | len, 32)) { 6460fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_32; 6470fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_32; 6480fb6f739SPiotr Ziecik tcd->soff = 32; 6490fb6f739SPiotr Ziecik tcd->doff = 32; 650ba2eea25SIlya Yanok } else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) { 651ba2eea25SIlya Yanok /* MPC8308 doesn't support 16 byte transfers */ 6520fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_16; 6530fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_16; 6540fb6f739SPiotr Ziecik tcd->soff = 16; 6550fb6f739SPiotr Ziecik tcd->doff = 16; 6560fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 4)) { 6570fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_4; 6580fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_4; 6590fb6f739SPiotr Ziecik tcd->soff = 4; 6600fb6f739SPiotr Ziecik tcd->doff = 4; 6610fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 2)) { 6620fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_2; 6630fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_2; 6640fb6f739SPiotr Ziecik tcd->soff = 2; 6650fb6f739SPiotr Ziecik tcd->doff = 2; 6660fb6f739SPiotr Ziecik } else { 6670fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_1; 6680fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_1; 6690fb6f739SPiotr Ziecik tcd->soff = 1; 6700fb6f739SPiotr Ziecik tcd->doff = 1; 6710fb6f739SPiotr Ziecik } 6720fb6f739SPiotr Ziecik 6730fb6f739SPiotr Ziecik tcd->saddr = src; 6740fb6f739SPiotr Ziecik tcd->daddr = dst; 6750fb6f739SPiotr Ziecik tcd->nbytes = len; 6760fb6f739SPiotr Ziecik tcd->biter = 1; 6770fb6f739SPiotr Ziecik tcd->citer = 1; 6780fb6f739SPiotr Ziecik 6790fb6f739SPiotr Ziecik /* Place descriptor in prepared list */ 6800fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags); 6810fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &mchan->prepared); 6820fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags); 6830fb6f739SPiotr Ziecik 6840fb6f739SPiotr Ziecik return &mdesc->desc; 6850fb6f739SPiotr Ziecik } 6860fb6f739SPiotr Ziecik 687899ed9ddSMario Six inline u8 buswidth_to_dmatsize(u8 buswidth) 688899ed9ddSMario Six { 689899ed9ddSMario Six u8 res; 690899ed9ddSMario Six 691899ed9ddSMario Six for (res = 0; buswidth > 1; buswidth /= 2) 692899ed9ddSMario Six res++; 693899ed9ddSMario Six return res; 694899ed9ddSMario Six } 695899ed9ddSMario Six 69663da8e0dSAlexander Popov static struct dma_async_tx_descriptor * 69763da8e0dSAlexander Popov mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 69863da8e0dSAlexander Popov unsigned int sg_len, enum dma_transfer_direction direction, 69963da8e0dSAlexander Popov unsigned long flags, void *context) 70063da8e0dSAlexander Popov { 70163da8e0dSAlexander Popov struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 70263da8e0dSAlexander Popov struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 70363da8e0dSAlexander Popov struct mpc_dma_desc *mdesc = NULL; 70463da8e0dSAlexander Popov dma_addr_t per_paddr; 70563da8e0dSAlexander Popov u32 tcd_nunits; 70663da8e0dSAlexander Popov struct mpc_dma_tcd *tcd; 70763da8e0dSAlexander Popov unsigned long iflags; 70863da8e0dSAlexander Popov struct scatterlist *sg; 70963da8e0dSAlexander Popov size_t len; 71063da8e0dSAlexander Popov int iter, i; 71163da8e0dSAlexander Popov 71263da8e0dSAlexander Popov /* Currently there is no proper support for scatter/gather */ 71363da8e0dSAlexander Popov if (sg_len != 1) 71463da8e0dSAlexander Popov return NULL; 71563da8e0dSAlexander Popov 71663da8e0dSAlexander Popov if (!is_slave_direction(direction)) 71763da8e0dSAlexander Popov return NULL; 71863da8e0dSAlexander Popov 71963da8e0dSAlexander Popov for_each_sg(sgl, sg, sg_len, i) { 72063da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags); 72163da8e0dSAlexander Popov 72263da8e0dSAlexander Popov mdesc = list_first_entry(&mchan->free, 72363da8e0dSAlexander Popov struct mpc_dma_desc, node); 72463da8e0dSAlexander Popov if (!mdesc) { 72563da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags); 72663da8e0dSAlexander Popov /* Try to free completed descriptors */ 72763da8e0dSAlexander Popov mpc_dma_process_completed(mdma); 72863da8e0dSAlexander Popov return NULL; 72963da8e0dSAlexander Popov } 73063da8e0dSAlexander Popov 73163da8e0dSAlexander Popov list_del(&mdesc->node); 73263da8e0dSAlexander Popov 73363da8e0dSAlexander Popov if (direction == DMA_DEV_TO_MEM) { 73463da8e0dSAlexander Popov per_paddr = mchan->src_per_paddr; 73563da8e0dSAlexander Popov tcd_nunits = mchan->src_tcd_nunits; 73663da8e0dSAlexander Popov } else { 73763da8e0dSAlexander Popov per_paddr = mchan->dst_per_paddr; 73863da8e0dSAlexander Popov tcd_nunits = mchan->dst_tcd_nunits; 73963da8e0dSAlexander Popov } 74063da8e0dSAlexander Popov 74163da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags); 74263da8e0dSAlexander Popov 74363da8e0dSAlexander Popov if (per_paddr == 0 || tcd_nunits == 0) 74463da8e0dSAlexander Popov goto err_prep; 74563da8e0dSAlexander Popov 74663da8e0dSAlexander Popov mdesc->error = 0; 74763da8e0dSAlexander Popov mdesc->will_access_peripheral = 1; 74863da8e0dSAlexander Popov 74963da8e0dSAlexander Popov /* Prepare Transfer Control Descriptor for this transaction */ 75063da8e0dSAlexander Popov tcd = mdesc->tcd; 75163da8e0dSAlexander Popov 75263da8e0dSAlexander Popov memset(tcd, 0, sizeof(struct mpc_dma_tcd)); 75363da8e0dSAlexander Popov 75463da8e0dSAlexander Popov if (direction == DMA_DEV_TO_MEM) { 75563da8e0dSAlexander Popov tcd->saddr = per_paddr; 75663da8e0dSAlexander Popov tcd->daddr = sg_dma_address(sg); 757899ed9ddSMario Six 758899ed9ddSMario Six if (!IS_ALIGNED(sg_dma_address(sg), mchan->dwidth)) 759899ed9ddSMario Six goto err_prep; 760899ed9ddSMario Six 76163da8e0dSAlexander Popov tcd->soff = 0; 762899ed9ddSMario Six tcd->doff = mchan->dwidth; 76363da8e0dSAlexander Popov } else { 76463da8e0dSAlexander Popov tcd->saddr = sg_dma_address(sg); 76563da8e0dSAlexander Popov tcd->daddr = per_paddr; 766899ed9ddSMario Six 767899ed9ddSMario Six if (!IS_ALIGNED(sg_dma_address(sg), mchan->swidth)) 768899ed9ddSMario Six goto err_prep; 769899ed9ddSMario Six 770899ed9ddSMario Six tcd->soff = mchan->swidth; 77163da8e0dSAlexander Popov tcd->doff = 0; 77263da8e0dSAlexander Popov } 77363da8e0dSAlexander Popov 774899ed9ddSMario Six tcd->ssize = buswidth_to_dmatsize(mchan->swidth); 775899ed9ddSMario Six tcd->dsize = buswidth_to_dmatsize(mchan->dwidth); 77663da8e0dSAlexander Popov 777237ec709SMario Six if (mdma->is_mpc8308) { 778237ec709SMario Six tcd->nbytes = sg_dma_len(sg); 779899ed9ddSMario Six if (!IS_ALIGNED(tcd->nbytes, mchan->swidth)) 780237ec709SMario Six goto err_prep; 781237ec709SMario Six 782237ec709SMario Six /* No major loops for MPC8303 */ 783237ec709SMario Six tcd->biter = 1; 784237ec709SMario Six tcd->citer = 1; 785237ec709SMario Six } else { 78663da8e0dSAlexander Popov len = sg_dma_len(sg); 787899ed9ddSMario Six tcd->nbytes = tcd_nunits * tcd->ssize; 78863da8e0dSAlexander Popov if (!IS_ALIGNED(len, tcd->nbytes)) 78963da8e0dSAlexander Popov goto err_prep; 79063da8e0dSAlexander Popov 79163da8e0dSAlexander Popov iter = len / tcd->nbytes; 79263da8e0dSAlexander Popov if (iter >= 1 << 15) { 79363da8e0dSAlexander Popov /* len is too big */ 79463da8e0dSAlexander Popov goto err_prep; 79563da8e0dSAlexander Popov } 79663da8e0dSAlexander Popov /* citer_linkch contains the high bits of iter */ 79763da8e0dSAlexander Popov tcd->biter = iter & 0x1ff; 79863da8e0dSAlexander Popov tcd->biter_linkch = iter >> 9; 79963da8e0dSAlexander Popov tcd->citer = tcd->biter; 80063da8e0dSAlexander Popov tcd->citer_linkch = tcd->biter_linkch; 801237ec709SMario Six } 80263da8e0dSAlexander Popov 80363da8e0dSAlexander Popov tcd->e_sg = 0; 80463da8e0dSAlexander Popov tcd->d_req = 1; 80563da8e0dSAlexander Popov 80663da8e0dSAlexander Popov /* Place descriptor in prepared list */ 80763da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags); 80863da8e0dSAlexander Popov list_add_tail(&mdesc->node, &mchan->prepared); 80963da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags); 81063da8e0dSAlexander Popov } 81163da8e0dSAlexander Popov 81263da8e0dSAlexander Popov return &mdesc->desc; 81363da8e0dSAlexander Popov 81463da8e0dSAlexander Popov err_prep: 81563da8e0dSAlexander Popov /* Put the descriptor back */ 81663da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags); 81763da8e0dSAlexander Popov list_add_tail(&mdesc->node, &mchan->free); 81863da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags); 81963da8e0dSAlexander Popov 82063da8e0dSAlexander Popov return NULL; 82163da8e0dSAlexander Popov } 82263da8e0dSAlexander Popov 823899ed9ddSMario Six inline bool is_buswidth_valid(u8 buswidth, bool is_mpc8308) 824899ed9ddSMario Six { 825899ed9ddSMario Six switch (buswidth) { 826899ed9ddSMario Six case 16: 827899ed9ddSMario Six if (is_mpc8308) 828899ed9ddSMario Six return false; 829899ed9ddSMario Six case 1: 830899ed9ddSMario Six case 2: 831899ed9ddSMario Six case 4: 832899ed9ddSMario Six case 32: 833899ed9ddSMario Six break; 834899ed9ddSMario Six default: 835899ed9ddSMario Six return false; 836899ed9ddSMario Six } 837899ed9ddSMario Six 838899ed9ddSMario Six return true; 839899ed9ddSMario Six } 840899ed9ddSMario Six 84195335f1fSMaxime Ripard static int mpc_dma_device_config(struct dma_chan *chan, 84295335f1fSMaxime Ripard struct dma_slave_config *cfg) 84363da8e0dSAlexander Popov { 84495335f1fSMaxime Ripard struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 845899ed9ddSMario Six struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); 84663da8e0dSAlexander Popov unsigned long flags; 84763da8e0dSAlexander Popov 84863da8e0dSAlexander Popov /* 84963da8e0dSAlexander Popov * Software constraints: 850899ed9ddSMario Six * - only transfers between a peripheral device and memory are 851899ed9ddSMario Six * supported 852899ed9ddSMario Six * - transfer chunk sizes of 1, 2, 4, 16 (for MPC512x), and 32 bytes 853899ed9ddSMario Six * are supported, and, consequently, source addresses and 854899ed9ddSMario Six * destination addresses; must be aligned accordingly; furthermore, 855899ed9ddSMario Six * for MPC512x SoCs, the transfer size must be aligned on (chunk 856899ed9ddSMario Six * size * maxburst) 857899ed9ddSMario Six * - during the transfer, the RAM address is incremented by the size 858899ed9ddSMario Six * of transfer chunk 859899ed9ddSMario Six * - the peripheral port's address is constant during the transfer. 86063da8e0dSAlexander Popov */ 86163da8e0dSAlexander Popov 862899ed9ddSMario Six if (!IS_ALIGNED(cfg->src_addr, cfg->src_addr_width) || 863899ed9ddSMario Six !IS_ALIGNED(cfg->dst_addr, cfg->dst_addr_width)) { 86463da8e0dSAlexander Popov return -EINVAL; 86563da8e0dSAlexander Popov } 86663da8e0dSAlexander Popov 867899ed9ddSMario Six if (!is_buswidth_valid(cfg->src_addr_width, mdma->is_mpc8308) || 868899ed9ddSMario Six !is_buswidth_valid(cfg->dst_addr_width, mdma->is_mpc8308)) 869899ed9ddSMario Six return -EINVAL; 870899ed9ddSMario Six 87163da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, flags); 87263da8e0dSAlexander Popov 87363da8e0dSAlexander Popov mchan->src_per_paddr = cfg->src_addr; 87463da8e0dSAlexander Popov mchan->src_tcd_nunits = cfg->src_maxburst; 875899ed9ddSMario Six mchan->swidth = cfg->src_addr_width; 87663da8e0dSAlexander Popov mchan->dst_per_paddr = cfg->dst_addr; 87763da8e0dSAlexander Popov mchan->dst_tcd_nunits = cfg->dst_maxburst; 878899ed9ddSMario Six mchan->dwidth = cfg->dst_addr_width; 87963da8e0dSAlexander Popov 88063da8e0dSAlexander Popov /* Apply defaults */ 88163da8e0dSAlexander Popov if (mchan->src_tcd_nunits == 0) 88263da8e0dSAlexander Popov mchan->src_tcd_nunits = 1; 88363da8e0dSAlexander Popov if (mchan->dst_tcd_nunits == 0) 88463da8e0dSAlexander Popov mchan->dst_tcd_nunits = 1; 88563da8e0dSAlexander Popov 88663da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, flags); 88763da8e0dSAlexander Popov 88863da8e0dSAlexander Popov return 0; 88963da8e0dSAlexander Popov } 89063da8e0dSAlexander Popov 89195335f1fSMaxime Ripard static int mpc_dma_device_terminate_all(struct dma_chan *chan) 89295335f1fSMaxime Ripard { 89395335f1fSMaxime Ripard struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 89495335f1fSMaxime Ripard struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 89595335f1fSMaxime Ripard unsigned long flags; 89695335f1fSMaxime Ripard 89795335f1fSMaxime Ripard /* Disable channel requests */ 89895335f1fSMaxime Ripard spin_lock_irqsave(&mchan->lock, flags); 89995335f1fSMaxime Ripard 90095335f1fSMaxime Ripard out_8(&mdma->regs->dmacerq, chan->chan_id); 90195335f1fSMaxime Ripard list_splice_tail_init(&mchan->prepared, &mchan->free); 90295335f1fSMaxime Ripard list_splice_tail_init(&mchan->queued, &mchan->free); 90395335f1fSMaxime Ripard list_splice_tail_init(&mchan->active, &mchan->free); 90495335f1fSMaxime Ripard 90595335f1fSMaxime Ripard spin_unlock_irqrestore(&mchan->lock, flags); 90695335f1fSMaxime Ripard 90795335f1fSMaxime Ripard return 0; 90863da8e0dSAlexander Popov } 90963da8e0dSAlexander Popov 910463a1f8bSBill Pemberton static int mpc_dma_probe(struct platform_device *op) 9110fb6f739SPiotr Ziecik { 912b4a75c91SAnatolij Gustschin struct device_node *dn = op->dev.of_node; 9130fb6f739SPiotr Ziecik struct device *dev = &op->dev; 9140fb6f739SPiotr Ziecik struct dma_device *dma; 9150fb6f739SPiotr Ziecik struct mpc_dma *mdma; 9160fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 9170fb6f739SPiotr Ziecik struct resource res; 9180fb6f739SPiotr Ziecik ulong regs_start, regs_size; 9190fb6f739SPiotr Ziecik int retval, i; 9209d82faebSMaxime Ripard u8 chancnt; 9210fb6f739SPiotr Ziecik 9220fb6f739SPiotr Ziecik mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL); 9230fb6f739SPiotr Ziecik if (!mdma) { 924baca66f7SAlexander Popov retval = -ENOMEM; 925baca66f7SAlexander Popov goto err; 9260fb6f739SPiotr Ziecik } 9270fb6f739SPiotr Ziecik 9280fb6f739SPiotr Ziecik mdma->irq = irq_of_parse_and_map(dn, 0); 9290fb6f739SPiotr Ziecik if (mdma->irq == NO_IRQ) { 9300fb6f739SPiotr Ziecik dev_err(dev, "Error mapping IRQ!\n"); 931baca66f7SAlexander Popov retval = -EINVAL; 932baca66f7SAlexander Popov goto err; 9330fb6f739SPiotr Ziecik } 9340fb6f739SPiotr Ziecik 935ba2eea25SIlya Yanok if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) { 936ba2eea25SIlya Yanok mdma->is_mpc8308 = 1; 937ba2eea25SIlya Yanok mdma->irq2 = irq_of_parse_and_map(dn, 1); 938ba2eea25SIlya Yanok if (mdma->irq2 == NO_IRQ) { 939ba2eea25SIlya Yanok dev_err(dev, "Error mapping IRQ!\n"); 940baca66f7SAlexander Popov retval = -EINVAL; 941baca66f7SAlexander Popov goto err_dispose1; 942ba2eea25SIlya Yanok } 943ba2eea25SIlya Yanok } 944ba2eea25SIlya Yanok 9450fb6f739SPiotr Ziecik retval = of_address_to_resource(dn, 0, &res); 9460fb6f739SPiotr Ziecik if (retval) { 9470fb6f739SPiotr Ziecik dev_err(dev, "Error parsing memory region!\n"); 948baca66f7SAlexander Popov goto err_dispose2; 9490fb6f739SPiotr Ziecik } 9500fb6f739SPiotr Ziecik 9510fb6f739SPiotr Ziecik regs_start = res.start; 9528381fc35STobias Klauser regs_size = resource_size(&res); 9530fb6f739SPiotr Ziecik 9540fb6f739SPiotr Ziecik if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) { 9550fb6f739SPiotr Ziecik dev_err(dev, "Error requesting memory region!\n"); 956baca66f7SAlexander Popov retval = -EBUSY; 957baca66f7SAlexander Popov goto err_dispose2; 9580fb6f739SPiotr Ziecik } 9590fb6f739SPiotr Ziecik 9600fb6f739SPiotr Ziecik mdma->regs = devm_ioremap(dev, regs_start, regs_size); 9610fb6f739SPiotr Ziecik if (!mdma->regs) { 9620fb6f739SPiotr Ziecik dev_err(dev, "Error mapping memory region!\n"); 963baca66f7SAlexander Popov retval = -ENOMEM; 964baca66f7SAlexander Popov goto err_dispose2; 9650fb6f739SPiotr Ziecik } 9660fb6f739SPiotr Ziecik 9670fb6f739SPiotr Ziecik mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs) 9680fb6f739SPiotr Ziecik + MPC_DMA_TCD_OFFSET); 9690fb6f739SPiotr Ziecik 970baca66f7SAlexander Popov retval = request_irq(mdma->irq, &mpc_dma_irq, 0, DRV_NAME, mdma); 9710fb6f739SPiotr Ziecik if (retval) { 9720fb6f739SPiotr Ziecik dev_err(dev, "Error requesting IRQ!\n"); 973baca66f7SAlexander Popov retval = -EINVAL; 974baca66f7SAlexander Popov goto err_dispose2; 9750fb6f739SPiotr Ziecik } 9760fb6f739SPiotr Ziecik 977ba2eea25SIlya Yanok if (mdma->is_mpc8308) { 978baca66f7SAlexander Popov retval = request_irq(mdma->irq2, &mpc_dma_irq, 0, 979ba2eea25SIlya Yanok DRV_NAME, mdma); 980ba2eea25SIlya Yanok if (retval) { 981ba2eea25SIlya Yanok dev_err(dev, "Error requesting IRQ2!\n"); 982baca66f7SAlexander Popov retval = -EINVAL; 983baca66f7SAlexander Popov goto err_free1; 984ba2eea25SIlya Yanok } 985ba2eea25SIlya Yanok } 986ba2eea25SIlya Yanok 9870fb6f739SPiotr Ziecik spin_lock_init(&mdma->error_status_lock); 9880fb6f739SPiotr Ziecik 9890fb6f739SPiotr Ziecik dma = &mdma->dma; 9900fb6f739SPiotr Ziecik dma->dev = dev; 9910fb6f739SPiotr Ziecik dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources; 9920fb6f739SPiotr Ziecik dma->device_free_chan_resources = mpc_dma_free_chan_resources; 9930fb6f739SPiotr Ziecik dma->device_issue_pending = mpc_dma_issue_pending; 99407934481SLinus Walleij dma->device_tx_status = mpc_dma_tx_status; 9950fb6f739SPiotr Ziecik dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy; 99663da8e0dSAlexander Popov dma->device_prep_slave_sg = mpc_dma_prep_slave_sg; 99795335f1fSMaxime Ripard dma->device_config = mpc_dma_device_config; 99895335f1fSMaxime Ripard dma->device_terminate_all = mpc_dma_device_terminate_all; 9990fb6f739SPiotr Ziecik 10000fb6f739SPiotr Ziecik INIT_LIST_HEAD(&dma->channels); 10010fb6f739SPiotr Ziecik dma_cap_set(DMA_MEMCPY, dma->cap_mask); 100263da8e0dSAlexander Popov dma_cap_set(DMA_SLAVE, dma->cap_mask); 10030fb6f739SPiotr Ziecik 10049d82faebSMaxime Ripard if (mdma->is_mpc8308) 10059d82faebSMaxime Ripard chancnt = MPC8308_DMACHAN_MAX; 10069d82faebSMaxime Ripard else 10079d82faebSMaxime Ripard chancnt = MPC512x_DMACHAN_MAX; 10089d82faebSMaxime Ripard 10099d82faebSMaxime Ripard for (i = 0; i < chancnt; i++) { 10100fb6f739SPiotr Ziecik mchan = &mdma->channels[i]; 10110fb6f739SPiotr Ziecik 10120fb6f739SPiotr Ziecik mchan->chan.device = dma; 1013d3ee98cdSRussell King - ARM Linux dma_cookie_init(&mchan->chan); 10140fb6f739SPiotr Ziecik 10150fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->free); 10160fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->prepared); 10170fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->queued); 10180fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->active); 10190fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->completed); 10200fb6f739SPiotr Ziecik 10210fb6f739SPiotr Ziecik spin_lock_init(&mchan->lock); 10220fb6f739SPiotr Ziecik list_add_tail(&mchan->chan.device_node, &dma->channels); 10230fb6f739SPiotr Ziecik } 10240fb6f739SPiotr Ziecik 10250fb6f739SPiotr Ziecik tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma); 10260fb6f739SPiotr Ziecik 10270fb6f739SPiotr Ziecik /* 10280fb6f739SPiotr Ziecik * Configure DMA Engine: 10290fb6f739SPiotr Ziecik * - Dynamic clock, 10300fb6f739SPiotr Ziecik * - Round-robin group arbitration, 10310fb6f739SPiotr Ziecik * - Round-robin channel arbitration. 10320fb6f739SPiotr Ziecik */ 103378a4f036SAlexander Popov if (mdma->is_mpc8308) { 103478a4f036SAlexander Popov /* MPC8308 has 16 channels and lacks some registers */ 103578a4f036SAlexander Popov out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA); 103678a4f036SAlexander Popov 103778a4f036SAlexander Popov /* enable snooping */ 103878a4f036SAlexander Popov out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE); 103978a4f036SAlexander Popov /* Disable error interrupts */ 104078a4f036SAlexander Popov out_be32(&mdma->regs->dmaeeil, 0); 104178a4f036SAlexander Popov 104278a4f036SAlexander Popov /* Clear interrupts status */ 104378a4f036SAlexander Popov out_be32(&mdma->regs->dmaintl, 0xFFFF); 104478a4f036SAlexander Popov out_be32(&mdma->regs->dmaerrl, 0xFFFF); 104578a4f036SAlexander Popov } else { 10460fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG | 104777fc3976SMario Six MPC_DMA_DMACR_ERGA | 104877fc3976SMario Six MPC_DMA_DMACR_ERCA); 10490fb6f739SPiotr Ziecik 10500fb6f739SPiotr Ziecik /* Disable hardware DMA requests */ 10510fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerqh, 0); 10520fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerql, 0); 10530fb6f739SPiotr Ziecik 10540fb6f739SPiotr Ziecik /* Disable error interrupts */ 10550fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeih, 0); 10560fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeil, 0); 10570fb6f739SPiotr Ziecik 10580fb6f739SPiotr Ziecik /* Clear interrupts status */ 10590fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmainth, 0xFFFFFFFF); 10600fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF); 10610fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF); 10620fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF); 10630fb6f739SPiotr Ziecik 10640fb6f739SPiotr Ziecik /* Route interrupts to IPIC */ 10650fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaihsa, 0); 10660fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmailsa, 0); 1067ba2eea25SIlya Yanok } 10680fb6f739SPiotr Ziecik 10690fb6f739SPiotr Ziecik /* Register DMA engine */ 10700fb6f739SPiotr Ziecik dev_set_drvdata(dev, mdma); 10710fb6f739SPiotr Ziecik retval = dma_async_device_register(dma); 1072baca66f7SAlexander Popov if (retval) 1073baca66f7SAlexander Popov goto err_free2; 10740fb6f739SPiotr Ziecik 1075ec1f0c96SAlexander Popov /* Register with OF helpers for DMA lookups (nonfatal) */ 1076ec1f0c96SAlexander Popov if (dev->of_node) { 1077ec1f0c96SAlexander Popov retval = of_dma_controller_register(dev->of_node, 1078ec1f0c96SAlexander Popov of_dma_xlate_by_chan_id, mdma); 1079ec1f0c96SAlexander Popov if (retval) 1080ec1f0c96SAlexander Popov dev_warn(dev, "Could not register for OF lookup\n"); 1081ec1f0c96SAlexander Popov } 1082ec1f0c96SAlexander Popov 1083ec1f0c96SAlexander Popov return 0; 1084baca66f7SAlexander Popov 1085baca66f7SAlexander Popov err_free2: 1086baca66f7SAlexander Popov if (mdma->is_mpc8308) 1087baca66f7SAlexander Popov free_irq(mdma->irq2, mdma); 1088baca66f7SAlexander Popov err_free1: 1089baca66f7SAlexander Popov free_irq(mdma->irq, mdma); 1090baca66f7SAlexander Popov err_dispose2: 1091baca66f7SAlexander Popov if (mdma->is_mpc8308) 1092baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq2); 1093baca66f7SAlexander Popov err_dispose1: 1094baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq); 1095baca66f7SAlexander Popov err: 1096baca66f7SAlexander Popov return retval; 10970fb6f739SPiotr Ziecik } 10980fb6f739SPiotr Ziecik 10994bf27b8bSGreg Kroah-Hartman static int mpc_dma_remove(struct platform_device *op) 11000fb6f739SPiotr Ziecik { 11010fb6f739SPiotr Ziecik struct device *dev = &op->dev; 11020fb6f739SPiotr Ziecik struct mpc_dma *mdma = dev_get_drvdata(dev); 11030fb6f739SPiotr Ziecik 1104ec1f0c96SAlexander Popov if (dev->of_node) 1105ec1f0c96SAlexander Popov of_dma_controller_free(dev->of_node); 11060fb6f739SPiotr Ziecik dma_async_device_unregister(&mdma->dma); 1107baca66f7SAlexander Popov if (mdma->is_mpc8308) { 1108baca66f7SAlexander Popov free_irq(mdma->irq2, mdma); 1109baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq2); 1110baca66f7SAlexander Popov } 1111baca66f7SAlexander Popov free_irq(mdma->irq, mdma); 11120fb6f739SPiotr Ziecik irq_dispose_mapping(mdma->irq); 11130fb6f739SPiotr Ziecik 11140fb6f739SPiotr Ziecik return 0; 11150fb6f739SPiotr Ziecik } 11160fb6f739SPiotr Ziecik 111757c03422SFabian Frederick static const struct of_device_id mpc_dma_match[] = { 11180fb6f739SPiotr Ziecik { .compatible = "fsl,mpc5121-dma", }, 111962057d33SAlexander Popov { .compatible = "fsl,mpc8308-dma", }, 11200fb6f739SPiotr Ziecik {}, 11210fb6f739SPiotr Ziecik }; 11229ace300cSLuis de Bethencourt MODULE_DEVICE_TABLE(of, mpc_dma_match); 11230fb6f739SPiotr Ziecik 112400006124SGrant Likely static struct platform_driver mpc_dma_driver = { 11250fb6f739SPiotr Ziecik .probe = mpc_dma_probe, 1126a7d6e3ecSBill Pemberton .remove = mpc_dma_remove, 11270fb6f739SPiotr Ziecik .driver = { 11280fb6f739SPiotr Ziecik .name = DRV_NAME, 1129b4a75c91SAnatolij Gustschin .of_match_table = mpc_dma_match, 11300fb6f739SPiotr Ziecik }, 11310fb6f739SPiotr Ziecik }; 11320fb6f739SPiotr Ziecik 1133c94e9105SAxel Lin module_platform_driver(mpc_dma_driver); 11340fb6f739SPiotr Ziecik 11350fb6f739SPiotr Ziecik MODULE_LICENSE("GPL"); 11360fb6f739SPiotr Ziecik MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>"); 1137