10fb6f739SPiotr Ziecik /* 20fb6f739SPiotr Ziecik * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008. 30fb6f739SPiotr Ziecik * Copyright (C) Semihalf 2009 4ba2eea25SIlya Yanok * Copyright (C) Ilya Yanok, Emcraft Systems 2010 50fb6f739SPiotr Ziecik * 60fb6f739SPiotr Ziecik * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description 70fb6f739SPiotr Ziecik * (defines, structures and comments) was taken from MPC5121 DMA driver 80fb6f739SPiotr Ziecik * written by Hongjun Chen <hong-jun.chen@freescale.com>. 90fb6f739SPiotr Ziecik * 100fb6f739SPiotr Ziecik * Approved as OSADL project by a majority of OSADL members and funded 110fb6f739SPiotr Ziecik * by OSADL membership fees in 2009; for details see www.osadl.org. 120fb6f739SPiotr Ziecik * 130fb6f739SPiotr Ziecik * This program is free software; you can redistribute it and/or modify it 140fb6f739SPiotr Ziecik * under the terms of the GNU General Public License as published by the Free 150fb6f739SPiotr Ziecik * Software Foundation; either version 2 of the License, or (at your option) 160fb6f739SPiotr Ziecik * any later version. 170fb6f739SPiotr Ziecik * 180fb6f739SPiotr Ziecik * This program is distributed in the hope that it will be useful, but WITHOUT 190fb6f739SPiotr Ziecik * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 200fb6f739SPiotr Ziecik * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 210fb6f739SPiotr Ziecik * more details. 220fb6f739SPiotr Ziecik * 230fb6f739SPiotr Ziecik * You should have received a copy of the GNU General Public License along with 240fb6f739SPiotr Ziecik * this program; if not, write to the Free Software Foundation, Inc., 59 250fb6f739SPiotr Ziecik * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 260fb6f739SPiotr Ziecik * 270fb6f739SPiotr Ziecik * The full GNU General Public License is included in this distribution in the 280fb6f739SPiotr Ziecik * file called COPYING. 290fb6f739SPiotr Ziecik */ 300fb6f739SPiotr Ziecik 310fb6f739SPiotr Ziecik /* 320fb6f739SPiotr Ziecik * This is initial version of MPC5121 DMA driver. Only memory to memory 330fb6f739SPiotr Ziecik * transfers are supported (tested using dmatest module). 340fb6f739SPiotr Ziecik */ 350fb6f739SPiotr Ziecik 360fb6f739SPiotr Ziecik #include <linux/module.h> 370fb6f739SPiotr Ziecik #include <linux/dmaengine.h> 380fb6f739SPiotr Ziecik #include <linux/dma-mapping.h> 390fb6f739SPiotr Ziecik #include <linux/interrupt.h> 400fb6f739SPiotr Ziecik #include <linux/io.h> 415a0e3ad6STejun Heo #include <linux/slab.h> 425af50730SRob Herring #include <linux/of_address.h> 430fb6f739SPiotr Ziecik #include <linux/of_device.h> 445af50730SRob Herring #include <linux/of_irq.h> 450fb6f739SPiotr Ziecik #include <linux/of_platform.h> 460fb6f739SPiotr Ziecik 470fb6f739SPiotr Ziecik #include <linux/random.h> 480fb6f739SPiotr Ziecik 49d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 50d2ebfb33SRussell King - ARM Linux 510fb6f739SPiotr Ziecik /* Number of DMA Transfer descriptors allocated per channel */ 520fb6f739SPiotr Ziecik #define MPC_DMA_DESCRIPTORS 64 530fb6f739SPiotr Ziecik 540fb6f739SPiotr Ziecik /* Macro definitions */ 550fb6f739SPiotr Ziecik #define MPC_DMA_CHANNELS 64 560fb6f739SPiotr Ziecik #define MPC_DMA_TCD_OFFSET 0x1000 570fb6f739SPiotr Ziecik 580fb6f739SPiotr Ziecik /* Arbitration mode of group and channel */ 590fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_EDCG (1 << 31) 600fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERGA (1 << 3) 610fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERCA (1 << 2) 620fb6f739SPiotr Ziecik 630fb6f739SPiotr Ziecik /* Error codes */ 640fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_VLD (1 << 31) 650fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_GPE (1 << 15) 660fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_CPE (1 << 14) 670fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_ERRCHN(err) \ 680fb6f739SPiotr Ziecik (((err) >> 8) & 0x3f) 690fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SAE (1 << 7) 700fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SOE (1 << 6) 710fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DAE (1 << 5) 720fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DOE (1 << 4) 730fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_NCE (1 << 3) 740fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SGE (1 << 2) 750fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SBE (1 << 1) 760fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DBE (1 << 0) 770fb6f739SPiotr Ziecik 78ba2eea25SIlya Yanok #define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6) 79ba2eea25SIlya Yanok 800fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_1 0x00 810fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_2 0x01 820fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_4 0x02 830fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_16 0x04 840fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_32 0x05 850fb6f739SPiotr Ziecik 860fb6f739SPiotr Ziecik /* MPC5121 DMA engine registers */ 870fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_regs { 880fb6f739SPiotr Ziecik /* 0x00 */ 890fb6f739SPiotr Ziecik u32 dmacr; /* DMA control register */ 900fb6f739SPiotr Ziecik u32 dmaes; /* DMA error status */ 910fb6f739SPiotr Ziecik /* 0x08 */ 920fb6f739SPiotr Ziecik u32 dmaerqh; /* DMA enable request high(channels 63~32) */ 930fb6f739SPiotr Ziecik u32 dmaerql; /* DMA enable request low(channels 31~0) */ 940fb6f739SPiotr Ziecik u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */ 950fb6f739SPiotr Ziecik u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */ 960fb6f739SPiotr Ziecik /* 0x18 */ 970fb6f739SPiotr Ziecik u8 dmaserq; /* DMA set enable request */ 980fb6f739SPiotr Ziecik u8 dmacerq; /* DMA clear enable request */ 990fb6f739SPiotr Ziecik u8 dmaseei; /* DMA set enable error interrupt */ 1000fb6f739SPiotr Ziecik u8 dmaceei; /* DMA clear enable error interrupt */ 1010fb6f739SPiotr Ziecik /* 0x1c */ 1020fb6f739SPiotr Ziecik u8 dmacint; /* DMA clear interrupt request */ 1030fb6f739SPiotr Ziecik u8 dmacerr; /* DMA clear error */ 1040fb6f739SPiotr Ziecik u8 dmassrt; /* DMA set start bit */ 1050fb6f739SPiotr Ziecik u8 dmacdne; /* DMA clear DONE status bit */ 1060fb6f739SPiotr Ziecik /* 0x20 */ 1070fb6f739SPiotr Ziecik u32 dmainth; /* DMA interrupt request high(ch63~32) */ 1080fb6f739SPiotr Ziecik u32 dmaintl; /* DMA interrupt request low(ch31~0) */ 1090fb6f739SPiotr Ziecik u32 dmaerrh; /* DMA error high(ch63~32) */ 1100fb6f739SPiotr Ziecik u32 dmaerrl; /* DMA error low(ch31~0) */ 1110fb6f739SPiotr Ziecik /* 0x30 */ 1120fb6f739SPiotr Ziecik u32 dmahrsh; /* DMA hw request status high(ch63~32) */ 1130fb6f739SPiotr Ziecik u32 dmahrsl; /* DMA hardware request status low(ch31~0) */ 114ba2eea25SIlya Yanok union { 1150fb6f739SPiotr Ziecik u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */ 116ba2eea25SIlya Yanok u32 dmagpor; /* (General purpose register on MPC8308) */ 117ba2eea25SIlya Yanok }; 1180fb6f739SPiotr Ziecik u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */ 1190fb6f739SPiotr Ziecik /* 0x40 ~ 0xff */ 1200fb6f739SPiotr Ziecik u32 reserve0[48]; /* Reserved */ 1210fb6f739SPiotr Ziecik /* 0x100 */ 1220fb6f739SPiotr Ziecik u8 dchpri[MPC_DMA_CHANNELS]; 1230fb6f739SPiotr Ziecik /* DMA channels(0~63) priority */ 1240fb6f739SPiotr Ziecik }; 1250fb6f739SPiotr Ziecik 1260fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_tcd { 1270fb6f739SPiotr Ziecik /* 0x00 */ 1280fb6f739SPiotr Ziecik u32 saddr; /* Source address */ 1290fb6f739SPiotr Ziecik 1300fb6f739SPiotr Ziecik u32 smod:5; /* Source address modulo */ 1310fb6f739SPiotr Ziecik u32 ssize:3; /* Source data transfer size */ 1320fb6f739SPiotr Ziecik u32 dmod:5; /* Destination address modulo */ 1330fb6f739SPiotr Ziecik u32 dsize:3; /* Destination data transfer size */ 1340fb6f739SPiotr Ziecik u32 soff:16; /* Signed source address offset */ 1350fb6f739SPiotr Ziecik 1360fb6f739SPiotr Ziecik /* 0x08 */ 1370fb6f739SPiotr Ziecik u32 nbytes; /* Inner "minor" byte count */ 1380fb6f739SPiotr Ziecik u32 slast; /* Last source address adjustment */ 1390fb6f739SPiotr Ziecik u32 daddr; /* Destination address */ 1400fb6f739SPiotr Ziecik 1410fb6f739SPiotr Ziecik /* 0x14 */ 1420fb6f739SPiotr Ziecik u32 citer_elink:1; /* Enable channel-to-channel linking on 1430fb6f739SPiotr Ziecik * minor loop complete 1440fb6f739SPiotr Ziecik */ 1450fb6f739SPiotr Ziecik u32 citer_linkch:6; /* Link channel for minor loop complete */ 1460fb6f739SPiotr Ziecik u32 citer:9; /* Current "major" iteration count */ 1470fb6f739SPiotr Ziecik u32 doff:16; /* Signed destination address offset */ 1480fb6f739SPiotr Ziecik 1490fb6f739SPiotr Ziecik /* 0x18 */ 1500fb6f739SPiotr Ziecik u32 dlast_sga; /* Last Destination address adjustment/scatter 1510fb6f739SPiotr Ziecik * gather address 1520fb6f739SPiotr Ziecik */ 1530fb6f739SPiotr Ziecik 1540fb6f739SPiotr Ziecik /* 0x1c */ 1550fb6f739SPiotr Ziecik u32 biter_elink:1; /* Enable channel-to-channel linking on major 1560fb6f739SPiotr Ziecik * loop complete 1570fb6f739SPiotr Ziecik */ 1580fb6f739SPiotr Ziecik u32 biter_linkch:6; 1590fb6f739SPiotr Ziecik u32 biter:9; /* Beginning "major" iteration count */ 1600fb6f739SPiotr Ziecik u32 bwc:2; /* Bandwidth control */ 1610fb6f739SPiotr Ziecik u32 major_linkch:6; /* Link channel number */ 1620fb6f739SPiotr Ziecik u32 done:1; /* Channel done */ 1630fb6f739SPiotr Ziecik u32 active:1; /* Channel active */ 1640fb6f739SPiotr Ziecik u32 major_elink:1; /* Enable channel-to-channel linking on major 1650fb6f739SPiotr Ziecik * loop complete 1660fb6f739SPiotr Ziecik */ 1670fb6f739SPiotr Ziecik u32 e_sg:1; /* Enable scatter/gather processing */ 1680fb6f739SPiotr Ziecik u32 d_req:1; /* Disable request */ 1690fb6f739SPiotr Ziecik u32 int_half:1; /* Enable an interrupt when major counter is 1700fb6f739SPiotr Ziecik * half complete 1710fb6f739SPiotr Ziecik */ 1720fb6f739SPiotr Ziecik u32 int_maj:1; /* Enable an interrupt when major iteration 1730fb6f739SPiotr Ziecik * count completes 1740fb6f739SPiotr Ziecik */ 1750fb6f739SPiotr Ziecik u32 start:1; /* Channel start */ 1760fb6f739SPiotr Ziecik }; 1770fb6f739SPiotr Ziecik 1780fb6f739SPiotr Ziecik struct mpc_dma_desc { 1790fb6f739SPiotr Ziecik struct dma_async_tx_descriptor desc; 1800fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 1810fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 1820fb6f739SPiotr Ziecik int error; 1830fb6f739SPiotr Ziecik struct list_head node; 1840fb6f739SPiotr Ziecik }; 1850fb6f739SPiotr Ziecik 1860fb6f739SPiotr Ziecik struct mpc_dma_chan { 1870fb6f739SPiotr Ziecik struct dma_chan chan; 1880fb6f739SPiotr Ziecik struct list_head free; 1890fb6f739SPiotr Ziecik struct list_head prepared; 1900fb6f739SPiotr Ziecik struct list_head queued; 1910fb6f739SPiotr Ziecik struct list_head active; 1920fb6f739SPiotr Ziecik struct list_head completed; 1930fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 1940fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 1950fb6f739SPiotr Ziecik 1960fb6f739SPiotr Ziecik /* Lock for this structure */ 1970fb6f739SPiotr Ziecik spinlock_t lock; 1980fb6f739SPiotr Ziecik }; 1990fb6f739SPiotr Ziecik 2000fb6f739SPiotr Ziecik struct mpc_dma { 2010fb6f739SPiotr Ziecik struct dma_device dma; 2020fb6f739SPiotr Ziecik struct tasklet_struct tasklet; 2030fb6f739SPiotr Ziecik struct mpc_dma_chan channels[MPC_DMA_CHANNELS]; 2040fb6f739SPiotr Ziecik struct mpc_dma_regs __iomem *regs; 2050fb6f739SPiotr Ziecik struct mpc_dma_tcd __iomem *tcd; 2060fb6f739SPiotr Ziecik int irq; 207ba2eea25SIlya Yanok int irq2; 2080fb6f739SPiotr Ziecik uint error_status; 209ba2eea25SIlya Yanok int is_mpc8308; 2100fb6f739SPiotr Ziecik 2110fb6f739SPiotr Ziecik /* Lock for error_status field in this structure */ 2120fb6f739SPiotr Ziecik spinlock_t error_status_lock; 2130fb6f739SPiotr Ziecik }; 2140fb6f739SPiotr Ziecik 2150fb6f739SPiotr Ziecik #define DRV_NAME "mpc512x_dma" 2160fb6f739SPiotr Ziecik 2170fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma_chan */ 2180fb6f739SPiotr Ziecik static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c) 2190fb6f739SPiotr Ziecik { 2200fb6f739SPiotr Ziecik return container_of(c, struct mpc_dma_chan, chan); 2210fb6f739SPiotr Ziecik } 2220fb6f739SPiotr Ziecik 2230fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma */ 2240fb6f739SPiotr Ziecik static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c) 2250fb6f739SPiotr Ziecik { 2260fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c); 2270fb6f739SPiotr Ziecik return container_of(mchan, struct mpc_dma, channels[c->chan_id]); 2280fb6f739SPiotr Ziecik } 2290fb6f739SPiotr Ziecik 2300fb6f739SPiotr Ziecik /* 2310fb6f739SPiotr Ziecik * Execute all queued DMA descriptors. 2320fb6f739SPiotr Ziecik * 2330fb6f739SPiotr Ziecik * Following requirements must be met while calling mpc_dma_execute(): 2340fb6f739SPiotr Ziecik * a) mchan->lock is acquired, 2350fb6f739SPiotr Ziecik * b) mchan->active list is empty, 2360fb6f739SPiotr Ziecik * c) mchan->queued list contains at least one entry. 2370fb6f739SPiotr Ziecik */ 2380fb6f739SPiotr Ziecik static void mpc_dma_execute(struct mpc_dma_chan *mchan) 2390fb6f739SPiotr Ziecik { 2400fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); 2410fb6f739SPiotr Ziecik struct mpc_dma_desc *first = NULL; 2420fb6f739SPiotr Ziecik struct mpc_dma_desc *prev = NULL; 2430fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 2440fb6f739SPiotr Ziecik int cid = mchan->chan.chan_id; 2450fb6f739SPiotr Ziecik 2460fb6f739SPiotr Ziecik /* Move all queued descriptors to active list */ 2470fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->queued, &mchan->active); 2480fb6f739SPiotr Ziecik 2490fb6f739SPiotr Ziecik /* Chain descriptors into one transaction */ 2500fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node) { 2510fb6f739SPiotr Ziecik if (!first) 2520fb6f739SPiotr Ziecik first = mdesc; 2530fb6f739SPiotr Ziecik 2540fb6f739SPiotr Ziecik if (!prev) { 2550fb6f739SPiotr Ziecik prev = mdesc; 2560fb6f739SPiotr Ziecik continue; 2570fb6f739SPiotr Ziecik } 2580fb6f739SPiotr Ziecik 2590fb6f739SPiotr Ziecik prev->tcd->dlast_sga = mdesc->tcd_paddr; 2600fb6f739SPiotr Ziecik prev->tcd->e_sg = 1; 2610fb6f739SPiotr Ziecik mdesc->tcd->start = 1; 2620fb6f739SPiotr Ziecik 2630fb6f739SPiotr Ziecik prev = mdesc; 2640fb6f739SPiotr Ziecik } 2650fb6f739SPiotr Ziecik 2660fb6f739SPiotr Ziecik prev->tcd->int_maj = 1; 2670fb6f739SPiotr Ziecik 2680fb6f739SPiotr Ziecik /* Send first descriptor in chain into hardware */ 2690fb6f739SPiotr Ziecik memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); 2706504cf34SIlya Yanok 2716504cf34SIlya Yanok if (first != prev) 2726504cf34SIlya Yanok mdma->tcd[cid].e_sg = 1; 2730fb6f739SPiotr Ziecik out_8(&mdma->regs->dmassrt, cid); 2740fb6f739SPiotr Ziecik } 2750fb6f739SPiotr Ziecik 2760fb6f739SPiotr Ziecik /* Handle interrupt on one half of DMA controller (32 channels) */ 2770fb6f739SPiotr Ziecik static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) 2780fb6f739SPiotr Ziecik { 2790fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 2800fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 2810fb6f739SPiotr Ziecik u32 status = is | es; 2820fb6f739SPiotr Ziecik int ch; 2830fb6f739SPiotr Ziecik 2840fb6f739SPiotr Ziecik while ((ch = fls(status) - 1) >= 0) { 2850fb6f739SPiotr Ziecik status &= ~(1 << ch); 2860fb6f739SPiotr Ziecik mchan = &mdma->channels[ch + off]; 2870fb6f739SPiotr Ziecik 2880fb6f739SPiotr Ziecik spin_lock(&mchan->lock); 2890fb6f739SPiotr Ziecik 2902862559eSIlya Yanok out_8(&mdma->regs->dmacint, ch + off); 2912862559eSIlya Yanok out_8(&mdma->regs->dmacerr, ch + off); 2922862559eSIlya Yanok 2930fb6f739SPiotr Ziecik /* Check error status */ 2940fb6f739SPiotr Ziecik if (es & (1 << ch)) 2950fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node) 2960fb6f739SPiotr Ziecik mdesc->error = -EIO; 2970fb6f739SPiotr Ziecik 2980fb6f739SPiotr Ziecik /* Execute queued descriptors */ 2990fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->active, &mchan->completed); 3000fb6f739SPiotr Ziecik if (!list_empty(&mchan->queued)) 3010fb6f739SPiotr Ziecik mpc_dma_execute(mchan); 3020fb6f739SPiotr Ziecik 3030fb6f739SPiotr Ziecik spin_unlock(&mchan->lock); 3040fb6f739SPiotr Ziecik } 3050fb6f739SPiotr Ziecik } 3060fb6f739SPiotr Ziecik 3070fb6f739SPiotr Ziecik /* Interrupt handler */ 3080fb6f739SPiotr Ziecik static irqreturn_t mpc_dma_irq(int irq, void *data) 3090fb6f739SPiotr Ziecik { 3100fb6f739SPiotr Ziecik struct mpc_dma *mdma = data; 3110fb6f739SPiotr Ziecik uint es; 3120fb6f739SPiotr Ziecik 3130fb6f739SPiotr Ziecik /* Save error status register */ 3140fb6f739SPiotr Ziecik es = in_be32(&mdma->regs->dmaes); 3150fb6f739SPiotr Ziecik spin_lock(&mdma->error_status_lock); 3160fb6f739SPiotr Ziecik if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0) 3170fb6f739SPiotr Ziecik mdma->error_status = es; 3180fb6f739SPiotr Ziecik spin_unlock(&mdma->error_status_lock); 3190fb6f739SPiotr Ziecik 3200fb6f739SPiotr Ziecik /* Handle interrupt on each channel */ 321ba2eea25SIlya Yanok if (mdma->dma.chancnt > 32) { 3220fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth), 3230fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrh), 32); 324ba2eea25SIlya Yanok } 3250fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl), 3260fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrl), 0); 3270fb6f739SPiotr Ziecik 3280fb6f739SPiotr Ziecik /* Schedule tasklet */ 3290fb6f739SPiotr Ziecik tasklet_schedule(&mdma->tasklet); 3300fb6f739SPiotr Ziecik 3310fb6f739SPiotr Ziecik return IRQ_HANDLED; 3320fb6f739SPiotr Ziecik } 3330fb6f739SPiotr Ziecik 33425985edcSLucas De Marchi /* process completed descriptors */ 335a2769913SIlya Yanok static void mpc_dma_process_completed(struct mpc_dma *mdma) 3360fb6f739SPiotr Ziecik { 3370fb6f739SPiotr Ziecik dma_cookie_t last_cookie = 0; 3380fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 3390fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 3400fb6f739SPiotr Ziecik struct dma_async_tx_descriptor *desc; 3410fb6f739SPiotr Ziecik unsigned long flags; 3420fb6f739SPiotr Ziecik LIST_HEAD(list); 3430fb6f739SPiotr Ziecik int i; 3440fb6f739SPiotr Ziecik 345a2769913SIlya Yanok for (i = 0; i < mdma->dma.chancnt; i++) { 346a2769913SIlya Yanok mchan = &mdma->channels[i]; 347a2769913SIlya Yanok 348a2769913SIlya Yanok /* Get all completed descriptors */ 349a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags); 350a2769913SIlya Yanok if (!list_empty(&mchan->completed)) 351a2769913SIlya Yanok list_splice_tail_init(&mchan->completed, &list); 352a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags); 353a2769913SIlya Yanok 354a2769913SIlya Yanok if (list_empty(&list)) 355a2769913SIlya Yanok continue; 356a2769913SIlya Yanok 357a2769913SIlya Yanok /* Execute callbacks and run dependencies */ 358a2769913SIlya Yanok list_for_each_entry(mdesc, &list, node) { 359a2769913SIlya Yanok desc = &mdesc->desc; 360a2769913SIlya Yanok 361a2769913SIlya Yanok if (desc->callback) 362a2769913SIlya Yanok desc->callback(desc->callback_param); 363a2769913SIlya Yanok 364a2769913SIlya Yanok last_cookie = desc->cookie; 365a2769913SIlya Yanok dma_run_dependencies(desc); 366a2769913SIlya Yanok } 367a2769913SIlya Yanok 368a2769913SIlya Yanok /* Free descriptors */ 369a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags); 370a2769913SIlya Yanok list_splice_tail_init(&list, &mchan->free); 3714d4e58deSRussell King - ARM Linux mchan->chan.completed_cookie = last_cookie; 372a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags); 373a2769913SIlya Yanok } 374a2769913SIlya Yanok } 375a2769913SIlya Yanok 376a2769913SIlya Yanok /* DMA Tasklet */ 377a2769913SIlya Yanok static void mpc_dma_tasklet(unsigned long data) 378a2769913SIlya Yanok { 379a2769913SIlya Yanok struct mpc_dma *mdma = (void *)data; 380a2769913SIlya Yanok unsigned long flags; 381a2769913SIlya Yanok uint es; 382a2769913SIlya Yanok 3830fb6f739SPiotr Ziecik spin_lock_irqsave(&mdma->error_status_lock, flags); 3840fb6f739SPiotr Ziecik es = mdma->error_status; 3850fb6f739SPiotr Ziecik mdma->error_status = 0; 3860fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mdma->error_status_lock, flags); 3870fb6f739SPiotr Ziecik 3880fb6f739SPiotr Ziecik /* Print nice error report */ 3890fb6f739SPiotr Ziecik if (es) { 3900fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, 3910fb6f739SPiotr Ziecik "Hardware reported following error(s) on channel %u:\n", 3920fb6f739SPiotr Ziecik MPC_DMA_DMAES_ERRCHN(es)); 3930fb6f739SPiotr Ziecik 3940fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_GPE) 3950fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Group Priority Error\n"); 3960fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_CPE) 3970fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Channel Priority Error\n"); 3980fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SAE) 3990fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Address Error\n"); 4000fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SOE) 4010fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Offset" 4020fb6f739SPiotr Ziecik " Configuration Error\n"); 4030fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DAE) 4040fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Destination Address" 4050fb6f739SPiotr Ziecik " Error\n"); 4060fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DOE) 4070fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Destination Offset" 4080fb6f739SPiotr Ziecik " Configuration Error\n"); 4090fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_NCE) 4100fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- NBytes/Citter" 4110fb6f739SPiotr Ziecik " Configuration Error\n"); 4120fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SGE) 4130fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Scatter/Gather" 4140fb6f739SPiotr Ziecik " Configuration Error\n"); 4150fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SBE) 4160fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Bus Error\n"); 4170fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DBE) 4180fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Destination Bus Error\n"); 4190fb6f739SPiotr Ziecik } 4200fb6f739SPiotr Ziecik 421a2769913SIlya Yanok mpc_dma_process_completed(mdma); 4220fb6f739SPiotr Ziecik } 4230fb6f739SPiotr Ziecik 4240fb6f739SPiotr Ziecik /* Submit descriptor to hardware */ 4250fb6f739SPiotr Ziecik static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd) 4260fb6f739SPiotr Ziecik { 4270fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan); 4280fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 4290fb6f739SPiotr Ziecik unsigned long flags; 4300fb6f739SPiotr Ziecik dma_cookie_t cookie; 4310fb6f739SPiotr Ziecik 4320fb6f739SPiotr Ziecik mdesc = container_of(txd, struct mpc_dma_desc, desc); 4330fb6f739SPiotr Ziecik 4340fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 4350fb6f739SPiotr Ziecik 4360fb6f739SPiotr Ziecik /* Move descriptor to queue */ 4370fb6f739SPiotr Ziecik list_move_tail(&mdesc->node, &mchan->queued); 4380fb6f739SPiotr Ziecik 4390fb6f739SPiotr Ziecik /* If channel is idle, execute all queued descriptors */ 4400fb6f739SPiotr Ziecik if (list_empty(&mchan->active)) 4410fb6f739SPiotr Ziecik mpc_dma_execute(mchan); 4420fb6f739SPiotr Ziecik 4430fb6f739SPiotr Ziecik /* Update cookie */ 444884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(txd); 4450fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 4460fb6f739SPiotr Ziecik 4470fb6f739SPiotr Ziecik return cookie; 4480fb6f739SPiotr Ziecik } 4490fb6f739SPiotr Ziecik 4500fb6f739SPiotr Ziecik /* Alloc channel resources */ 4510fb6f739SPiotr Ziecik static int mpc_dma_alloc_chan_resources(struct dma_chan *chan) 4520fb6f739SPiotr Ziecik { 4530fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 4540fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 4550fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc; 4560fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 4570fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 4580fb6f739SPiotr Ziecik unsigned long flags; 4590fb6f739SPiotr Ziecik LIST_HEAD(descs); 4600fb6f739SPiotr Ziecik int i; 4610fb6f739SPiotr Ziecik 4620fb6f739SPiotr Ziecik /* Alloc DMA memory for Transfer Control Descriptors */ 4630fb6f739SPiotr Ziecik tcd = dma_alloc_coherent(mdma->dma.dev, 4640fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 4650fb6f739SPiotr Ziecik &tcd_paddr, GFP_KERNEL); 4660fb6f739SPiotr Ziecik if (!tcd) 4670fb6f739SPiotr Ziecik return -ENOMEM; 4680fb6f739SPiotr Ziecik 4690fb6f739SPiotr Ziecik /* Alloc descriptors for this channel */ 4700fb6f739SPiotr Ziecik for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) { 4710fb6f739SPiotr Ziecik mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL); 4720fb6f739SPiotr Ziecik if (!mdesc) { 4730fb6f739SPiotr Ziecik dev_notice(mdma->dma.dev, "Memory allocation error. " 4740fb6f739SPiotr Ziecik "Allocated only %u descriptors\n", i); 4750fb6f739SPiotr Ziecik break; 4760fb6f739SPiotr Ziecik } 4770fb6f739SPiotr Ziecik 4780fb6f739SPiotr Ziecik dma_async_tx_descriptor_init(&mdesc->desc, chan); 4790fb6f739SPiotr Ziecik mdesc->desc.flags = DMA_CTRL_ACK; 4800fb6f739SPiotr Ziecik mdesc->desc.tx_submit = mpc_dma_tx_submit; 4810fb6f739SPiotr Ziecik 4820fb6f739SPiotr Ziecik mdesc->tcd = &tcd[i]; 4830fb6f739SPiotr Ziecik mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd)); 4840fb6f739SPiotr Ziecik 4850fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &descs); 4860fb6f739SPiotr Ziecik } 4870fb6f739SPiotr Ziecik 4880fb6f739SPiotr Ziecik /* Return error only if no descriptors were allocated */ 4890fb6f739SPiotr Ziecik if (i == 0) { 4900fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev, 4910fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 4920fb6f739SPiotr Ziecik tcd, tcd_paddr); 4930fb6f739SPiotr Ziecik return -ENOMEM; 4940fb6f739SPiotr Ziecik } 4950fb6f739SPiotr Ziecik 4960fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 4970fb6f739SPiotr Ziecik mchan->tcd = tcd; 4980fb6f739SPiotr Ziecik mchan->tcd_paddr = tcd_paddr; 4990fb6f739SPiotr Ziecik list_splice_tail_init(&descs, &mchan->free); 5000fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 5010fb6f739SPiotr Ziecik 5020fb6f739SPiotr Ziecik /* Enable Error Interrupt */ 5030fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaseei, chan->chan_id); 5040fb6f739SPiotr Ziecik 5050fb6f739SPiotr Ziecik return 0; 5060fb6f739SPiotr Ziecik } 5070fb6f739SPiotr Ziecik 5080fb6f739SPiotr Ziecik /* Free channel resources */ 5090fb6f739SPiotr Ziecik static void mpc_dma_free_chan_resources(struct dma_chan *chan) 5100fb6f739SPiotr Ziecik { 5110fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 5120fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 5130fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc, *tmp; 5140fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 5150fb6f739SPiotr Ziecik dma_addr_t tcd_paddr; 5160fb6f739SPiotr Ziecik unsigned long flags; 5170fb6f739SPiotr Ziecik LIST_HEAD(descs); 5180fb6f739SPiotr Ziecik 5190fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags); 5200fb6f739SPiotr Ziecik 5210fb6f739SPiotr Ziecik /* Channel must be idle */ 5220fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->prepared)); 5230fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->queued)); 5240fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->active)); 5250fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->completed)); 5260fb6f739SPiotr Ziecik 5270fb6f739SPiotr Ziecik /* Move data */ 5280fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->free, &descs); 5290fb6f739SPiotr Ziecik tcd = mchan->tcd; 5300fb6f739SPiotr Ziecik tcd_paddr = mchan->tcd_paddr; 5310fb6f739SPiotr Ziecik 5320fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags); 5330fb6f739SPiotr Ziecik 5340fb6f739SPiotr Ziecik /* Free DMA memory used by descriptors */ 5350fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev, 5360fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), 5370fb6f739SPiotr Ziecik tcd, tcd_paddr); 5380fb6f739SPiotr Ziecik 5390fb6f739SPiotr Ziecik /* Free descriptors */ 5400fb6f739SPiotr Ziecik list_for_each_entry_safe(mdesc, tmp, &descs, node) 5410fb6f739SPiotr Ziecik kfree(mdesc); 5420fb6f739SPiotr Ziecik 5430fb6f739SPiotr Ziecik /* Disable Error Interrupt */ 5440fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaceei, chan->chan_id); 5450fb6f739SPiotr Ziecik } 5460fb6f739SPiotr Ziecik 5470fb6f739SPiotr Ziecik /* Send all pending descriptor to hardware */ 5480fb6f739SPiotr Ziecik static void mpc_dma_issue_pending(struct dma_chan *chan) 5490fb6f739SPiotr Ziecik { 5500fb6f739SPiotr Ziecik /* 5510fb6f739SPiotr Ziecik * We are posting descriptors to the hardware as soon as 5520fb6f739SPiotr Ziecik * they are ready, so this function does nothing. 5530fb6f739SPiotr Ziecik */ 5540fb6f739SPiotr Ziecik } 5550fb6f739SPiotr Ziecik 5560fb6f739SPiotr Ziecik /* Check request completion status */ 5570fb6f739SPiotr Ziecik static enum dma_status 55807934481SLinus Walleij mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 55907934481SLinus Walleij struct dma_tx_state *txstate) 5600fb6f739SPiotr Ziecik { 561108fae84SAndy Shevchenko return dma_cookie_status(chan, cookie, txstate); 5620fb6f739SPiotr Ziecik } 5630fb6f739SPiotr Ziecik 5640fb6f739SPiotr Ziecik /* Prepare descriptor for memory to memory copy */ 5650fb6f739SPiotr Ziecik static struct dma_async_tx_descriptor * 5660fb6f739SPiotr Ziecik mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 5670fb6f739SPiotr Ziecik size_t len, unsigned long flags) 5680fb6f739SPiotr Ziecik { 569ba2eea25SIlya Yanok struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); 5700fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); 5710fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc = NULL; 5720fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd; 5730fb6f739SPiotr Ziecik unsigned long iflags; 5740fb6f739SPiotr Ziecik 5750fb6f739SPiotr Ziecik /* Get free descriptor */ 5760fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags); 5770fb6f739SPiotr Ziecik if (!list_empty(&mchan->free)) { 5780fb6f739SPiotr Ziecik mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc, 5790fb6f739SPiotr Ziecik node); 5800fb6f739SPiotr Ziecik list_del(&mdesc->node); 5810fb6f739SPiotr Ziecik } 5820fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags); 5830fb6f739SPiotr Ziecik 584a2769913SIlya Yanok if (!mdesc) { 585a2769913SIlya Yanok /* try to free completed descriptors */ 586a2769913SIlya Yanok mpc_dma_process_completed(mdma); 5870fb6f739SPiotr Ziecik return NULL; 588a2769913SIlya Yanok } 5890fb6f739SPiotr Ziecik 5900fb6f739SPiotr Ziecik mdesc->error = 0; 5910fb6f739SPiotr Ziecik tcd = mdesc->tcd; 5920fb6f739SPiotr Ziecik 5930fb6f739SPiotr Ziecik /* Prepare Transfer Control Descriptor for this transaction */ 5940fb6f739SPiotr Ziecik memset(tcd, 0, sizeof(struct mpc_dma_tcd)); 5950fb6f739SPiotr Ziecik 5960fb6f739SPiotr Ziecik if (IS_ALIGNED(src | dst | len, 32)) { 5970fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_32; 5980fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_32; 5990fb6f739SPiotr Ziecik tcd->soff = 32; 6000fb6f739SPiotr Ziecik tcd->doff = 32; 601ba2eea25SIlya Yanok } else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) { 602ba2eea25SIlya Yanok /* MPC8308 doesn't support 16 byte transfers */ 6030fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_16; 6040fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_16; 6050fb6f739SPiotr Ziecik tcd->soff = 16; 6060fb6f739SPiotr Ziecik tcd->doff = 16; 6070fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 4)) { 6080fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_4; 6090fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_4; 6100fb6f739SPiotr Ziecik tcd->soff = 4; 6110fb6f739SPiotr Ziecik tcd->doff = 4; 6120fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 2)) { 6130fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_2; 6140fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_2; 6150fb6f739SPiotr Ziecik tcd->soff = 2; 6160fb6f739SPiotr Ziecik tcd->doff = 2; 6170fb6f739SPiotr Ziecik } else { 6180fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_1; 6190fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_1; 6200fb6f739SPiotr Ziecik tcd->soff = 1; 6210fb6f739SPiotr Ziecik tcd->doff = 1; 6220fb6f739SPiotr Ziecik } 6230fb6f739SPiotr Ziecik 6240fb6f739SPiotr Ziecik tcd->saddr = src; 6250fb6f739SPiotr Ziecik tcd->daddr = dst; 6260fb6f739SPiotr Ziecik tcd->nbytes = len; 6270fb6f739SPiotr Ziecik tcd->biter = 1; 6280fb6f739SPiotr Ziecik tcd->citer = 1; 6290fb6f739SPiotr Ziecik 6300fb6f739SPiotr Ziecik /* Place descriptor in prepared list */ 6310fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags); 6320fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &mchan->prepared); 6330fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags); 6340fb6f739SPiotr Ziecik 6350fb6f739SPiotr Ziecik return &mdesc->desc; 6360fb6f739SPiotr Ziecik } 6370fb6f739SPiotr Ziecik 638463a1f8bSBill Pemberton static int mpc_dma_probe(struct platform_device *op) 6390fb6f739SPiotr Ziecik { 640b4a75c91SAnatolij Gustschin struct device_node *dn = op->dev.of_node; 6410fb6f739SPiotr Ziecik struct device *dev = &op->dev; 6420fb6f739SPiotr Ziecik struct dma_device *dma; 6430fb6f739SPiotr Ziecik struct mpc_dma *mdma; 6440fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan; 6450fb6f739SPiotr Ziecik struct resource res; 6460fb6f739SPiotr Ziecik ulong regs_start, regs_size; 6470fb6f739SPiotr Ziecik int retval, i; 6480fb6f739SPiotr Ziecik 6490fb6f739SPiotr Ziecik mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL); 6500fb6f739SPiotr Ziecik if (!mdma) { 6510fb6f739SPiotr Ziecik dev_err(dev, "Memory exhausted!\n"); 6520fb6f739SPiotr Ziecik return -ENOMEM; 6530fb6f739SPiotr Ziecik } 6540fb6f739SPiotr Ziecik 6550fb6f739SPiotr Ziecik mdma->irq = irq_of_parse_and_map(dn, 0); 6560fb6f739SPiotr Ziecik if (mdma->irq == NO_IRQ) { 6570fb6f739SPiotr Ziecik dev_err(dev, "Error mapping IRQ!\n"); 6580fb6f739SPiotr Ziecik return -EINVAL; 6590fb6f739SPiotr Ziecik } 6600fb6f739SPiotr Ziecik 661ba2eea25SIlya Yanok if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) { 662ba2eea25SIlya Yanok mdma->is_mpc8308 = 1; 663ba2eea25SIlya Yanok mdma->irq2 = irq_of_parse_and_map(dn, 1); 664ba2eea25SIlya Yanok if (mdma->irq2 == NO_IRQ) { 665ba2eea25SIlya Yanok dev_err(dev, "Error mapping IRQ!\n"); 666ba2eea25SIlya Yanok return -EINVAL; 667ba2eea25SIlya Yanok } 668ba2eea25SIlya Yanok } 669ba2eea25SIlya Yanok 6700fb6f739SPiotr Ziecik retval = of_address_to_resource(dn, 0, &res); 6710fb6f739SPiotr Ziecik if (retval) { 6720fb6f739SPiotr Ziecik dev_err(dev, "Error parsing memory region!\n"); 6730fb6f739SPiotr Ziecik return retval; 6740fb6f739SPiotr Ziecik } 6750fb6f739SPiotr Ziecik 6760fb6f739SPiotr Ziecik regs_start = res.start; 6778381fc35STobias Klauser regs_size = resource_size(&res); 6780fb6f739SPiotr Ziecik 6790fb6f739SPiotr Ziecik if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) { 6800fb6f739SPiotr Ziecik dev_err(dev, "Error requesting memory region!\n"); 6810fb6f739SPiotr Ziecik return -EBUSY; 6820fb6f739SPiotr Ziecik } 6830fb6f739SPiotr Ziecik 6840fb6f739SPiotr Ziecik mdma->regs = devm_ioremap(dev, regs_start, regs_size); 6850fb6f739SPiotr Ziecik if (!mdma->regs) { 6860fb6f739SPiotr Ziecik dev_err(dev, "Error mapping memory region!\n"); 6870fb6f739SPiotr Ziecik return -ENOMEM; 6880fb6f739SPiotr Ziecik } 6890fb6f739SPiotr Ziecik 6900fb6f739SPiotr Ziecik mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs) 6910fb6f739SPiotr Ziecik + MPC_DMA_TCD_OFFSET); 6920fb6f739SPiotr Ziecik 6930fb6f739SPiotr Ziecik retval = devm_request_irq(dev, mdma->irq, &mpc_dma_irq, 0, DRV_NAME, 6940fb6f739SPiotr Ziecik mdma); 6950fb6f739SPiotr Ziecik if (retval) { 6960fb6f739SPiotr Ziecik dev_err(dev, "Error requesting IRQ!\n"); 6970fb6f739SPiotr Ziecik return -EINVAL; 6980fb6f739SPiotr Ziecik } 6990fb6f739SPiotr Ziecik 700ba2eea25SIlya Yanok if (mdma->is_mpc8308) { 701ba2eea25SIlya Yanok retval = devm_request_irq(dev, mdma->irq2, &mpc_dma_irq, 0, 702ba2eea25SIlya Yanok DRV_NAME, mdma); 703ba2eea25SIlya Yanok if (retval) { 704ba2eea25SIlya Yanok dev_err(dev, "Error requesting IRQ2!\n"); 705ba2eea25SIlya Yanok return -EINVAL; 706ba2eea25SIlya Yanok } 707ba2eea25SIlya Yanok } 708ba2eea25SIlya Yanok 7090fb6f739SPiotr Ziecik spin_lock_init(&mdma->error_status_lock); 7100fb6f739SPiotr Ziecik 7110fb6f739SPiotr Ziecik dma = &mdma->dma; 7120fb6f739SPiotr Ziecik dma->dev = dev; 713ba2eea25SIlya Yanok if (!mdma->is_mpc8308) 7140fb6f739SPiotr Ziecik dma->chancnt = MPC_DMA_CHANNELS; 715ba2eea25SIlya Yanok else 716ba2eea25SIlya Yanok dma->chancnt = 16; /* MPC8308 DMA has only 16 channels */ 7170fb6f739SPiotr Ziecik dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources; 7180fb6f739SPiotr Ziecik dma->device_free_chan_resources = mpc_dma_free_chan_resources; 7190fb6f739SPiotr Ziecik dma->device_issue_pending = mpc_dma_issue_pending; 72007934481SLinus Walleij dma->device_tx_status = mpc_dma_tx_status; 7210fb6f739SPiotr Ziecik dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy; 7220fb6f739SPiotr Ziecik 7230fb6f739SPiotr Ziecik INIT_LIST_HEAD(&dma->channels); 7240fb6f739SPiotr Ziecik dma_cap_set(DMA_MEMCPY, dma->cap_mask); 7250fb6f739SPiotr Ziecik 7260fb6f739SPiotr Ziecik for (i = 0; i < dma->chancnt; i++) { 7270fb6f739SPiotr Ziecik mchan = &mdma->channels[i]; 7280fb6f739SPiotr Ziecik 7290fb6f739SPiotr Ziecik mchan->chan.device = dma; 730d3ee98cdSRussell King - ARM Linux dma_cookie_init(&mchan->chan); 7310fb6f739SPiotr Ziecik 7320fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->free); 7330fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->prepared); 7340fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->queued); 7350fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->active); 7360fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->completed); 7370fb6f739SPiotr Ziecik 7380fb6f739SPiotr Ziecik spin_lock_init(&mchan->lock); 7390fb6f739SPiotr Ziecik list_add_tail(&mchan->chan.device_node, &dma->channels); 7400fb6f739SPiotr Ziecik } 7410fb6f739SPiotr Ziecik 7420fb6f739SPiotr Ziecik tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma); 7430fb6f739SPiotr Ziecik 7440fb6f739SPiotr Ziecik /* 7450fb6f739SPiotr Ziecik * Configure DMA Engine: 7460fb6f739SPiotr Ziecik * - Dynamic clock, 7470fb6f739SPiotr Ziecik * - Round-robin group arbitration, 7480fb6f739SPiotr Ziecik * - Round-robin channel arbitration. 7490fb6f739SPiotr Ziecik */ 750ba2eea25SIlya Yanok if (!mdma->is_mpc8308) { 7510fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG | 7520fb6f739SPiotr Ziecik MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA); 7530fb6f739SPiotr Ziecik 7540fb6f739SPiotr Ziecik /* Disable hardware DMA requests */ 7550fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerqh, 0); 7560fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerql, 0); 7570fb6f739SPiotr Ziecik 7580fb6f739SPiotr Ziecik /* Disable error interrupts */ 7590fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeih, 0); 7600fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeil, 0); 7610fb6f739SPiotr Ziecik 7620fb6f739SPiotr Ziecik /* Clear interrupts status */ 7630fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmainth, 0xFFFFFFFF); 7640fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF); 7650fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF); 7660fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF); 7670fb6f739SPiotr Ziecik 7680fb6f739SPiotr Ziecik /* Route interrupts to IPIC */ 7690fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaihsa, 0); 7700fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmailsa, 0); 771ba2eea25SIlya Yanok } else { 772ba2eea25SIlya Yanok /* MPC8308 has 16 channels and lacks some registers */ 773ba2eea25SIlya Yanok out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA); 774ba2eea25SIlya Yanok 775ba2eea25SIlya Yanok /* enable snooping */ 776ba2eea25SIlya Yanok out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE); 777ba2eea25SIlya Yanok /* Disable error interrupts */ 778ba2eea25SIlya Yanok out_be32(&mdma->regs->dmaeeil, 0); 779ba2eea25SIlya Yanok 780ba2eea25SIlya Yanok /* Clear interrupts status */ 781ba2eea25SIlya Yanok out_be32(&mdma->regs->dmaintl, 0xFFFF); 782ba2eea25SIlya Yanok out_be32(&mdma->regs->dmaerrl, 0xFFFF); 783ba2eea25SIlya Yanok } 7840fb6f739SPiotr Ziecik 7850fb6f739SPiotr Ziecik /* Register DMA engine */ 7860fb6f739SPiotr Ziecik dev_set_drvdata(dev, mdma); 7870fb6f739SPiotr Ziecik retval = dma_async_device_register(dma); 7880fb6f739SPiotr Ziecik if (retval) { 7890fb6f739SPiotr Ziecik devm_free_irq(dev, mdma->irq, mdma); 7900fb6f739SPiotr Ziecik irq_dispose_mapping(mdma->irq); 7910fb6f739SPiotr Ziecik } 7920fb6f739SPiotr Ziecik 7930fb6f739SPiotr Ziecik return retval; 7940fb6f739SPiotr Ziecik } 7950fb6f739SPiotr Ziecik 7964bf27b8bSGreg Kroah-Hartman static int mpc_dma_remove(struct platform_device *op) 7970fb6f739SPiotr Ziecik { 7980fb6f739SPiotr Ziecik struct device *dev = &op->dev; 7990fb6f739SPiotr Ziecik struct mpc_dma *mdma = dev_get_drvdata(dev); 8000fb6f739SPiotr Ziecik 8010fb6f739SPiotr Ziecik dma_async_device_unregister(&mdma->dma); 8020fb6f739SPiotr Ziecik devm_free_irq(dev, mdma->irq, mdma); 8030fb6f739SPiotr Ziecik irq_dispose_mapping(mdma->irq); 8040fb6f739SPiotr Ziecik 8050fb6f739SPiotr Ziecik return 0; 8060fb6f739SPiotr Ziecik } 8070fb6f739SPiotr Ziecik 8080fb6f739SPiotr Ziecik static struct of_device_id mpc_dma_match[] = { 8090fb6f739SPiotr Ziecik { .compatible = "fsl,mpc5121-dma", }, 8100fb6f739SPiotr Ziecik {}, 8110fb6f739SPiotr Ziecik }; 8120fb6f739SPiotr Ziecik 81300006124SGrant Likely static struct platform_driver mpc_dma_driver = { 8140fb6f739SPiotr Ziecik .probe = mpc_dma_probe, 815a7d6e3ecSBill Pemberton .remove = mpc_dma_remove, 8160fb6f739SPiotr Ziecik .driver = { 8170fb6f739SPiotr Ziecik .name = DRV_NAME, 8180fb6f739SPiotr Ziecik .owner = THIS_MODULE, 819b4a75c91SAnatolij Gustschin .of_match_table = mpc_dma_match, 8200fb6f739SPiotr Ziecik }, 8210fb6f739SPiotr Ziecik }; 8220fb6f739SPiotr Ziecik 823c94e9105SAxel Lin module_platform_driver(mpc_dma_driver); 8240fb6f739SPiotr Ziecik 8250fb6f739SPiotr Ziecik MODULE_LICENSE("GPL"); 8260fb6f739SPiotr Ziecik MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>"); 827