19ab65affSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
20fb6f739SPiotr Ziecik /*
30fb6f739SPiotr Ziecik * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
40fb6f739SPiotr Ziecik * Copyright (C) Semihalf 2009
5ba2eea25SIlya Yanok * Copyright (C) Ilya Yanok, Emcraft Systems 2010
663da8e0dSAlexander Popov * Copyright (C) Alexander Popov, Promcontroller 2014
7899ed9ddSMario Six * Copyright (C) Mario Six, Guntermann & Drunck GmbH, 2016
80fb6f739SPiotr Ziecik *
90fb6f739SPiotr Ziecik * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
100fb6f739SPiotr Ziecik * (defines, structures and comments) was taken from MPC5121 DMA driver
110fb6f739SPiotr Ziecik * written by Hongjun Chen <hong-jun.chen@freescale.com>.
120fb6f739SPiotr Ziecik *
130fb6f739SPiotr Ziecik * Approved as OSADL project by a majority of OSADL members and funded
140fb6f739SPiotr Ziecik * by OSADL membership fees in 2009; for details see www.osadl.org.
150fb6f739SPiotr Ziecik */
160fb6f739SPiotr Ziecik
170fb6f739SPiotr Ziecik /*
18899ed9ddSMario Six * MPC512x and MPC8308 DMA driver. It supports memory to memory data transfers
19899ed9ddSMario Six * (tested using dmatest module) and data transfers between memory and
20899ed9ddSMario Six * peripheral I/O memory by means of slave scatter/gather with these
21899ed9ddSMario Six * limitations:
22899ed9ddSMario Six * - chunked transfers (described by s/g lists with more than one item) are
23899ed9ddSMario Six * refused as long as proper support for scatter/gather is missing
24899ed9ddSMario Six * - transfers on MPC8308 always start from software as this SoC does not have
25899ed9ddSMario Six * external request lines for peripheral flow control
26899ed9ddSMario Six * - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for
27899ed9ddSMario Six * MPC512x), and 32 bytes are supported, and, consequently, source
28899ed9ddSMario Six * addresses and destination addresses must be aligned accordingly;
29899ed9ddSMario Six * furthermore, for MPC512x SoCs, the transfer size must be aligned on
30899ed9ddSMario Six * (chunk size * maxburst)
310fb6f739SPiotr Ziecik */
320fb6f739SPiotr Ziecik
330fb6f739SPiotr Ziecik #include <linux/module.h>
340fb6f739SPiotr Ziecik #include <linux/dmaengine.h>
350fb6f739SPiotr Ziecik #include <linux/dma-mapping.h>
360fb6f739SPiotr Ziecik #include <linux/interrupt.h>
370fb6f739SPiotr Ziecik #include <linux/io.h>
385a0e3ad6STejun Heo #include <linux/slab.h>
39*897500c7SRob Herring #include <linux/of.h>
405af50730SRob Herring #include <linux/of_address.h>
415af50730SRob Herring #include <linux/of_irq.h>
42ec1f0c96SAlexander Popov #include <linux/of_dma.h>
43*897500c7SRob Herring #include <linux/platform_device.h>
440fb6f739SPiotr Ziecik
450fb6f739SPiotr Ziecik #include <linux/random.h>
460fb6f739SPiotr Ziecik
47d2ebfb33SRussell King - ARM Linux #include "dmaengine.h"
48d2ebfb33SRussell King - ARM Linux
490fb6f739SPiotr Ziecik /* Number of DMA Transfer descriptors allocated per channel */
500fb6f739SPiotr Ziecik #define MPC_DMA_DESCRIPTORS 64
510fb6f739SPiotr Ziecik
520fb6f739SPiotr Ziecik /* Macro definitions */
530fb6f739SPiotr Ziecik #define MPC_DMA_TCD_OFFSET 0x1000
540fb6f739SPiotr Ziecik
5578a4f036SAlexander Popov /*
5678a4f036SAlexander Popov * Maximum channel counts for individual hardware variants
5778a4f036SAlexander Popov * and the maximum channel count over all supported controllers,
5878a4f036SAlexander Popov * used for data structure size
5978a4f036SAlexander Popov */
6078a4f036SAlexander Popov #define MPC8308_DMACHAN_MAX 16
6178a4f036SAlexander Popov #define MPC512x_DMACHAN_MAX 64
6278a4f036SAlexander Popov #define MPC_DMA_CHANNELS 64
6378a4f036SAlexander Popov
640fb6f739SPiotr Ziecik /* Arbitration mode of group and channel */
650fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_EDCG (1 << 31)
660fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERGA (1 << 3)
670fb6f739SPiotr Ziecik #define MPC_DMA_DMACR_ERCA (1 << 2)
680fb6f739SPiotr Ziecik
690fb6f739SPiotr Ziecik /* Error codes */
700fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_VLD (1 << 31)
710fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_GPE (1 << 15)
720fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_CPE (1 << 14)
730fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_ERRCHN(err) \
740fb6f739SPiotr Ziecik (((err) >> 8) & 0x3f)
750fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SAE (1 << 7)
760fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SOE (1 << 6)
770fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DAE (1 << 5)
780fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DOE (1 << 4)
790fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_NCE (1 << 3)
800fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SGE (1 << 2)
810fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_SBE (1 << 1)
820fb6f739SPiotr Ziecik #define MPC_DMA_DMAES_DBE (1 << 0)
830fb6f739SPiotr Ziecik
84ba2eea25SIlya Yanok #define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6)
85ba2eea25SIlya Yanok
860fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_1 0x00
870fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_2 0x01
880fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_4 0x02
890fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_16 0x04
900fb6f739SPiotr Ziecik #define MPC_DMA_TSIZE_32 0x05
910fb6f739SPiotr Ziecik
920fb6f739SPiotr Ziecik /* MPC5121 DMA engine registers */
930fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_regs {
940fb6f739SPiotr Ziecik /* 0x00 */
950fb6f739SPiotr Ziecik u32 dmacr; /* DMA control register */
960fb6f739SPiotr Ziecik u32 dmaes; /* DMA error status */
970fb6f739SPiotr Ziecik /* 0x08 */
980fb6f739SPiotr Ziecik u32 dmaerqh; /* DMA enable request high(channels 63~32) */
990fb6f739SPiotr Ziecik u32 dmaerql; /* DMA enable request low(channels 31~0) */
1000fb6f739SPiotr Ziecik u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */
1010fb6f739SPiotr Ziecik u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */
1020fb6f739SPiotr Ziecik /* 0x18 */
1030fb6f739SPiotr Ziecik u8 dmaserq; /* DMA set enable request */
1040fb6f739SPiotr Ziecik u8 dmacerq; /* DMA clear enable request */
1050fb6f739SPiotr Ziecik u8 dmaseei; /* DMA set enable error interrupt */
1060fb6f739SPiotr Ziecik u8 dmaceei; /* DMA clear enable error interrupt */
1070fb6f739SPiotr Ziecik /* 0x1c */
1080fb6f739SPiotr Ziecik u8 dmacint; /* DMA clear interrupt request */
1090fb6f739SPiotr Ziecik u8 dmacerr; /* DMA clear error */
1100fb6f739SPiotr Ziecik u8 dmassrt; /* DMA set start bit */
1110fb6f739SPiotr Ziecik u8 dmacdne; /* DMA clear DONE status bit */
1120fb6f739SPiotr Ziecik /* 0x20 */
1130fb6f739SPiotr Ziecik u32 dmainth; /* DMA interrupt request high(ch63~32) */
1140fb6f739SPiotr Ziecik u32 dmaintl; /* DMA interrupt request low(ch31~0) */
1150fb6f739SPiotr Ziecik u32 dmaerrh; /* DMA error high(ch63~32) */
1160fb6f739SPiotr Ziecik u32 dmaerrl; /* DMA error low(ch31~0) */
1170fb6f739SPiotr Ziecik /* 0x30 */
1180fb6f739SPiotr Ziecik u32 dmahrsh; /* DMA hw request status high(ch63~32) */
1190fb6f739SPiotr Ziecik u32 dmahrsl; /* DMA hardware request status low(ch31~0) */
120ba2eea25SIlya Yanok union {
1210fb6f739SPiotr Ziecik u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
122ba2eea25SIlya Yanok u32 dmagpor; /* (General purpose register on MPC8308) */
123ba2eea25SIlya Yanok };
1240fb6f739SPiotr Ziecik u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */
1250fb6f739SPiotr Ziecik /* 0x40 ~ 0xff */
1260fb6f739SPiotr Ziecik u32 reserve0[48]; /* Reserved */
1270fb6f739SPiotr Ziecik /* 0x100 */
1280fb6f739SPiotr Ziecik u8 dchpri[MPC_DMA_CHANNELS];
1290fb6f739SPiotr Ziecik /* DMA channels(0~63) priority */
1300fb6f739SPiotr Ziecik };
1310fb6f739SPiotr Ziecik
1320fb6f739SPiotr Ziecik struct __attribute__ ((__packed__)) mpc_dma_tcd {
1330fb6f739SPiotr Ziecik /* 0x00 */
1340fb6f739SPiotr Ziecik u32 saddr; /* Source address */
1350fb6f739SPiotr Ziecik
1360fb6f739SPiotr Ziecik u32 smod:5; /* Source address modulo */
1370fb6f739SPiotr Ziecik u32 ssize:3; /* Source data transfer size */
1380fb6f739SPiotr Ziecik u32 dmod:5; /* Destination address modulo */
1390fb6f739SPiotr Ziecik u32 dsize:3; /* Destination data transfer size */
1400fb6f739SPiotr Ziecik u32 soff:16; /* Signed source address offset */
1410fb6f739SPiotr Ziecik
1420fb6f739SPiotr Ziecik /* 0x08 */
1430fb6f739SPiotr Ziecik u32 nbytes; /* Inner "minor" byte count */
1440fb6f739SPiotr Ziecik u32 slast; /* Last source address adjustment */
1450fb6f739SPiotr Ziecik u32 daddr; /* Destination address */
1460fb6f739SPiotr Ziecik
1470fb6f739SPiotr Ziecik /* 0x14 */
1480fb6f739SPiotr Ziecik u32 citer_elink:1; /* Enable channel-to-channel linking on
1490fb6f739SPiotr Ziecik * minor loop complete
1500fb6f739SPiotr Ziecik */
1510fb6f739SPiotr Ziecik u32 citer_linkch:6; /* Link channel for minor loop complete */
1520fb6f739SPiotr Ziecik u32 citer:9; /* Current "major" iteration count */
1530fb6f739SPiotr Ziecik u32 doff:16; /* Signed destination address offset */
1540fb6f739SPiotr Ziecik
1550fb6f739SPiotr Ziecik /* 0x18 */
1560fb6f739SPiotr Ziecik u32 dlast_sga; /* Last Destination address adjustment/scatter
1570fb6f739SPiotr Ziecik * gather address
1580fb6f739SPiotr Ziecik */
1590fb6f739SPiotr Ziecik
1600fb6f739SPiotr Ziecik /* 0x1c */
1610fb6f739SPiotr Ziecik u32 biter_elink:1; /* Enable channel-to-channel linking on major
1620fb6f739SPiotr Ziecik * loop complete
1630fb6f739SPiotr Ziecik */
1640fb6f739SPiotr Ziecik u32 biter_linkch:6;
1650fb6f739SPiotr Ziecik u32 biter:9; /* Beginning "major" iteration count */
1660fb6f739SPiotr Ziecik u32 bwc:2; /* Bandwidth control */
1670fb6f739SPiotr Ziecik u32 major_linkch:6; /* Link channel number */
1680fb6f739SPiotr Ziecik u32 done:1; /* Channel done */
1690fb6f739SPiotr Ziecik u32 active:1; /* Channel active */
1700fb6f739SPiotr Ziecik u32 major_elink:1; /* Enable channel-to-channel linking on major
1710fb6f739SPiotr Ziecik * loop complete
1720fb6f739SPiotr Ziecik */
1730fb6f739SPiotr Ziecik u32 e_sg:1; /* Enable scatter/gather processing */
1740fb6f739SPiotr Ziecik u32 d_req:1; /* Disable request */
1750fb6f739SPiotr Ziecik u32 int_half:1; /* Enable an interrupt when major counter is
1760fb6f739SPiotr Ziecik * half complete
1770fb6f739SPiotr Ziecik */
1780fb6f739SPiotr Ziecik u32 int_maj:1; /* Enable an interrupt when major iteration
1790fb6f739SPiotr Ziecik * count completes
1800fb6f739SPiotr Ziecik */
1810fb6f739SPiotr Ziecik u32 start:1; /* Channel start */
1820fb6f739SPiotr Ziecik };
1830fb6f739SPiotr Ziecik
1840fb6f739SPiotr Ziecik struct mpc_dma_desc {
1850fb6f739SPiotr Ziecik struct dma_async_tx_descriptor desc;
1860fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd;
1870fb6f739SPiotr Ziecik dma_addr_t tcd_paddr;
1880fb6f739SPiotr Ziecik int error;
1890fb6f739SPiotr Ziecik struct list_head node;
19063da8e0dSAlexander Popov int will_access_peripheral;
1910fb6f739SPiotr Ziecik };
1920fb6f739SPiotr Ziecik
1930fb6f739SPiotr Ziecik struct mpc_dma_chan {
1940fb6f739SPiotr Ziecik struct dma_chan chan;
1950fb6f739SPiotr Ziecik struct list_head free;
1960fb6f739SPiotr Ziecik struct list_head prepared;
1970fb6f739SPiotr Ziecik struct list_head queued;
1980fb6f739SPiotr Ziecik struct list_head active;
1990fb6f739SPiotr Ziecik struct list_head completed;
2000fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd;
2010fb6f739SPiotr Ziecik dma_addr_t tcd_paddr;
2020fb6f739SPiotr Ziecik
20363da8e0dSAlexander Popov /* Settings for access to peripheral FIFO */
20463da8e0dSAlexander Popov dma_addr_t src_per_paddr;
20563da8e0dSAlexander Popov u32 src_tcd_nunits;
206899ed9ddSMario Six u8 swidth;
20763da8e0dSAlexander Popov dma_addr_t dst_per_paddr;
20863da8e0dSAlexander Popov u32 dst_tcd_nunits;
209899ed9ddSMario Six u8 dwidth;
21063da8e0dSAlexander Popov
2110fb6f739SPiotr Ziecik /* Lock for this structure */
2120fb6f739SPiotr Ziecik spinlock_t lock;
2130fb6f739SPiotr Ziecik };
2140fb6f739SPiotr Ziecik
2150fb6f739SPiotr Ziecik struct mpc_dma {
2160fb6f739SPiotr Ziecik struct dma_device dma;
2170fb6f739SPiotr Ziecik struct tasklet_struct tasklet;
2180fb6f739SPiotr Ziecik struct mpc_dma_chan channels[MPC_DMA_CHANNELS];
2190fb6f739SPiotr Ziecik struct mpc_dma_regs __iomem *regs;
2200fb6f739SPiotr Ziecik struct mpc_dma_tcd __iomem *tcd;
2210fb6f739SPiotr Ziecik int irq;
222ba2eea25SIlya Yanok int irq2;
2230fb6f739SPiotr Ziecik uint error_status;
224ba2eea25SIlya Yanok int is_mpc8308;
2250fb6f739SPiotr Ziecik
2260fb6f739SPiotr Ziecik /* Lock for error_status field in this structure */
2270fb6f739SPiotr Ziecik spinlock_t error_status_lock;
2280fb6f739SPiotr Ziecik };
2290fb6f739SPiotr Ziecik
2300fb6f739SPiotr Ziecik #define DRV_NAME "mpc512x_dma"
2310fb6f739SPiotr Ziecik
2320fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma_chan */
dma_chan_to_mpc_dma_chan(struct dma_chan * c)2330fb6f739SPiotr Ziecik static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
2340fb6f739SPiotr Ziecik {
2350fb6f739SPiotr Ziecik return container_of(c, struct mpc_dma_chan, chan);
2360fb6f739SPiotr Ziecik }
2370fb6f739SPiotr Ziecik
2380fb6f739SPiotr Ziecik /* Convert struct dma_chan to struct mpc_dma */
dma_chan_to_mpc_dma(struct dma_chan * c)2390fb6f739SPiotr Ziecik static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
2400fb6f739SPiotr Ziecik {
2410fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
24277fc3976SMario Six
2430fb6f739SPiotr Ziecik return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
2440fb6f739SPiotr Ziecik }
2450fb6f739SPiotr Ziecik
2460fb6f739SPiotr Ziecik /*
2470fb6f739SPiotr Ziecik * Execute all queued DMA descriptors.
2480fb6f739SPiotr Ziecik *
2490fb6f739SPiotr Ziecik * Following requirements must be met while calling mpc_dma_execute():
2500fb6f739SPiotr Ziecik * a) mchan->lock is acquired,
2510fb6f739SPiotr Ziecik * b) mchan->active list is empty,
2520fb6f739SPiotr Ziecik * c) mchan->queued list contains at least one entry.
2530fb6f739SPiotr Ziecik */
mpc_dma_execute(struct mpc_dma_chan * mchan)2540fb6f739SPiotr Ziecik static void mpc_dma_execute(struct mpc_dma_chan *mchan)
2550fb6f739SPiotr Ziecik {
2560fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
2570fb6f739SPiotr Ziecik struct mpc_dma_desc *first = NULL;
2580fb6f739SPiotr Ziecik struct mpc_dma_desc *prev = NULL;
2590fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc;
2600fb6f739SPiotr Ziecik int cid = mchan->chan.chan_id;
2610fb6f739SPiotr Ziecik
26263da8e0dSAlexander Popov while (!list_empty(&mchan->queued)) {
26363da8e0dSAlexander Popov mdesc = list_first_entry(&mchan->queued,
26463da8e0dSAlexander Popov struct mpc_dma_desc, node);
26563da8e0dSAlexander Popov /*
26663da8e0dSAlexander Popov * Grab either several mem-to-mem transfer descriptors
26763da8e0dSAlexander Popov * or one peripheral transfer descriptor,
26863da8e0dSAlexander Popov * don't mix mem-to-mem and peripheral transfer descriptors
26963da8e0dSAlexander Popov * within the same 'active' list.
27063da8e0dSAlexander Popov */
27163da8e0dSAlexander Popov if (mdesc->will_access_peripheral) {
27263da8e0dSAlexander Popov if (list_empty(&mchan->active))
27363da8e0dSAlexander Popov list_move_tail(&mdesc->node, &mchan->active);
27463da8e0dSAlexander Popov break;
27563da8e0dSAlexander Popov } else {
27663da8e0dSAlexander Popov list_move_tail(&mdesc->node, &mchan->active);
27763da8e0dSAlexander Popov }
27863da8e0dSAlexander Popov }
2790fb6f739SPiotr Ziecik
2800fb6f739SPiotr Ziecik /* Chain descriptors into one transaction */
2810fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node) {
2820fb6f739SPiotr Ziecik if (!first)
2830fb6f739SPiotr Ziecik first = mdesc;
2840fb6f739SPiotr Ziecik
2850fb6f739SPiotr Ziecik if (!prev) {
2860fb6f739SPiotr Ziecik prev = mdesc;
2870fb6f739SPiotr Ziecik continue;
2880fb6f739SPiotr Ziecik }
2890fb6f739SPiotr Ziecik
2900fb6f739SPiotr Ziecik prev->tcd->dlast_sga = mdesc->tcd_paddr;
2910fb6f739SPiotr Ziecik prev->tcd->e_sg = 1;
2920fb6f739SPiotr Ziecik mdesc->tcd->start = 1;
2930fb6f739SPiotr Ziecik
2940fb6f739SPiotr Ziecik prev = mdesc;
2950fb6f739SPiotr Ziecik }
2960fb6f739SPiotr Ziecik
2970fb6f739SPiotr Ziecik prev->tcd->int_maj = 1;
2980fb6f739SPiotr Ziecik
2990fb6f739SPiotr Ziecik /* Send first descriptor in chain into hardware */
3000fb6f739SPiotr Ziecik memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
3016504cf34SIlya Yanok
3026504cf34SIlya Yanok if (first != prev)
3036504cf34SIlya Yanok mdma->tcd[cid].e_sg = 1;
30463da8e0dSAlexander Popov
30563da8e0dSAlexander Popov if (mdma->is_mpc8308) {
30663da8e0dSAlexander Popov /* MPC8308, no request lines, software initiated start */
3070fb6f739SPiotr Ziecik out_8(&mdma->regs->dmassrt, cid);
30863da8e0dSAlexander Popov } else if (first->will_access_peripheral) {
30963da8e0dSAlexander Popov /* Peripherals involved, start by external request signal */
31063da8e0dSAlexander Popov out_8(&mdma->regs->dmaserq, cid);
31163da8e0dSAlexander Popov } else {
31263da8e0dSAlexander Popov /* Memory to memory transfer, software initiated start */
31363da8e0dSAlexander Popov out_8(&mdma->regs->dmassrt, cid);
31463da8e0dSAlexander Popov }
3150fb6f739SPiotr Ziecik }
3160fb6f739SPiotr Ziecik
3170fb6f739SPiotr Ziecik /* Handle interrupt on one half of DMA controller (32 channels) */
mpc_dma_irq_process(struct mpc_dma * mdma,u32 is,u32 es,int off)3180fb6f739SPiotr Ziecik static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
3190fb6f739SPiotr Ziecik {
3200fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan;
3210fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc;
3220fb6f739SPiotr Ziecik u32 status = is | es;
3230fb6f739SPiotr Ziecik int ch;
3240fb6f739SPiotr Ziecik
3250fb6f739SPiotr Ziecik while ((ch = fls(status) - 1) >= 0) {
3260fb6f739SPiotr Ziecik status &= ~(1 << ch);
3270fb6f739SPiotr Ziecik mchan = &mdma->channels[ch + off];
3280fb6f739SPiotr Ziecik
3290fb6f739SPiotr Ziecik spin_lock(&mchan->lock);
3300fb6f739SPiotr Ziecik
3312862559eSIlya Yanok out_8(&mdma->regs->dmacint, ch + off);
3322862559eSIlya Yanok out_8(&mdma->regs->dmacerr, ch + off);
3332862559eSIlya Yanok
3340fb6f739SPiotr Ziecik /* Check error status */
3350fb6f739SPiotr Ziecik if (es & (1 << ch))
3360fb6f739SPiotr Ziecik list_for_each_entry(mdesc, &mchan->active, node)
3370fb6f739SPiotr Ziecik mdesc->error = -EIO;
3380fb6f739SPiotr Ziecik
3390fb6f739SPiotr Ziecik /* Execute queued descriptors */
3400fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->active, &mchan->completed);
3410fb6f739SPiotr Ziecik if (!list_empty(&mchan->queued))
3420fb6f739SPiotr Ziecik mpc_dma_execute(mchan);
3430fb6f739SPiotr Ziecik
3440fb6f739SPiotr Ziecik spin_unlock(&mchan->lock);
3450fb6f739SPiotr Ziecik }
3460fb6f739SPiotr Ziecik }
3470fb6f739SPiotr Ziecik
3480fb6f739SPiotr Ziecik /* Interrupt handler */
mpc_dma_irq(int irq,void * data)3490fb6f739SPiotr Ziecik static irqreturn_t mpc_dma_irq(int irq, void *data)
3500fb6f739SPiotr Ziecik {
3510fb6f739SPiotr Ziecik struct mpc_dma *mdma = data;
3520fb6f739SPiotr Ziecik uint es;
3530fb6f739SPiotr Ziecik
3540fb6f739SPiotr Ziecik /* Save error status register */
3550fb6f739SPiotr Ziecik es = in_be32(&mdma->regs->dmaes);
3560fb6f739SPiotr Ziecik spin_lock(&mdma->error_status_lock);
3570fb6f739SPiotr Ziecik if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0)
3580fb6f739SPiotr Ziecik mdma->error_status = es;
3590fb6f739SPiotr Ziecik spin_unlock(&mdma->error_status_lock);
3600fb6f739SPiotr Ziecik
3610fb6f739SPiotr Ziecik /* Handle interrupt on each channel */
362ba2eea25SIlya Yanok if (mdma->dma.chancnt > 32) {
3630fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
3640fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrh), 32);
365ba2eea25SIlya Yanok }
3660fb6f739SPiotr Ziecik mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
3670fb6f739SPiotr Ziecik in_be32(&mdma->regs->dmaerrl), 0);
3680fb6f739SPiotr Ziecik
3690fb6f739SPiotr Ziecik /* Schedule tasklet */
3700fb6f739SPiotr Ziecik tasklet_schedule(&mdma->tasklet);
3710fb6f739SPiotr Ziecik
3720fb6f739SPiotr Ziecik return IRQ_HANDLED;
3730fb6f739SPiotr Ziecik }
3740fb6f739SPiotr Ziecik
37525985edcSLucas De Marchi /* process completed descriptors */
mpc_dma_process_completed(struct mpc_dma * mdma)376a2769913SIlya Yanok static void mpc_dma_process_completed(struct mpc_dma *mdma)
3770fb6f739SPiotr Ziecik {
3780fb6f739SPiotr Ziecik dma_cookie_t last_cookie = 0;
3790fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan;
3800fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc;
3810fb6f739SPiotr Ziecik struct dma_async_tx_descriptor *desc;
3820fb6f739SPiotr Ziecik unsigned long flags;
3830fb6f739SPiotr Ziecik LIST_HEAD(list);
3840fb6f739SPiotr Ziecik int i;
3850fb6f739SPiotr Ziecik
386a2769913SIlya Yanok for (i = 0; i < mdma->dma.chancnt; i++) {
387a2769913SIlya Yanok mchan = &mdma->channels[i];
388a2769913SIlya Yanok
389a2769913SIlya Yanok /* Get all completed descriptors */
390a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags);
391a2769913SIlya Yanok if (!list_empty(&mchan->completed))
392a2769913SIlya Yanok list_splice_tail_init(&mchan->completed, &list);
393a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags);
394a2769913SIlya Yanok
395a2769913SIlya Yanok if (list_empty(&list))
396a2769913SIlya Yanok continue;
397a2769913SIlya Yanok
398a2769913SIlya Yanok /* Execute callbacks and run dependencies */
399a2769913SIlya Yanok list_for_each_entry(mdesc, &list, node) {
400a2769913SIlya Yanok desc = &mdesc->desc;
401a2769913SIlya Yanok
402ad346368SDave Jiang dmaengine_desc_get_callback_invoke(desc, NULL);
403a2769913SIlya Yanok
404a2769913SIlya Yanok last_cookie = desc->cookie;
405a2769913SIlya Yanok dma_run_dependencies(desc);
406a2769913SIlya Yanok }
407a2769913SIlya Yanok
408a2769913SIlya Yanok /* Free descriptors */
409a2769913SIlya Yanok spin_lock_irqsave(&mchan->lock, flags);
410a2769913SIlya Yanok list_splice_tail_init(&list, &mchan->free);
4114d4e58deSRussell King - ARM Linux mchan->chan.completed_cookie = last_cookie;
412a2769913SIlya Yanok spin_unlock_irqrestore(&mchan->lock, flags);
413a2769913SIlya Yanok }
414a2769913SIlya Yanok }
415a2769913SIlya Yanok
416a2769913SIlya Yanok /* DMA Tasklet */
mpc_dma_tasklet(struct tasklet_struct * t)41781259685SAllen Pais static void mpc_dma_tasklet(struct tasklet_struct *t)
418a2769913SIlya Yanok {
41981259685SAllen Pais struct mpc_dma *mdma = from_tasklet(mdma, t, tasklet);
420a2769913SIlya Yanok unsigned long flags;
421a2769913SIlya Yanok uint es;
422a2769913SIlya Yanok
4230fb6f739SPiotr Ziecik spin_lock_irqsave(&mdma->error_status_lock, flags);
4240fb6f739SPiotr Ziecik es = mdma->error_status;
4250fb6f739SPiotr Ziecik mdma->error_status = 0;
4260fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mdma->error_status_lock, flags);
4270fb6f739SPiotr Ziecik
4280fb6f739SPiotr Ziecik /* Print nice error report */
4290fb6f739SPiotr Ziecik if (es) {
4300fb6f739SPiotr Ziecik dev_err(mdma->dma.dev,
4310fb6f739SPiotr Ziecik "Hardware reported following error(s) on channel %u:\n",
4320fb6f739SPiotr Ziecik MPC_DMA_DMAES_ERRCHN(es));
4330fb6f739SPiotr Ziecik
4340fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_GPE)
4350fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Group Priority Error\n");
4360fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_CPE)
4370fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Channel Priority Error\n");
4380fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SAE)
4390fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Address Error\n");
4400fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SOE)
44177fc3976SMario Six dev_err(mdma->dma.dev, "- Source Offset Configuration Error\n");
4420fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DAE)
44377fc3976SMario Six dev_err(mdma->dma.dev, "- Destination Address Error\n");
4440fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DOE)
44577fc3976SMario Six dev_err(mdma->dma.dev, "- Destination Offset Configuration Error\n");
4460fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_NCE)
44777fc3976SMario Six dev_err(mdma->dma.dev, "- NBytes/Citter Configuration Error\n");
4480fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SGE)
44977fc3976SMario Six dev_err(mdma->dma.dev, "- Scatter/Gather Configuration Error\n");
4500fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_SBE)
4510fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Source Bus Error\n");
4520fb6f739SPiotr Ziecik if (es & MPC_DMA_DMAES_DBE)
4530fb6f739SPiotr Ziecik dev_err(mdma->dma.dev, "- Destination Bus Error\n");
4540fb6f739SPiotr Ziecik }
4550fb6f739SPiotr Ziecik
456a2769913SIlya Yanok mpc_dma_process_completed(mdma);
4570fb6f739SPiotr Ziecik }
4580fb6f739SPiotr Ziecik
4590fb6f739SPiotr Ziecik /* Submit descriptor to hardware */
mpc_dma_tx_submit(struct dma_async_tx_descriptor * txd)4600fb6f739SPiotr Ziecik static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
4610fb6f739SPiotr Ziecik {
4620fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan);
4630fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc;
4640fb6f739SPiotr Ziecik unsigned long flags;
4650fb6f739SPiotr Ziecik dma_cookie_t cookie;
4660fb6f739SPiotr Ziecik
4670fb6f739SPiotr Ziecik mdesc = container_of(txd, struct mpc_dma_desc, desc);
4680fb6f739SPiotr Ziecik
4690fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags);
4700fb6f739SPiotr Ziecik
4710fb6f739SPiotr Ziecik /* Move descriptor to queue */
4720fb6f739SPiotr Ziecik list_move_tail(&mdesc->node, &mchan->queued);
4730fb6f739SPiotr Ziecik
4740fb6f739SPiotr Ziecik /* If channel is idle, execute all queued descriptors */
4750fb6f739SPiotr Ziecik if (list_empty(&mchan->active))
4760fb6f739SPiotr Ziecik mpc_dma_execute(mchan);
4770fb6f739SPiotr Ziecik
4780fb6f739SPiotr Ziecik /* Update cookie */
479884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(txd);
4800fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags);
4810fb6f739SPiotr Ziecik
4820fb6f739SPiotr Ziecik return cookie;
4830fb6f739SPiotr Ziecik }
4840fb6f739SPiotr Ziecik
4850fb6f739SPiotr Ziecik /* Alloc channel resources */
mpc_dma_alloc_chan_resources(struct dma_chan * chan)4860fb6f739SPiotr Ziecik static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
4870fb6f739SPiotr Ziecik {
4880fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
4890fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
4900fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc;
4910fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd;
4920fb6f739SPiotr Ziecik dma_addr_t tcd_paddr;
4930fb6f739SPiotr Ziecik unsigned long flags;
4940fb6f739SPiotr Ziecik LIST_HEAD(descs);
4950fb6f739SPiotr Ziecik int i;
4960fb6f739SPiotr Ziecik
4970fb6f739SPiotr Ziecik /* Alloc DMA memory for Transfer Control Descriptors */
4980fb6f739SPiotr Ziecik tcd = dma_alloc_coherent(mdma->dma.dev,
4990fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
5000fb6f739SPiotr Ziecik &tcd_paddr, GFP_KERNEL);
5010fb6f739SPiotr Ziecik if (!tcd)
5020fb6f739SPiotr Ziecik return -ENOMEM;
5030fb6f739SPiotr Ziecik
5040fb6f739SPiotr Ziecik /* Alloc descriptors for this channel */
5050fb6f739SPiotr Ziecik for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
5060fb6f739SPiotr Ziecik mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
5070fb6f739SPiotr Ziecik if (!mdesc) {
50877fc3976SMario Six dev_notice(mdma->dma.dev,
50977fc3976SMario Six "Memory allocation error. Allocated only %u descriptors\n", i);
5100fb6f739SPiotr Ziecik break;
5110fb6f739SPiotr Ziecik }
5120fb6f739SPiotr Ziecik
5130fb6f739SPiotr Ziecik dma_async_tx_descriptor_init(&mdesc->desc, chan);
5140fb6f739SPiotr Ziecik mdesc->desc.flags = DMA_CTRL_ACK;
5150fb6f739SPiotr Ziecik mdesc->desc.tx_submit = mpc_dma_tx_submit;
5160fb6f739SPiotr Ziecik
5170fb6f739SPiotr Ziecik mdesc->tcd = &tcd[i];
5180fb6f739SPiotr Ziecik mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd));
5190fb6f739SPiotr Ziecik
5200fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &descs);
5210fb6f739SPiotr Ziecik }
5220fb6f739SPiotr Ziecik
5230fb6f739SPiotr Ziecik /* Return error only if no descriptors were allocated */
5240fb6f739SPiotr Ziecik if (i == 0) {
5250fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev,
5260fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
5270fb6f739SPiotr Ziecik tcd, tcd_paddr);
5280fb6f739SPiotr Ziecik return -ENOMEM;
5290fb6f739SPiotr Ziecik }
5300fb6f739SPiotr Ziecik
5310fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags);
5320fb6f739SPiotr Ziecik mchan->tcd = tcd;
5330fb6f739SPiotr Ziecik mchan->tcd_paddr = tcd_paddr;
5340fb6f739SPiotr Ziecik list_splice_tail_init(&descs, &mchan->free);
5350fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags);
5360fb6f739SPiotr Ziecik
5370fb6f739SPiotr Ziecik /* Enable Error Interrupt */
5380fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaseei, chan->chan_id);
5390fb6f739SPiotr Ziecik
5400fb6f739SPiotr Ziecik return 0;
5410fb6f739SPiotr Ziecik }
5420fb6f739SPiotr Ziecik
5430fb6f739SPiotr Ziecik /* Free channel resources */
mpc_dma_free_chan_resources(struct dma_chan * chan)5440fb6f739SPiotr Ziecik static void mpc_dma_free_chan_resources(struct dma_chan *chan)
5450fb6f739SPiotr Ziecik {
5460fb6f739SPiotr Ziecik struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
5470fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
5480fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc, *tmp;
5490fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd;
5500fb6f739SPiotr Ziecik dma_addr_t tcd_paddr;
5510fb6f739SPiotr Ziecik unsigned long flags;
5520fb6f739SPiotr Ziecik LIST_HEAD(descs);
5530fb6f739SPiotr Ziecik
5540fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, flags);
5550fb6f739SPiotr Ziecik
5560fb6f739SPiotr Ziecik /* Channel must be idle */
5570fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->prepared));
5580fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->queued));
5590fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->active));
5600fb6f739SPiotr Ziecik BUG_ON(!list_empty(&mchan->completed));
5610fb6f739SPiotr Ziecik
5620fb6f739SPiotr Ziecik /* Move data */
5630fb6f739SPiotr Ziecik list_splice_tail_init(&mchan->free, &descs);
5640fb6f739SPiotr Ziecik tcd = mchan->tcd;
5650fb6f739SPiotr Ziecik tcd_paddr = mchan->tcd_paddr;
5660fb6f739SPiotr Ziecik
5670fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, flags);
5680fb6f739SPiotr Ziecik
5690fb6f739SPiotr Ziecik /* Free DMA memory used by descriptors */
5700fb6f739SPiotr Ziecik dma_free_coherent(mdma->dma.dev,
5710fb6f739SPiotr Ziecik MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
5720fb6f739SPiotr Ziecik tcd, tcd_paddr);
5730fb6f739SPiotr Ziecik
5740fb6f739SPiotr Ziecik /* Free descriptors */
5750fb6f739SPiotr Ziecik list_for_each_entry_safe(mdesc, tmp, &descs, node)
5760fb6f739SPiotr Ziecik kfree(mdesc);
5770fb6f739SPiotr Ziecik
5780fb6f739SPiotr Ziecik /* Disable Error Interrupt */
5790fb6f739SPiotr Ziecik out_8(&mdma->regs->dmaceei, chan->chan_id);
5800fb6f739SPiotr Ziecik }
5810fb6f739SPiotr Ziecik
5820fb6f739SPiotr Ziecik /* Send all pending descriptor to hardware */
mpc_dma_issue_pending(struct dma_chan * chan)5830fb6f739SPiotr Ziecik static void mpc_dma_issue_pending(struct dma_chan *chan)
5840fb6f739SPiotr Ziecik {
5850fb6f739SPiotr Ziecik /*
5860fb6f739SPiotr Ziecik * We are posting descriptors to the hardware as soon as
5870fb6f739SPiotr Ziecik * they are ready, so this function does nothing.
5880fb6f739SPiotr Ziecik */
5890fb6f739SPiotr Ziecik }
5900fb6f739SPiotr Ziecik
5910fb6f739SPiotr Ziecik /* Check request completion status */
5920fb6f739SPiotr Ziecik static enum dma_status
mpc_dma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)59307934481SLinus Walleij mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
59407934481SLinus Walleij struct dma_tx_state *txstate)
5950fb6f739SPiotr Ziecik {
596108fae84SAndy Shevchenko return dma_cookie_status(chan, cookie, txstate);
5970fb6f739SPiotr Ziecik }
5980fb6f739SPiotr Ziecik
5990fb6f739SPiotr Ziecik /* Prepare descriptor for memory to memory copy */
6000fb6f739SPiotr Ziecik static struct dma_async_tx_descriptor *
mpc_dma_prep_memcpy(struct dma_chan * chan,dma_addr_t dst,dma_addr_t src,size_t len,unsigned long flags)6010fb6f739SPiotr Ziecik mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
6020fb6f739SPiotr Ziecik size_t len, unsigned long flags)
6030fb6f739SPiotr Ziecik {
604ba2eea25SIlya Yanok struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
6050fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
6060fb6f739SPiotr Ziecik struct mpc_dma_desc *mdesc = NULL;
6070fb6f739SPiotr Ziecik struct mpc_dma_tcd *tcd;
6080fb6f739SPiotr Ziecik unsigned long iflags;
6090fb6f739SPiotr Ziecik
6100fb6f739SPiotr Ziecik /* Get free descriptor */
6110fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags);
6120fb6f739SPiotr Ziecik if (!list_empty(&mchan->free)) {
6130fb6f739SPiotr Ziecik mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc,
6140fb6f739SPiotr Ziecik node);
6150fb6f739SPiotr Ziecik list_del(&mdesc->node);
6160fb6f739SPiotr Ziecik }
6170fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags);
6180fb6f739SPiotr Ziecik
619a2769913SIlya Yanok if (!mdesc) {
620a2769913SIlya Yanok /* try to free completed descriptors */
621a2769913SIlya Yanok mpc_dma_process_completed(mdma);
6220fb6f739SPiotr Ziecik return NULL;
623a2769913SIlya Yanok }
6240fb6f739SPiotr Ziecik
6250fb6f739SPiotr Ziecik mdesc->error = 0;
62663da8e0dSAlexander Popov mdesc->will_access_peripheral = 0;
6270fb6f739SPiotr Ziecik tcd = mdesc->tcd;
6280fb6f739SPiotr Ziecik
6290fb6f739SPiotr Ziecik /* Prepare Transfer Control Descriptor for this transaction */
6300fb6f739SPiotr Ziecik memset(tcd, 0, sizeof(struct mpc_dma_tcd));
6310fb6f739SPiotr Ziecik
6320fb6f739SPiotr Ziecik if (IS_ALIGNED(src | dst | len, 32)) {
6330fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_32;
6340fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_32;
6350fb6f739SPiotr Ziecik tcd->soff = 32;
6360fb6f739SPiotr Ziecik tcd->doff = 32;
637ba2eea25SIlya Yanok } else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) {
638ba2eea25SIlya Yanok /* MPC8308 doesn't support 16 byte transfers */
6390fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_16;
6400fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_16;
6410fb6f739SPiotr Ziecik tcd->soff = 16;
6420fb6f739SPiotr Ziecik tcd->doff = 16;
6430fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 4)) {
6440fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_4;
6450fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_4;
6460fb6f739SPiotr Ziecik tcd->soff = 4;
6470fb6f739SPiotr Ziecik tcd->doff = 4;
6480fb6f739SPiotr Ziecik } else if (IS_ALIGNED(src | dst | len, 2)) {
6490fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_2;
6500fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_2;
6510fb6f739SPiotr Ziecik tcd->soff = 2;
6520fb6f739SPiotr Ziecik tcd->doff = 2;
6530fb6f739SPiotr Ziecik } else {
6540fb6f739SPiotr Ziecik tcd->ssize = MPC_DMA_TSIZE_1;
6550fb6f739SPiotr Ziecik tcd->dsize = MPC_DMA_TSIZE_1;
6560fb6f739SPiotr Ziecik tcd->soff = 1;
6570fb6f739SPiotr Ziecik tcd->doff = 1;
6580fb6f739SPiotr Ziecik }
6590fb6f739SPiotr Ziecik
6600fb6f739SPiotr Ziecik tcd->saddr = src;
6610fb6f739SPiotr Ziecik tcd->daddr = dst;
6620fb6f739SPiotr Ziecik tcd->nbytes = len;
6630fb6f739SPiotr Ziecik tcd->biter = 1;
6640fb6f739SPiotr Ziecik tcd->citer = 1;
6650fb6f739SPiotr Ziecik
6660fb6f739SPiotr Ziecik /* Place descriptor in prepared list */
6670fb6f739SPiotr Ziecik spin_lock_irqsave(&mchan->lock, iflags);
6680fb6f739SPiotr Ziecik list_add_tail(&mdesc->node, &mchan->prepared);
6690fb6f739SPiotr Ziecik spin_unlock_irqrestore(&mchan->lock, iflags);
6700fb6f739SPiotr Ziecik
6710fb6f739SPiotr Ziecik return &mdesc->desc;
6720fb6f739SPiotr Ziecik }
6730fb6f739SPiotr Ziecik
buswidth_to_dmatsize(u8 buswidth)674899ed9ddSMario Six inline u8 buswidth_to_dmatsize(u8 buswidth)
675899ed9ddSMario Six {
676899ed9ddSMario Six u8 res;
677899ed9ddSMario Six
678899ed9ddSMario Six for (res = 0; buswidth > 1; buswidth /= 2)
679899ed9ddSMario Six res++;
680899ed9ddSMario Six return res;
681899ed9ddSMario Six }
682899ed9ddSMario Six
68363da8e0dSAlexander Popov static struct dma_async_tx_descriptor *
mpc_dma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)68463da8e0dSAlexander Popov mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
68563da8e0dSAlexander Popov unsigned int sg_len, enum dma_transfer_direction direction,
68663da8e0dSAlexander Popov unsigned long flags, void *context)
68763da8e0dSAlexander Popov {
68863da8e0dSAlexander Popov struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
68963da8e0dSAlexander Popov struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
69063da8e0dSAlexander Popov struct mpc_dma_desc *mdesc = NULL;
69163da8e0dSAlexander Popov dma_addr_t per_paddr;
69263da8e0dSAlexander Popov u32 tcd_nunits;
69363da8e0dSAlexander Popov struct mpc_dma_tcd *tcd;
69463da8e0dSAlexander Popov unsigned long iflags;
69563da8e0dSAlexander Popov struct scatterlist *sg;
69663da8e0dSAlexander Popov size_t len;
69763da8e0dSAlexander Popov int iter, i;
69863da8e0dSAlexander Popov
69963da8e0dSAlexander Popov /* Currently there is no proper support for scatter/gather */
70063da8e0dSAlexander Popov if (sg_len != 1)
70163da8e0dSAlexander Popov return NULL;
70263da8e0dSAlexander Popov
70363da8e0dSAlexander Popov if (!is_slave_direction(direction))
70463da8e0dSAlexander Popov return NULL;
70563da8e0dSAlexander Popov
70663da8e0dSAlexander Popov for_each_sg(sgl, sg, sg_len, i) {
70763da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags);
70863da8e0dSAlexander Popov
70963da8e0dSAlexander Popov mdesc = list_first_entry(&mchan->free,
71063da8e0dSAlexander Popov struct mpc_dma_desc, node);
71163da8e0dSAlexander Popov if (!mdesc) {
71263da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags);
71363da8e0dSAlexander Popov /* Try to free completed descriptors */
71463da8e0dSAlexander Popov mpc_dma_process_completed(mdma);
71563da8e0dSAlexander Popov return NULL;
71663da8e0dSAlexander Popov }
71763da8e0dSAlexander Popov
71863da8e0dSAlexander Popov list_del(&mdesc->node);
71963da8e0dSAlexander Popov
72063da8e0dSAlexander Popov if (direction == DMA_DEV_TO_MEM) {
72163da8e0dSAlexander Popov per_paddr = mchan->src_per_paddr;
72263da8e0dSAlexander Popov tcd_nunits = mchan->src_tcd_nunits;
72363da8e0dSAlexander Popov } else {
72463da8e0dSAlexander Popov per_paddr = mchan->dst_per_paddr;
72563da8e0dSAlexander Popov tcd_nunits = mchan->dst_tcd_nunits;
72663da8e0dSAlexander Popov }
72763da8e0dSAlexander Popov
72863da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags);
72963da8e0dSAlexander Popov
73063da8e0dSAlexander Popov if (per_paddr == 0 || tcd_nunits == 0)
73163da8e0dSAlexander Popov goto err_prep;
73263da8e0dSAlexander Popov
73363da8e0dSAlexander Popov mdesc->error = 0;
73463da8e0dSAlexander Popov mdesc->will_access_peripheral = 1;
73563da8e0dSAlexander Popov
73663da8e0dSAlexander Popov /* Prepare Transfer Control Descriptor for this transaction */
73763da8e0dSAlexander Popov tcd = mdesc->tcd;
73863da8e0dSAlexander Popov
73963da8e0dSAlexander Popov memset(tcd, 0, sizeof(struct mpc_dma_tcd));
74063da8e0dSAlexander Popov
74163da8e0dSAlexander Popov if (direction == DMA_DEV_TO_MEM) {
74263da8e0dSAlexander Popov tcd->saddr = per_paddr;
74363da8e0dSAlexander Popov tcd->daddr = sg_dma_address(sg);
744899ed9ddSMario Six
745899ed9ddSMario Six if (!IS_ALIGNED(sg_dma_address(sg), mchan->dwidth))
746899ed9ddSMario Six goto err_prep;
747899ed9ddSMario Six
74863da8e0dSAlexander Popov tcd->soff = 0;
749899ed9ddSMario Six tcd->doff = mchan->dwidth;
75063da8e0dSAlexander Popov } else {
75163da8e0dSAlexander Popov tcd->saddr = sg_dma_address(sg);
75263da8e0dSAlexander Popov tcd->daddr = per_paddr;
753899ed9ddSMario Six
754899ed9ddSMario Six if (!IS_ALIGNED(sg_dma_address(sg), mchan->swidth))
755899ed9ddSMario Six goto err_prep;
756899ed9ddSMario Six
757899ed9ddSMario Six tcd->soff = mchan->swidth;
75863da8e0dSAlexander Popov tcd->doff = 0;
75963da8e0dSAlexander Popov }
76063da8e0dSAlexander Popov
761899ed9ddSMario Six tcd->ssize = buswidth_to_dmatsize(mchan->swidth);
762899ed9ddSMario Six tcd->dsize = buswidth_to_dmatsize(mchan->dwidth);
76363da8e0dSAlexander Popov
764237ec709SMario Six if (mdma->is_mpc8308) {
765237ec709SMario Six tcd->nbytes = sg_dma_len(sg);
766899ed9ddSMario Six if (!IS_ALIGNED(tcd->nbytes, mchan->swidth))
767237ec709SMario Six goto err_prep;
768237ec709SMario Six
769237ec709SMario Six /* No major loops for MPC8303 */
770237ec709SMario Six tcd->biter = 1;
771237ec709SMario Six tcd->citer = 1;
772237ec709SMario Six } else {
77363da8e0dSAlexander Popov len = sg_dma_len(sg);
774899ed9ddSMario Six tcd->nbytes = tcd_nunits * tcd->ssize;
77563da8e0dSAlexander Popov if (!IS_ALIGNED(len, tcd->nbytes))
77663da8e0dSAlexander Popov goto err_prep;
77763da8e0dSAlexander Popov
77863da8e0dSAlexander Popov iter = len / tcd->nbytes;
77963da8e0dSAlexander Popov if (iter >= 1 << 15) {
78063da8e0dSAlexander Popov /* len is too big */
78163da8e0dSAlexander Popov goto err_prep;
78263da8e0dSAlexander Popov }
78363da8e0dSAlexander Popov /* citer_linkch contains the high bits of iter */
78463da8e0dSAlexander Popov tcd->biter = iter & 0x1ff;
78563da8e0dSAlexander Popov tcd->biter_linkch = iter >> 9;
78663da8e0dSAlexander Popov tcd->citer = tcd->biter;
78763da8e0dSAlexander Popov tcd->citer_linkch = tcd->biter_linkch;
788237ec709SMario Six }
78963da8e0dSAlexander Popov
79063da8e0dSAlexander Popov tcd->e_sg = 0;
79163da8e0dSAlexander Popov tcd->d_req = 1;
79263da8e0dSAlexander Popov
79363da8e0dSAlexander Popov /* Place descriptor in prepared list */
79463da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags);
79563da8e0dSAlexander Popov list_add_tail(&mdesc->node, &mchan->prepared);
79663da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags);
79763da8e0dSAlexander Popov }
79863da8e0dSAlexander Popov
79963da8e0dSAlexander Popov return &mdesc->desc;
80063da8e0dSAlexander Popov
80163da8e0dSAlexander Popov err_prep:
80263da8e0dSAlexander Popov /* Put the descriptor back */
80363da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, iflags);
80463da8e0dSAlexander Popov list_add_tail(&mdesc->node, &mchan->free);
80563da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, iflags);
80663da8e0dSAlexander Popov
80763da8e0dSAlexander Popov return NULL;
80863da8e0dSAlexander Popov }
80963da8e0dSAlexander Popov
is_buswidth_valid(u8 buswidth,bool is_mpc8308)810899ed9ddSMario Six inline bool is_buswidth_valid(u8 buswidth, bool is_mpc8308)
811899ed9ddSMario Six {
812899ed9ddSMario Six switch (buswidth) {
813899ed9ddSMario Six case 16:
814899ed9ddSMario Six if (is_mpc8308)
815899ed9ddSMario Six return false;
816afbd0d29SGustavo A. R. Silva break;
817899ed9ddSMario Six case 1:
818899ed9ddSMario Six case 2:
819899ed9ddSMario Six case 4:
820899ed9ddSMario Six case 32:
821899ed9ddSMario Six break;
822899ed9ddSMario Six default:
823899ed9ddSMario Six return false;
824899ed9ddSMario Six }
825899ed9ddSMario Six
826899ed9ddSMario Six return true;
827899ed9ddSMario Six }
828899ed9ddSMario Six
mpc_dma_device_config(struct dma_chan * chan,struct dma_slave_config * cfg)82995335f1fSMaxime Ripard static int mpc_dma_device_config(struct dma_chan *chan,
83095335f1fSMaxime Ripard struct dma_slave_config *cfg)
83163da8e0dSAlexander Popov {
83295335f1fSMaxime Ripard struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
833899ed9ddSMario Six struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
83463da8e0dSAlexander Popov unsigned long flags;
83563da8e0dSAlexander Popov
83663da8e0dSAlexander Popov /*
83763da8e0dSAlexander Popov * Software constraints:
838899ed9ddSMario Six * - only transfers between a peripheral device and memory are
839899ed9ddSMario Six * supported
840899ed9ddSMario Six * - transfer chunk sizes of 1, 2, 4, 16 (for MPC512x), and 32 bytes
841899ed9ddSMario Six * are supported, and, consequently, source addresses and
842899ed9ddSMario Six * destination addresses; must be aligned accordingly; furthermore,
843899ed9ddSMario Six * for MPC512x SoCs, the transfer size must be aligned on (chunk
844899ed9ddSMario Six * size * maxburst)
845899ed9ddSMario Six * - during the transfer, the RAM address is incremented by the size
846899ed9ddSMario Six * of transfer chunk
847899ed9ddSMario Six * - the peripheral port's address is constant during the transfer.
84863da8e0dSAlexander Popov */
84963da8e0dSAlexander Popov
850899ed9ddSMario Six if (!IS_ALIGNED(cfg->src_addr, cfg->src_addr_width) ||
851899ed9ddSMario Six !IS_ALIGNED(cfg->dst_addr, cfg->dst_addr_width)) {
85263da8e0dSAlexander Popov return -EINVAL;
85363da8e0dSAlexander Popov }
85463da8e0dSAlexander Popov
855899ed9ddSMario Six if (!is_buswidth_valid(cfg->src_addr_width, mdma->is_mpc8308) ||
856899ed9ddSMario Six !is_buswidth_valid(cfg->dst_addr_width, mdma->is_mpc8308))
857899ed9ddSMario Six return -EINVAL;
858899ed9ddSMario Six
85963da8e0dSAlexander Popov spin_lock_irqsave(&mchan->lock, flags);
86063da8e0dSAlexander Popov
86163da8e0dSAlexander Popov mchan->src_per_paddr = cfg->src_addr;
86263da8e0dSAlexander Popov mchan->src_tcd_nunits = cfg->src_maxburst;
863899ed9ddSMario Six mchan->swidth = cfg->src_addr_width;
86463da8e0dSAlexander Popov mchan->dst_per_paddr = cfg->dst_addr;
86563da8e0dSAlexander Popov mchan->dst_tcd_nunits = cfg->dst_maxburst;
866899ed9ddSMario Six mchan->dwidth = cfg->dst_addr_width;
86763da8e0dSAlexander Popov
86863da8e0dSAlexander Popov /* Apply defaults */
86963da8e0dSAlexander Popov if (mchan->src_tcd_nunits == 0)
87063da8e0dSAlexander Popov mchan->src_tcd_nunits = 1;
87163da8e0dSAlexander Popov if (mchan->dst_tcd_nunits == 0)
87263da8e0dSAlexander Popov mchan->dst_tcd_nunits = 1;
87363da8e0dSAlexander Popov
87463da8e0dSAlexander Popov spin_unlock_irqrestore(&mchan->lock, flags);
87563da8e0dSAlexander Popov
87663da8e0dSAlexander Popov return 0;
87763da8e0dSAlexander Popov }
87863da8e0dSAlexander Popov
mpc_dma_device_terminate_all(struct dma_chan * chan)87995335f1fSMaxime Ripard static int mpc_dma_device_terminate_all(struct dma_chan *chan)
88095335f1fSMaxime Ripard {
88195335f1fSMaxime Ripard struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
88295335f1fSMaxime Ripard struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
88395335f1fSMaxime Ripard unsigned long flags;
88495335f1fSMaxime Ripard
88595335f1fSMaxime Ripard /* Disable channel requests */
88695335f1fSMaxime Ripard spin_lock_irqsave(&mchan->lock, flags);
88795335f1fSMaxime Ripard
88895335f1fSMaxime Ripard out_8(&mdma->regs->dmacerq, chan->chan_id);
88995335f1fSMaxime Ripard list_splice_tail_init(&mchan->prepared, &mchan->free);
89095335f1fSMaxime Ripard list_splice_tail_init(&mchan->queued, &mchan->free);
89195335f1fSMaxime Ripard list_splice_tail_init(&mchan->active, &mchan->free);
89295335f1fSMaxime Ripard
89395335f1fSMaxime Ripard spin_unlock_irqrestore(&mchan->lock, flags);
89495335f1fSMaxime Ripard
89595335f1fSMaxime Ripard return 0;
89663da8e0dSAlexander Popov }
89763da8e0dSAlexander Popov
mpc_dma_probe(struct platform_device * op)898463a1f8bSBill Pemberton static int mpc_dma_probe(struct platform_device *op)
8990fb6f739SPiotr Ziecik {
900b4a75c91SAnatolij Gustschin struct device_node *dn = op->dev.of_node;
9010fb6f739SPiotr Ziecik struct device *dev = &op->dev;
9020fb6f739SPiotr Ziecik struct dma_device *dma;
9030fb6f739SPiotr Ziecik struct mpc_dma *mdma;
9040fb6f739SPiotr Ziecik struct mpc_dma_chan *mchan;
9050fb6f739SPiotr Ziecik struct resource res;
9060fb6f739SPiotr Ziecik ulong regs_start, regs_size;
9070fb6f739SPiotr Ziecik int retval, i;
9089d82faebSMaxime Ripard u8 chancnt;
9090fb6f739SPiotr Ziecik
9100fb6f739SPiotr Ziecik mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
9110fb6f739SPiotr Ziecik if (!mdma) {
912baca66f7SAlexander Popov retval = -ENOMEM;
913baca66f7SAlexander Popov goto err;
9140fb6f739SPiotr Ziecik }
9150fb6f739SPiotr Ziecik
9160fb6f739SPiotr Ziecik mdma->irq = irq_of_parse_and_map(dn, 0);
917aa570be6SMichael Ellerman if (!mdma->irq) {
9180fb6f739SPiotr Ziecik dev_err(dev, "Error mapping IRQ!\n");
919baca66f7SAlexander Popov retval = -EINVAL;
920baca66f7SAlexander Popov goto err;
9210fb6f739SPiotr Ziecik }
9220fb6f739SPiotr Ziecik
923ba2eea25SIlya Yanok if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) {
924ba2eea25SIlya Yanok mdma->is_mpc8308 = 1;
925ba2eea25SIlya Yanok mdma->irq2 = irq_of_parse_and_map(dn, 1);
926aa570be6SMichael Ellerman if (!mdma->irq2) {
927ba2eea25SIlya Yanok dev_err(dev, "Error mapping IRQ!\n");
928baca66f7SAlexander Popov retval = -EINVAL;
929baca66f7SAlexander Popov goto err_dispose1;
930ba2eea25SIlya Yanok }
931ba2eea25SIlya Yanok }
932ba2eea25SIlya Yanok
9330fb6f739SPiotr Ziecik retval = of_address_to_resource(dn, 0, &res);
9340fb6f739SPiotr Ziecik if (retval) {
9350fb6f739SPiotr Ziecik dev_err(dev, "Error parsing memory region!\n");
936baca66f7SAlexander Popov goto err_dispose2;
9370fb6f739SPiotr Ziecik }
9380fb6f739SPiotr Ziecik
9390fb6f739SPiotr Ziecik regs_start = res.start;
9408381fc35STobias Klauser regs_size = resource_size(&res);
9410fb6f739SPiotr Ziecik
9420fb6f739SPiotr Ziecik if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) {
9430fb6f739SPiotr Ziecik dev_err(dev, "Error requesting memory region!\n");
944baca66f7SAlexander Popov retval = -EBUSY;
945baca66f7SAlexander Popov goto err_dispose2;
9460fb6f739SPiotr Ziecik }
9470fb6f739SPiotr Ziecik
9480fb6f739SPiotr Ziecik mdma->regs = devm_ioremap(dev, regs_start, regs_size);
9490fb6f739SPiotr Ziecik if (!mdma->regs) {
9500fb6f739SPiotr Ziecik dev_err(dev, "Error mapping memory region!\n");
951baca66f7SAlexander Popov retval = -ENOMEM;
952baca66f7SAlexander Popov goto err_dispose2;
9530fb6f739SPiotr Ziecik }
9540fb6f739SPiotr Ziecik
9550fb6f739SPiotr Ziecik mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs)
9560fb6f739SPiotr Ziecik + MPC_DMA_TCD_OFFSET);
9570fb6f739SPiotr Ziecik
958baca66f7SAlexander Popov retval = request_irq(mdma->irq, &mpc_dma_irq, 0, DRV_NAME, mdma);
9590fb6f739SPiotr Ziecik if (retval) {
9600fb6f739SPiotr Ziecik dev_err(dev, "Error requesting IRQ!\n");
961baca66f7SAlexander Popov retval = -EINVAL;
962baca66f7SAlexander Popov goto err_dispose2;
9630fb6f739SPiotr Ziecik }
9640fb6f739SPiotr Ziecik
965ba2eea25SIlya Yanok if (mdma->is_mpc8308) {
966baca66f7SAlexander Popov retval = request_irq(mdma->irq2, &mpc_dma_irq, 0,
967ba2eea25SIlya Yanok DRV_NAME, mdma);
968ba2eea25SIlya Yanok if (retval) {
969ba2eea25SIlya Yanok dev_err(dev, "Error requesting IRQ2!\n");
970baca66f7SAlexander Popov retval = -EINVAL;
971baca66f7SAlexander Popov goto err_free1;
972ba2eea25SIlya Yanok }
973ba2eea25SIlya Yanok }
974ba2eea25SIlya Yanok
9750fb6f739SPiotr Ziecik spin_lock_init(&mdma->error_status_lock);
9760fb6f739SPiotr Ziecik
9770fb6f739SPiotr Ziecik dma = &mdma->dma;
9780fb6f739SPiotr Ziecik dma->dev = dev;
9790fb6f739SPiotr Ziecik dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
9800fb6f739SPiotr Ziecik dma->device_free_chan_resources = mpc_dma_free_chan_resources;
9810fb6f739SPiotr Ziecik dma->device_issue_pending = mpc_dma_issue_pending;
98207934481SLinus Walleij dma->device_tx_status = mpc_dma_tx_status;
9830fb6f739SPiotr Ziecik dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
98463da8e0dSAlexander Popov dma->device_prep_slave_sg = mpc_dma_prep_slave_sg;
98595335f1fSMaxime Ripard dma->device_config = mpc_dma_device_config;
98695335f1fSMaxime Ripard dma->device_terminate_all = mpc_dma_device_terminate_all;
9870fb6f739SPiotr Ziecik
9880fb6f739SPiotr Ziecik INIT_LIST_HEAD(&dma->channels);
9890fb6f739SPiotr Ziecik dma_cap_set(DMA_MEMCPY, dma->cap_mask);
99063da8e0dSAlexander Popov dma_cap_set(DMA_SLAVE, dma->cap_mask);
9910fb6f739SPiotr Ziecik
9929d82faebSMaxime Ripard if (mdma->is_mpc8308)
9939d82faebSMaxime Ripard chancnt = MPC8308_DMACHAN_MAX;
9949d82faebSMaxime Ripard else
9959d82faebSMaxime Ripard chancnt = MPC512x_DMACHAN_MAX;
9969d82faebSMaxime Ripard
9979d82faebSMaxime Ripard for (i = 0; i < chancnt; i++) {
9980fb6f739SPiotr Ziecik mchan = &mdma->channels[i];
9990fb6f739SPiotr Ziecik
10000fb6f739SPiotr Ziecik mchan->chan.device = dma;
1001d3ee98cdSRussell King - ARM Linux dma_cookie_init(&mchan->chan);
10020fb6f739SPiotr Ziecik
10030fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->free);
10040fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->prepared);
10050fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->queued);
10060fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->active);
10070fb6f739SPiotr Ziecik INIT_LIST_HEAD(&mchan->completed);
10080fb6f739SPiotr Ziecik
10090fb6f739SPiotr Ziecik spin_lock_init(&mchan->lock);
10100fb6f739SPiotr Ziecik list_add_tail(&mchan->chan.device_node, &dma->channels);
10110fb6f739SPiotr Ziecik }
10120fb6f739SPiotr Ziecik
101381259685SAllen Pais tasklet_setup(&mdma->tasklet, mpc_dma_tasklet);
10140fb6f739SPiotr Ziecik
10150fb6f739SPiotr Ziecik /*
10160fb6f739SPiotr Ziecik * Configure DMA Engine:
10170fb6f739SPiotr Ziecik * - Dynamic clock,
10180fb6f739SPiotr Ziecik * - Round-robin group arbitration,
10190fb6f739SPiotr Ziecik * - Round-robin channel arbitration.
10200fb6f739SPiotr Ziecik */
102178a4f036SAlexander Popov if (mdma->is_mpc8308) {
102278a4f036SAlexander Popov /* MPC8308 has 16 channels and lacks some registers */
102378a4f036SAlexander Popov out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA);
102478a4f036SAlexander Popov
102578a4f036SAlexander Popov /* enable snooping */
102678a4f036SAlexander Popov out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE);
102778a4f036SAlexander Popov /* Disable error interrupts */
102878a4f036SAlexander Popov out_be32(&mdma->regs->dmaeeil, 0);
102978a4f036SAlexander Popov
103078a4f036SAlexander Popov /* Clear interrupts status */
103178a4f036SAlexander Popov out_be32(&mdma->regs->dmaintl, 0xFFFF);
103278a4f036SAlexander Popov out_be32(&mdma->regs->dmaerrl, 0xFFFF);
103378a4f036SAlexander Popov } else {
10340fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
103577fc3976SMario Six MPC_DMA_DMACR_ERGA |
103677fc3976SMario Six MPC_DMA_DMACR_ERCA);
10370fb6f739SPiotr Ziecik
10380fb6f739SPiotr Ziecik /* Disable hardware DMA requests */
10390fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerqh, 0);
10400fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerql, 0);
10410fb6f739SPiotr Ziecik
10420fb6f739SPiotr Ziecik /* Disable error interrupts */
10430fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeih, 0);
10440fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaeeil, 0);
10450fb6f739SPiotr Ziecik
10460fb6f739SPiotr Ziecik /* Clear interrupts status */
10470fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
10480fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
10490fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
10500fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
10510fb6f739SPiotr Ziecik
10520fb6f739SPiotr Ziecik /* Route interrupts to IPIC */
10530fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmaihsa, 0);
10540fb6f739SPiotr Ziecik out_be32(&mdma->regs->dmailsa, 0);
1055ba2eea25SIlya Yanok }
10560fb6f739SPiotr Ziecik
10570fb6f739SPiotr Ziecik /* Register DMA engine */
10580fb6f739SPiotr Ziecik dev_set_drvdata(dev, mdma);
10590fb6f739SPiotr Ziecik retval = dma_async_device_register(dma);
1060baca66f7SAlexander Popov if (retval)
1061baca66f7SAlexander Popov goto err_free2;
10620fb6f739SPiotr Ziecik
1063ec1f0c96SAlexander Popov /* Register with OF helpers for DMA lookups (nonfatal) */
1064ec1f0c96SAlexander Popov if (dev->of_node) {
1065ec1f0c96SAlexander Popov retval = of_dma_controller_register(dev->of_node,
1066ec1f0c96SAlexander Popov of_dma_xlate_by_chan_id, mdma);
1067ec1f0c96SAlexander Popov if (retval)
1068ec1f0c96SAlexander Popov dev_warn(dev, "Could not register for OF lookup\n");
1069ec1f0c96SAlexander Popov }
1070ec1f0c96SAlexander Popov
1071ec1f0c96SAlexander Popov return 0;
1072baca66f7SAlexander Popov
1073baca66f7SAlexander Popov err_free2:
1074baca66f7SAlexander Popov if (mdma->is_mpc8308)
1075baca66f7SAlexander Popov free_irq(mdma->irq2, mdma);
1076baca66f7SAlexander Popov err_free1:
1077baca66f7SAlexander Popov free_irq(mdma->irq, mdma);
1078baca66f7SAlexander Popov err_dispose2:
1079baca66f7SAlexander Popov if (mdma->is_mpc8308)
1080baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq2);
1081baca66f7SAlexander Popov err_dispose1:
1082baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq);
1083baca66f7SAlexander Popov err:
1084baca66f7SAlexander Popov return retval;
10850fb6f739SPiotr Ziecik }
10860fb6f739SPiotr Ziecik
mpc_dma_remove(struct platform_device * op)10874bf27b8bSGreg Kroah-Hartman static int mpc_dma_remove(struct platform_device *op)
10880fb6f739SPiotr Ziecik {
10890fb6f739SPiotr Ziecik struct device *dev = &op->dev;
10900fb6f739SPiotr Ziecik struct mpc_dma *mdma = dev_get_drvdata(dev);
10910fb6f739SPiotr Ziecik
1092ec1f0c96SAlexander Popov if (dev->of_node)
1093ec1f0c96SAlexander Popov of_dma_controller_free(dev->of_node);
10940fb6f739SPiotr Ziecik dma_async_device_unregister(&mdma->dma);
1095baca66f7SAlexander Popov if (mdma->is_mpc8308) {
1096baca66f7SAlexander Popov free_irq(mdma->irq2, mdma);
1097baca66f7SAlexander Popov irq_dispose_mapping(mdma->irq2);
1098baca66f7SAlexander Popov }
1099baca66f7SAlexander Popov free_irq(mdma->irq, mdma);
11000fb6f739SPiotr Ziecik irq_dispose_mapping(mdma->irq);
1101085fedf7SVinod Koul tasklet_kill(&mdma->tasklet);
11020fb6f739SPiotr Ziecik
11030fb6f739SPiotr Ziecik return 0;
11040fb6f739SPiotr Ziecik }
11050fb6f739SPiotr Ziecik
110657c03422SFabian Frederick static const struct of_device_id mpc_dma_match[] = {
11070fb6f739SPiotr Ziecik { .compatible = "fsl,mpc5121-dma", },
110862057d33SAlexander Popov { .compatible = "fsl,mpc8308-dma", },
11090fb6f739SPiotr Ziecik {},
11100fb6f739SPiotr Ziecik };
11119ace300cSLuis de Bethencourt MODULE_DEVICE_TABLE(of, mpc_dma_match);
11120fb6f739SPiotr Ziecik
111300006124SGrant Likely static struct platform_driver mpc_dma_driver = {
11140fb6f739SPiotr Ziecik .probe = mpc_dma_probe,
1115a7d6e3ecSBill Pemberton .remove = mpc_dma_remove,
11160fb6f739SPiotr Ziecik .driver = {
11170fb6f739SPiotr Ziecik .name = DRV_NAME,
1118b4a75c91SAnatolij Gustschin .of_match_table = mpc_dma_match,
11190fb6f739SPiotr Ziecik },
11200fb6f739SPiotr Ziecik };
11210fb6f739SPiotr Ziecik
1122c94e9105SAxel Lin module_platform_driver(mpc_dma_driver);
11230fb6f739SPiotr Ziecik
11240fb6f739SPiotr Ziecik MODULE_LICENSE("GPL");
11250fb6f739SPiotr Ziecik MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");
1126