1 /* 2 * Driver For Marvell Two-channel DMA Engine 3 * 4 * Copyright: Marvell International Ltd. 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 */ 11 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/dmaengine.h> 20 #include <linux/platform_device.h> 21 #include <linux/device.h> 22 #include <mach/regs-icu.h> 23 #include <linux/platform_data/dma-mmp_tdma.h> 24 #include <linux/of_device.h> 25 26 #include "dmaengine.h" 27 28 /* 29 * Two-Channel DMA registers 30 */ 31 #define TDBCR 0x00 /* Byte Count */ 32 #define TDSAR 0x10 /* Src Addr */ 33 #define TDDAR 0x20 /* Dst Addr */ 34 #define TDNDPR 0x30 /* Next Desc */ 35 #define TDCR 0x40 /* Control */ 36 #define TDCP 0x60 /* Priority*/ 37 #define TDCDPR 0x70 /* Current Desc */ 38 #define TDIMR 0x80 /* Int Mask */ 39 #define TDISR 0xa0 /* Int Status */ 40 41 /* Two-Channel DMA Control Register */ 42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ 43 #define TDCR_SSZ_12_BITS (0x1 << 22) 44 #define TDCR_SSZ_16_BITS (0x2 << 22) 45 #define TDCR_SSZ_20_BITS (0x3 << 22) 46 #define TDCR_SSZ_24_BITS (0x4 << 22) 47 #define TDCR_SSZ_32_BITS (0x5 << 22) 48 #define TDCR_SSZ_SHIFT (0x1 << 22) 49 #define TDCR_SSZ_MASK (0x7 << 22) 50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ 51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */ 52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ 53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ 54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ 55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ 56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ 57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ 58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ 59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ 60 #define TDCR_BURSTSZ_4B (0x0 << 6) 61 #define TDCR_BURSTSZ_8B (0x1 << 6) 62 #define TDCR_BURSTSZ_16B (0x3 << 6) 63 #define TDCR_BURSTSZ_32B (0x6 << 6) 64 #define TDCR_BURSTSZ_64B (0x7 << 6) 65 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) 66 #define TDCR_BURSTSZ_128B (0x5 << 6) 67 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ 68 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ 69 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ 70 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ 71 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ 72 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ 73 #define TDCR_DSTDESCCONT (0x1 << 1) 74 #define TDCR_SRCDESTCONT (0x1 << 0) 75 76 /* Two-Channel DMA Int Mask Register */ 77 #define TDIMR_COMP (0x1 << 0) 78 79 /* Two-Channel DMA Int Status Register */ 80 #define TDISR_COMP (0x1 << 0) 81 82 /* 83 * Two-Channel DMA Descriptor Struct 84 * NOTE: desc's buf must be aligned to 16 bytes. 85 */ 86 struct mmp_tdma_desc { 87 u32 byte_cnt; 88 u32 src_addr; 89 u32 dst_addr; 90 u32 nxt_desc; 91 }; 92 93 enum mmp_tdma_type { 94 MMP_AUD_TDMA = 0, 95 PXA910_SQU, 96 }; 97 98 #define TDMA_ALIGNMENT 3 99 #define TDMA_MAX_XFER_BYTES SZ_64K 100 101 struct mmp_tdma_chan { 102 struct device *dev; 103 struct dma_chan chan; 104 struct dma_async_tx_descriptor desc; 105 struct tasklet_struct tasklet; 106 107 struct mmp_tdma_desc *desc_arr; 108 phys_addr_t desc_arr_phys; 109 int desc_num; 110 enum dma_transfer_direction dir; 111 dma_addr_t dev_addr; 112 u32 burst_sz; 113 enum dma_slave_buswidth buswidth; 114 enum dma_status status; 115 116 int idx; 117 enum mmp_tdma_type type; 118 int irq; 119 unsigned long reg_base; 120 121 size_t buf_len; 122 size_t period_len; 123 size_t pos; 124 }; 125 126 #define TDMA_CHANNEL_NUM 2 127 struct mmp_tdma_device { 128 struct device *dev; 129 void __iomem *base; 130 struct dma_device device; 131 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; 132 }; 133 134 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) 135 136 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) 137 { 138 writel(phys, tdmac->reg_base + TDNDPR); 139 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 140 tdmac->reg_base + TDCR); 141 } 142 143 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 144 { 145 /* enable irq */ 146 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 147 /* enable dma chan */ 148 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 149 tdmac->reg_base + TDCR); 150 tdmac->status = DMA_IN_PROGRESS; 151 } 152 153 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac) 154 { 155 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 156 tdmac->reg_base + TDCR); 157 158 /* disable irq */ 159 writel(0, tdmac->reg_base + TDIMR); 160 161 tdmac->status = DMA_SUCCESS; 162 } 163 164 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac) 165 { 166 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 167 tdmac->reg_base + TDCR); 168 tdmac->status = DMA_IN_PROGRESS; 169 } 170 171 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac) 172 { 173 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 174 tdmac->reg_base + TDCR); 175 tdmac->status = DMA_PAUSED; 176 } 177 178 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) 179 { 180 unsigned int tdcr; 181 182 mmp_tdma_disable_chan(tdmac); 183 184 if (tdmac->dir == DMA_MEM_TO_DEV) 185 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; 186 else if (tdmac->dir == DMA_DEV_TO_MEM) 187 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; 188 189 if (tdmac->type == MMP_AUD_TDMA) { 190 tdcr |= TDCR_PACKMOD; 191 192 switch (tdmac->burst_sz) { 193 case 4: 194 tdcr |= TDCR_BURSTSZ_4B; 195 break; 196 case 8: 197 tdcr |= TDCR_BURSTSZ_8B; 198 break; 199 case 16: 200 tdcr |= TDCR_BURSTSZ_16B; 201 break; 202 case 32: 203 tdcr |= TDCR_BURSTSZ_32B; 204 break; 205 case 64: 206 tdcr |= TDCR_BURSTSZ_64B; 207 break; 208 case 128: 209 tdcr |= TDCR_BURSTSZ_128B; 210 break; 211 default: 212 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 213 return -EINVAL; 214 } 215 216 switch (tdmac->buswidth) { 217 case DMA_SLAVE_BUSWIDTH_1_BYTE: 218 tdcr |= TDCR_SSZ_8_BITS; 219 break; 220 case DMA_SLAVE_BUSWIDTH_2_BYTES: 221 tdcr |= TDCR_SSZ_16_BITS; 222 break; 223 case DMA_SLAVE_BUSWIDTH_4_BYTES: 224 tdcr |= TDCR_SSZ_32_BITS; 225 break; 226 default: 227 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); 228 return -EINVAL; 229 } 230 } else if (tdmac->type == PXA910_SQU) { 231 tdcr |= TDCR_BURSTSZ_SQU_32B; 232 tdcr |= TDCR_SSPMOD; 233 } 234 235 writel(tdcr, tdmac->reg_base + TDCR); 236 return 0; 237 } 238 239 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) 240 { 241 u32 reg = readl(tdmac->reg_base + TDISR); 242 243 if (reg & TDISR_COMP) { 244 /* clear irq */ 245 reg &= ~TDISR_COMP; 246 writel(reg, tdmac->reg_base + TDISR); 247 248 return 0; 249 } 250 return -EAGAIN; 251 } 252 253 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) 254 { 255 struct mmp_tdma_chan *tdmac = dev_id; 256 257 if (mmp_tdma_clear_chan_irq(tdmac) == 0) { 258 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len; 259 tasklet_schedule(&tdmac->tasklet); 260 return IRQ_HANDLED; 261 } else 262 return IRQ_NONE; 263 } 264 265 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) 266 { 267 struct mmp_tdma_device *tdev = dev_id; 268 int i, ret; 269 int irq_num = 0; 270 271 for (i = 0; i < TDMA_CHANNEL_NUM; i++) { 272 struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; 273 274 ret = mmp_tdma_chan_handler(irq, tdmac); 275 if (ret == IRQ_HANDLED) 276 irq_num++; 277 } 278 279 if (irq_num) 280 return IRQ_HANDLED; 281 else 282 return IRQ_NONE; 283 } 284 285 static void dma_do_tasklet(unsigned long data) 286 { 287 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; 288 289 if (tdmac->desc.callback) 290 tdmac->desc.callback(tdmac->desc.callback_param); 291 292 } 293 294 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) 295 { 296 struct gen_pool *gpool; 297 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 298 299 gpool = sram_get_gpool("asram"); 300 if (tdmac->desc_arr) 301 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, 302 size); 303 tdmac->desc_arr = NULL; 304 305 return; 306 } 307 308 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) 309 { 310 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); 311 312 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); 313 314 return 0; 315 } 316 317 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) 318 { 319 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 320 int ret; 321 322 dma_async_tx_descriptor_init(&tdmac->desc, chan); 323 tdmac->desc.tx_submit = mmp_tdma_tx_submit; 324 325 if (tdmac->irq) { 326 ret = devm_request_irq(tdmac->dev, tdmac->irq, 327 mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac); 328 if (ret) 329 return ret; 330 } 331 return 1; 332 } 333 334 static void mmp_tdma_free_chan_resources(struct dma_chan *chan) 335 { 336 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 337 338 if (tdmac->irq) 339 devm_free_irq(tdmac->dev, tdmac->irq, tdmac); 340 mmp_tdma_free_descriptor(tdmac); 341 return; 342 } 343 344 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) 345 { 346 struct gen_pool *gpool; 347 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 348 349 gpool = sram_get_gpool("asram"); 350 if (!gpool) 351 return NULL; 352 353 tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size); 354 if (!tdmac->desc_arr) 355 return NULL; 356 357 tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool, 358 (unsigned long)tdmac->desc_arr); 359 360 return tdmac->desc_arr; 361 } 362 363 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( 364 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 365 size_t period_len, enum dma_transfer_direction direction, 366 unsigned long flags, void *context) 367 { 368 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 369 struct mmp_tdma_desc *desc; 370 int num_periods = buf_len / period_len; 371 int i = 0, buf = 0; 372 373 if (tdmac->status != DMA_SUCCESS) 374 return NULL; 375 376 if (period_len > TDMA_MAX_XFER_BYTES) { 377 dev_err(tdmac->dev, 378 "maximum period size exceeded: %d > %d\n", 379 period_len, TDMA_MAX_XFER_BYTES); 380 goto err_out; 381 } 382 383 tdmac->status = DMA_IN_PROGRESS; 384 tdmac->desc_num = num_periods; 385 desc = mmp_tdma_alloc_descriptor(tdmac); 386 if (!desc) 387 goto err_out; 388 389 while (buf < buf_len) { 390 desc = &tdmac->desc_arr[i]; 391 392 if (i + 1 == num_periods) 393 desc->nxt_desc = tdmac->desc_arr_phys; 394 else 395 desc->nxt_desc = tdmac->desc_arr_phys + 396 sizeof(*desc) * (i + 1); 397 398 if (direction == DMA_MEM_TO_DEV) { 399 desc->src_addr = dma_addr; 400 desc->dst_addr = tdmac->dev_addr; 401 } else { 402 desc->src_addr = tdmac->dev_addr; 403 desc->dst_addr = dma_addr; 404 } 405 desc->byte_cnt = period_len; 406 dma_addr += period_len; 407 buf += period_len; 408 i++; 409 } 410 411 tdmac->buf_len = buf_len; 412 tdmac->period_len = period_len; 413 tdmac->pos = 0; 414 415 return &tdmac->desc; 416 417 err_out: 418 tdmac->status = DMA_ERROR; 419 return NULL; 420 } 421 422 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 423 unsigned long arg) 424 { 425 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 426 struct dma_slave_config *dmaengine_cfg = (void *)arg; 427 int ret = 0; 428 429 switch (cmd) { 430 case DMA_TERMINATE_ALL: 431 mmp_tdma_disable_chan(tdmac); 432 break; 433 case DMA_PAUSE: 434 mmp_tdma_pause_chan(tdmac); 435 break; 436 case DMA_RESUME: 437 mmp_tdma_resume_chan(tdmac); 438 break; 439 case DMA_SLAVE_CONFIG: 440 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 441 tdmac->dev_addr = dmaengine_cfg->src_addr; 442 tdmac->burst_sz = dmaengine_cfg->src_maxburst; 443 tdmac->buswidth = dmaengine_cfg->src_addr_width; 444 } else { 445 tdmac->dev_addr = dmaengine_cfg->dst_addr; 446 tdmac->burst_sz = dmaengine_cfg->dst_maxburst; 447 tdmac->buswidth = dmaengine_cfg->dst_addr_width; 448 } 449 tdmac->dir = dmaengine_cfg->direction; 450 return mmp_tdma_config_chan(tdmac); 451 default: 452 ret = -ENOSYS; 453 } 454 455 return ret; 456 } 457 458 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, 459 dma_cookie_t cookie, struct dma_tx_state *txstate) 460 { 461 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 462 463 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 464 tdmac->buf_len - tdmac->pos); 465 466 return tdmac->status; 467 } 468 469 static void mmp_tdma_issue_pending(struct dma_chan *chan) 470 { 471 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 472 473 mmp_tdma_enable_chan(tdmac); 474 } 475 476 static int mmp_tdma_remove(struct platform_device *pdev) 477 { 478 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); 479 480 dma_async_device_unregister(&tdev->device); 481 return 0; 482 } 483 484 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, 485 int idx, int irq, int type) 486 { 487 struct mmp_tdma_chan *tdmac; 488 489 if (idx >= TDMA_CHANNEL_NUM) { 490 dev_err(tdev->dev, "too many channels for device!\n"); 491 return -EINVAL; 492 } 493 494 /* alloc channel */ 495 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); 496 if (!tdmac) { 497 dev_err(tdev->dev, "no free memory for DMA channels!\n"); 498 return -ENOMEM; 499 } 500 if (irq) 501 tdmac->irq = irq; 502 tdmac->dev = tdev->dev; 503 tdmac->chan.device = &tdev->device; 504 tdmac->idx = idx; 505 tdmac->type = type; 506 tdmac->reg_base = (unsigned long)tdev->base + idx * 4; 507 tdmac->status = DMA_SUCCESS; 508 tdev->tdmac[tdmac->idx] = tdmac; 509 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); 510 511 /* add the channel to tdma_chan list */ 512 list_add_tail(&tdmac->chan.device_node, 513 &tdev->device.channels); 514 return 0; 515 } 516 517 static struct of_device_id mmp_tdma_dt_ids[] = { 518 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, 519 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, 520 {} 521 }; 522 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); 523 524 static int mmp_tdma_probe(struct platform_device *pdev) 525 { 526 enum mmp_tdma_type type; 527 const struct of_device_id *of_id; 528 struct mmp_tdma_device *tdev; 529 struct resource *iores; 530 int i, ret; 531 int irq = 0, irq_num = 0; 532 int chan_num = TDMA_CHANNEL_NUM; 533 534 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); 535 if (of_id) 536 type = (enum mmp_tdma_type) of_id->data; 537 else 538 type = platform_get_device_id(pdev)->driver_data; 539 540 /* always have couple channels */ 541 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); 542 if (!tdev) 543 return -ENOMEM; 544 545 tdev->dev = &pdev->dev; 546 547 for (i = 0; i < chan_num; i++) { 548 if (platform_get_irq(pdev, i) > 0) 549 irq_num++; 550 } 551 552 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 553 tdev->base = devm_ioremap_resource(&pdev->dev, iores); 554 if (IS_ERR(tdev->base)) 555 return PTR_ERR(tdev->base); 556 557 INIT_LIST_HEAD(&tdev->device.channels); 558 559 if (irq_num != chan_num) { 560 irq = platform_get_irq(pdev, 0); 561 ret = devm_request_irq(&pdev->dev, irq, 562 mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev); 563 if (ret) 564 return ret; 565 } 566 567 /* initialize channel parameters */ 568 for (i = 0; i < chan_num; i++) { 569 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); 570 ret = mmp_tdma_chan_init(tdev, i, irq, type); 571 if (ret) 572 return ret; 573 } 574 575 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); 576 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); 577 tdev->device.dev = &pdev->dev; 578 tdev->device.device_alloc_chan_resources = 579 mmp_tdma_alloc_chan_resources; 580 tdev->device.device_free_chan_resources = 581 mmp_tdma_free_chan_resources; 582 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; 583 tdev->device.device_tx_status = mmp_tdma_tx_status; 584 tdev->device.device_issue_pending = mmp_tdma_issue_pending; 585 tdev->device.device_control = mmp_tdma_control; 586 tdev->device.copy_align = TDMA_ALIGNMENT; 587 588 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 589 platform_set_drvdata(pdev, tdev); 590 591 ret = dma_async_device_register(&tdev->device); 592 if (ret) { 593 dev_err(tdev->device.dev, "unable to register\n"); 594 return ret; 595 } 596 597 dev_info(tdev->device.dev, "initialized\n"); 598 return 0; 599 } 600 601 static const struct platform_device_id mmp_tdma_id_table[] = { 602 { "mmp-adma", MMP_AUD_TDMA }, 603 { "pxa910-squ", PXA910_SQU }, 604 { }, 605 }; 606 607 static struct platform_driver mmp_tdma_driver = { 608 .driver = { 609 .name = "mmp-tdma", 610 .owner = THIS_MODULE, 611 .of_match_table = mmp_tdma_dt_ids, 612 }, 613 .id_table = mmp_tdma_id_table, 614 .probe = mmp_tdma_probe, 615 .remove = mmp_tdma_remove, 616 }; 617 618 module_platform_driver(mmp_tdma_driver); 619 620 MODULE_LICENSE("GPL"); 621 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); 622 MODULE_ALIAS("platform:mmp-tdma"); 623 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 624 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); 625