1 /* 2 * Driver For Marvell Two-channel DMA Engine 3 * 4 * Copyright: Marvell International Ltd. 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 */ 11 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/dmaengine.h> 20 #include <linux/platform_device.h> 21 #include <linux/device.h> 22 #include <mach/regs-icu.h> 23 #include <linux/platform_data/dma-mmp_tdma.h> 24 #include <linux/of_device.h> 25 26 #include "dmaengine.h" 27 28 /* 29 * Two-Channel DMA registers 30 */ 31 #define TDBCR 0x00 /* Byte Count */ 32 #define TDSAR 0x10 /* Src Addr */ 33 #define TDDAR 0x20 /* Dst Addr */ 34 #define TDNDPR 0x30 /* Next Desc */ 35 #define TDCR 0x40 /* Control */ 36 #define TDCP 0x60 /* Priority*/ 37 #define TDCDPR 0x70 /* Current Desc */ 38 #define TDIMR 0x80 /* Int Mask */ 39 #define TDISR 0xa0 /* Int Status */ 40 41 /* Two-Channel DMA Control Register */ 42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ 43 #define TDCR_SSZ_12_BITS (0x1 << 22) 44 #define TDCR_SSZ_16_BITS (0x2 << 22) 45 #define TDCR_SSZ_20_BITS (0x3 << 22) 46 #define TDCR_SSZ_24_BITS (0x4 << 22) 47 #define TDCR_SSZ_32_BITS (0x5 << 22) 48 #define TDCR_SSZ_SHIFT (0x1 << 22) 49 #define TDCR_SSZ_MASK (0x7 << 22) 50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ 51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */ 52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ 53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ 54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ 55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ 56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ 57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ 58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ 59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ 60 #define TDCR_BURSTSZ_4B (0x0 << 6) 61 #define TDCR_BURSTSZ_8B (0x1 << 6) 62 #define TDCR_BURSTSZ_16B (0x3 << 6) 63 #define TDCR_BURSTSZ_32B (0x6 << 6) 64 #define TDCR_BURSTSZ_64B (0x7 << 6) 65 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) 66 #define TDCR_BURSTSZ_128B (0x5 << 6) 67 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ 68 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ 69 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ 70 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ 71 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ 72 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ 73 #define TDCR_DSTDESCCONT (0x1 << 1) 74 #define TDCR_SRCDESTCONT (0x1 << 0) 75 76 /* Two-Channel DMA Int Mask Register */ 77 #define TDIMR_COMP (0x1 << 0) 78 79 /* Two-Channel DMA Int Status Register */ 80 #define TDISR_COMP (0x1 << 0) 81 82 /* 83 * Two-Channel DMA Descriptor Struct 84 * NOTE: desc's buf must be aligned to 16 bytes. 85 */ 86 struct mmp_tdma_desc { 87 u32 byte_cnt; 88 u32 src_addr; 89 u32 dst_addr; 90 u32 nxt_desc; 91 }; 92 93 enum mmp_tdma_type { 94 MMP_AUD_TDMA = 0, 95 PXA910_SQU, 96 }; 97 98 #define TDMA_ALIGNMENT 3 99 #define TDMA_MAX_XFER_BYTES SZ_64K 100 101 struct mmp_tdma_chan { 102 struct device *dev; 103 struct dma_chan chan; 104 struct dma_async_tx_descriptor desc; 105 struct tasklet_struct tasklet; 106 107 struct mmp_tdma_desc *desc_arr; 108 phys_addr_t desc_arr_phys; 109 int desc_num; 110 enum dma_transfer_direction dir; 111 dma_addr_t dev_addr; 112 u32 burst_sz; 113 enum dma_slave_buswidth buswidth; 114 enum dma_status status; 115 116 int idx; 117 enum mmp_tdma_type type; 118 int irq; 119 unsigned long reg_base; 120 121 size_t buf_len; 122 size_t period_len; 123 size_t pos; 124 }; 125 126 #define TDMA_CHANNEL_NUM 2 127 struct mmp_tdma_device { 128 struct device *dev; 129 void __iomem *base; 130 struct dma_device device; 131 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; 132 }; 133 134 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) 135 136 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) 137 { 138 writel(phys, tdmac->reg_base + TDNDPR); 139 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 140 tdmac->reg_base + TDCR); 141 } 142 143 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 144 { 145 /* enable irq */ 146 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 147 /* enable dma chan */ 148 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 149 tdmac->reg_base + TDCR); 150 tdmac->status = DMA_IN_PROGRESS; 151 } 152 153 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac) 154 { 155 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 156 tdmac->reg_base + TDCR); 157 tdmac->status = DMA_SUCCESS; 158 } 159 160 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac) 161 { 162 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 163 tdmac->reg_base + TDCR); 164 tdmac->status = DMA_IN_PROGRESS; 165 } 166 167 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac) 168 { 169 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 170 tdmac->reg_base + TDCR); 171 tdmac->status = DMA_PAUSED; 172 } 173 174 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) 175 { 176 unsigned int tdcr; 177 178 mmp_tdma_disable_chan(tdmac); 179 180 if (tdmac->dir == DMA_MEM_TO_DEV) 181 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; 182 else if (tdmac->dir == DMA_DEV_TO_MEM) 183 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; 184 185 if (tdmac->type == MMP_AUD_TDMA) { 186 tdcr |= TDCR_PACKMOD; 187 188 switch (tdmac->burst_sz) { 189 case 4: 190 tdcr |= TDCR_BURSTSZ_4B; 191 break; 192 case 8: 193 tdcr |= TDCR_BURSTSZ_8B; 194 break; 195 case 16: 196 tdcr |= TDCR_BURSTSZ_16B; 197 break; 198 case 32: 199 tdcr |= TDCR_BURSTSZ_32B; 200 break; 201 case 64: 202 tdcr |= TDCR_BURSTSZ_64B; 203 break; 204 case 128: 205 tdcr |= TDCR_BURSTSZ_128B; 206 break; 207 default: 208 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 209 return -EINVAL; 210 } 211 212 switch (tdmac->buswidth) { 213 case DMA_SLAVE_BUSWIDTH_1_BYTE: 214 tdcr |= TDCR_SSZ_8_BITS; 215 break; 216 case DMA_SLAVE_BUSWIDTH_2_BYTES: 217 tdcr |= TDCR_SSZ_16_BITS; 218 break; 219 case DMA_SLAVE_BUSWIDTH_4_BYTES: 220 tdcr |= TDCR_SSZ_32_BITS; 221 break; 222 default: 223 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); 224 return -EINVAL; 225 } 226 } else if (tdmac->type == PXA910_SQU) { 227 tdcr |= TDCR_BURSTSZ_SQU_32B; 228 tdcr |= TDCR_SSPMOD; 229 } 230 231 writel(tdcr, tdmac->reg_base + TDCR); 232 return 0; 233 } 234 235 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) 236 { 237 u32 reg = readl(tdmac->reg_base + TDISR); 238 239 if (reg & TDISR_COMP) { 240 /* clear irq */ 241 reg &= ~TDISR_COMP; 242 writel(reg, tdmac->reg_base + TDISR); 243 244 return 0; 245 } 246 return -EAGAIN; 247 } 248 249 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) 250 { 251 struct mmp_tdma_chan *tdmac = dev_id; 252 253 if (mmp_tdma_clear_chan_irq(tdmac) == 0) { 254 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len; 255 tasklet_schedule(&tdmac->tasklet); 256 return IRQ_HANDLED; 257 } else 258 return IRQ_NONE; 259 } 260 261 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) 262 { 263 struct mmp_tdma_device *tdev = dev_id; 264 int i, ret; 265 int irq_num = 0; 266 267 for (i = 0; i < TDMA_CHANNEL_NUM; i++) { 268 struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; 269 270 ret = mmp_tdma_chan_handler(irq, tdmac); 271 if (ret == IRQ_HANDLED) 272 irq_num++; 273 } 274 275 if (irq_num) 276 return IRQ_HANDLED; 277 else 278 return IRQ_NONE; 279 } 280 281 static void dma_do_tasklet(unsigned long data) 282 { 283 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; 284 285 if (tdmac->desc.callback) 286 tdmac->desc.callback(tdmac->desc.callback_param); 287 288 } 289 290 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) 291 { 292 struct gen_pool *gpool; 293 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 294 295 gpool = sram_get_gpool("asram"); 296 if (tdmac->desc_arr) 297 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, 298 size); 299 tdmac->desc_arr = NULL; 300 301 return; 302 } 303 304 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) 305 { 306 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); 307 308 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); 309 310 return 0; 311 } 312 313 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) 314 { 315 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 316 int ret; 317 318 dma_async_tx_descriptor_init(&tdmac->desc, chan); 319 tdmac->desc.tx_submit = mmp_tdma_tx_submit; 320 321 if (tdmac->irq) { 322 ret = devm_request_irq(tdmac->dev, tdmac->irq, 323 mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac); 324 if (ret) 325 return ret; 326 } 327 return 1; 328 } 329 330 static void mmp_tdma_free_chan_resources(struct dma_chan *chan) 331 { 332 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 333 334 if (tdmac->irq) 335 devm_free_irq(tdmac->dev, tdmac->irq, tdmac); 336 mmp_tdma_free_descriptor(tdmac); 337 return; 338 } 339 340 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) 341 { 342 struct gen_pool *gpool; 343 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 344 345 gpool = sram_get_gpool("asram"); 346 if (!gpool) 347 return NULL; 348 349 tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size); 350 if (!tdmac->desc_arr) 351 return NULL; 352 353 tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool, 354 (unsigned long)tdmac->desc_arr); 355 356 return tdmac->desc_arr; 357 } 358 359 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( 360 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 361 size_t period_len, enum dma_transfer_direction direction, 362 unsigned long flags, void *context) 363 { 364 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 365 struct mmp_tdma_desc *desc; 366 int num_periods = buf_len / period_len; 367 int i = 0, buf = 0; 368 369 if (tdmac->status != DMA_SUCCESS) 370 return NULL; 371 372 if (period_len > TDMA_MAX_XFER_BYTES) { 373 dev_err(tdmac->dev, 374 "maximum period size exceeded: %d > %d\n", 375 period_len, TDMA_MAX_XFER_BYTES); 376 goto err_out; 377 } 378 379 tdmac->status = DMA_IN_PROGRESS; 380 tdmac->desc_num = num_periods; 381 desc = mmp_tdma_alloc_descriptor(tdmac); 382 if (!desc) 383 goto err_out; 384 385 while (buf < buf_len) { 386 desc = &tdmac->desc_arr[i]; 387 388 if (i + 1 == num_periods) 389 desc->nxt_desc = tdmac->desc_arr_phys; 390 else 391 desc->nxt_desc = tdmac->desc_arr_phys + 392 sizeof(*desc) * (i + 1); 393 394 if (direction == DMA_MEM_TO_DEV) { 395 desc->src_addr = dma_addr; 396 desc->dst_addr = tdmac->dev_addr; 397 } else { 398 desc->src_addr = tdmac->dev_addr; 399 desc->dst_addr = dma_addr; 400 } 401 desc->byte_cnt = period_len; 402 dma_addr += period_len; 403 buf += period_len; 404 i++; 405 } 406 407 tdmac->buf_len = buf_len; 408 tdmac->period_len = period_len; 409 tdmac->pos = 0; 410 411 return &tdmac->desc; 412 413 err_out: 414 tdmac->status = DMA_ERROR; 415 return NULL; 416 } 417 418 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 419 unsigned long arg) 420 { 421 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 422 struct dma_slave_config *dmaengine_cfg = (void *)arg; 423 int ret = 0; 424 425 switch (cmd) { 426 case DMA_TERMINATE_ALL: 427 mmp_tdma_disable_chan(tdmac); 428 break; 429 case DMA_PAUSE: 430 mmp_tdma_pause_chan(tdmac); 431 break; 432 case DMA_RESUME: 433 mmp_tdma_resume_chan(tdmac); 434 break; 435 case DMA_SLAVE_CONFIG: 436 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 437 tdmac->dev_addr = dmaengine_cfg->src_addr; 438 tdmac->burst_sz = dmaengine_cfg->src_maxburst; 439 tdmac->buswidth = dmaengine_cfg->src_addr_width; 440 } else { 441 tdmac->dev_addr = dmaengine_cfg->dst_addr; 442 tdmac->burst_sz = dmaengine_cfg->dst_maxburst; 443 tdmac->buswidth = dmaengine_cfg->dst_addr_width; 444 } 445 tdmac->dir = dmaengine_cfg->direction; 446 return mmp_tdma_config_chan(tdmac); 447 default: 448 ret = -ENOSYS; 449 } 450 451 return ret; 452 } 453 454 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, 455 dma_cookie_t cookie, struct dma_tx_state *txstate) 456 { 457 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 458 459 dma_set_residue(txstate, tdmac->buf_len - tdmac->pos); 460 461 return tdmac->status; 462 } 463 464 static void mmp_tdma_issue_pending(struct dma_chan *chan) 465 { 466 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 467 468 mmp_tdma_enable_chan(tdmac); 469 } 470 471 static int mmp_tdma_remove(struct platform_device *pdev) 472 { 473 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); 474 475 dma_async_device_unregister(&tdev->device); 476 return 0; 477 } 478 479 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, 480 int idx, int irq, int type) 481 { 482 struct mmp_tdma_chan *tdmac; 483 484 if (idx >= TDMA_CHANNEL_NUM) { 485 dev_err(tdev->dev, "too many channels for device!\n"); 486 return -EINVAL; 487 } 488 489 /* alloc channel */ 490 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); 491 if (!tdmac) { 492 dev_err(tdev->dev, "no free memory for DMA channels!\n"); 493 return -ENOMEM; 494 } 495 if (irq) 496 tdmac->irq = irq; 497 tdmac->dev = tdev->dev; 498 tdmac->chan.device = &tdev->device; 499 tdmac->idx = idx; 500 tdmac->type = type; 501 tdmac->reg_base = (unsigned long)tdev->base + idx * 4; 502 tdmac->status = DMA_SUCCESS; 503 tdev->tdmac[tdmac->idx] = tdmac; 504 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); 505 506 /* add the channel to tdma_chan list */ 507 list_add_tail(&tdmac->chan.device_node, 508 &tdev->device.channels); 509 return 0; 510 } 511 512 static struct of_device_id mmp_tdma_dt_ids[] = { 513 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, 514 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, 515 {} 516 }; 517 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); 518 519 static int mmp_tdma_probe(struct platform_device *pdev) 520 { 521 enum mmp_tdma_type type; 522 const struct of_device_id *of_id; 523 struct mmp_tdma_device *tdev; 524 struct resource *iores; 525 int i, ret; 526 int irq = 0, irq_num = 0; 527 int chan_num = TDMA_CHANNEL_NUM; 528 529 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); 530 if (of_id) 531 type = (enum mmp_tdma_type) of_id->data; 532 else 533 type = platform_get_device_id(pdev)->driver_data; 534 535 /* always have couple channels */ 536 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); 537 if (!tdev) 538 return -ENOMEM; 539 540 tdev->dev = &pdev->dev; 541 542 for (i = 0; i < chan_num; i++) { 543 if (platform_get_irq(pdev, i) > 0) 544 irq_num++; 545 } 546 547 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 548 if (!iores) 549 return -EINVAL; 550 551 tdev->base = devm_ioremap_resource(&pdev->dev, iores); 552 if (IS_ERR(tdev->base)) 553 return PTR_ERR(tdev->base); 554 555 INIT_LIST_HEAD(&tdev->device.channels); 556 557 if (irq_num != chan_num) { 558 irq = platform_get_irq(pdev, 0); 559 ret = devm_request_irq(&pdev->dev, irq, 560 mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev); 561 if (ret) 562 return ret; 563 } 564 565 /* initialize channel parameters */ 566 for (i = 0; i < chan_num; i++) { 567 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); 568 ret = mmp_tdma_chan_init(tdev, i, irq, type); 569 if (ret) 570 return ret; 571 } 572 573 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); 574 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); 575 tdev->device.dev = &pdev->dev; 576 tdev->device.device_alloc_chan_resources = 577 mmp_tdma_alloc_chan_resources; 578 tdev->device.device_free_chan_resources = 579 mmp_tdma_free_chan_resources; 580 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; 581 tdev->device.device_tx_status = mmp_tdma_tx_status; 582 tdev->device.device_issue_pending = mmp_tdma_issue_pending; 583 tdev->device.device_control = mmp_tdma_control; 584 tdev->device.copy_align = TDMA_ALIGNMENT; 585 586 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 587 platform_set_drvdata(pdev, tdev); 588 589 ret = dma_async_device_register(&tdev->device); 590 if (ret) { 591 dev_err(tdev->device.dev, "unable to register\n"); 592 return ret; 593 } 594 595 dev_info(tdev->device.dev, "initialized\n"); 596 return 0; 597 } 598 599 static const struct platform_device_id mmp_tdma_id_table[] = { 600 { "mmp-adma", MMP_AUD_TDMA }, 601 { "pxa910-squ", PXA910_SQU }, 602 { }, 603 }; 604 605 static struct platform_driver mmp_tdma_driver = { 606 .driver = { 607 .name = "mmp-tdma", 608 .owner = THIS_MODULE, 609 .of_match_table = mmp_tdma_dt_ids, 610 }, 611 .id_table = mmp_tdma_id_table, 612 .probe = mmp_tdma_probe, 613 .remove = mmp_tdma_remove, 614 }; 615 616 module_platform_driver(mmp_tdma_driver); 617 618 MODULE_LICENSE("GPL"); 619 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); 620 MODULE_ALIAS("platform:mmp-tdma"); 621 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 622 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); 623