1 /* 2 * Driver For Marvell Two-channel DMA Engine 3 * 4 * Copyright: Marvell International Ltd. 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 */ 11 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/dmaengine.h> 20 #include <linux/platform_device.h> 21 #include <linux/device.h> 22 #include <linux/platform_data/dma-mmp_tdma.h> 23 #include <linux/of_device.h> 24 #include <linux/of_dma.h> 25 26 #include "dmaengine.h" 27 28 /* 29 * Two-Channel DMA registers 30 */ 31 #define TDBCR 0x00 /* Byte Count */ 32 #define TDSAR 0x10 /* Src Addr */ 33 #define TDDAR 0x20 /* Dst Addr */ 34 #define TDNDPR 0x30 /* Next Desc */ 35 #define TDCR 0x40 /* Control */ 36 #define TDCP 0x60 /* Priority*/ 37 #define TDCDPR 0x70 /* Current Desc */ 38 #define TDIMR 0x80 /* Int Mask */ 39 #define TDISR 0xa0 /* Int Status */ 40 41 /* Two-Channel DMA Control Register */ 42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ 43 #define TDCR_SSZ_12_BITS (0x1 << 22) 44 #define TDCR_SSZ_16_BITS (0x2 << 22) 45 #define TDCR_SSZ_20_BITS (0x3 << 22) 46 #define TDCR_SSZ_24_BITS (0x4 << 22) 47 #define TDCR_SSZ_32_BITS (0x5 << 22) 48 #define TDCR_SSZ_SHIFT (0x1 << 22) 49 #define TDCR_SSZ_MASK (0x7 << 22) 50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ 51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */ 52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ 53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ 54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ 55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ 56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ 57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ 58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ 59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ 60 #define TDCR_BURSTSZ_4B (0x0 << 6) 61 #define TDCR_BURSTSZ_8B (0x1 << 6) 62 #define TDCR_BURSTSZ_16B (0x3 << 6) 63 #define TDCR_BURSTSZ_32B (0x6 << 6) 64 #define TDCR_BURSTSZ_64B (0x7 << 6) 65 #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) 66 #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) 67 #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) 68 #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) 69 #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) 70 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) 71 #define TDCR_BURSTSZ_128B (0x5 << 6) 72 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ 73 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ 74 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ 75 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ 76 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ 77 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ 78 #define TDCR_DSTDESCCONT (0x1 << 1) 79 #define TDCR_SRCDESTCONT (0x1 << 0) 80 81 /* Two-Channel DMA Int Mask Register */ 82 #define TDIMR_COMP (0x1 << 0) 83 84 /* Two-Channel DMA Int Status Register */ 85 #define TDISR_COMP (0x1 << 0) 86 87 /* 88 * Two-Channel DMA Descriptor Struct 89 * NOTE: desc's buf must be aligned to 16 bytes. 90 */ 91 struct mmp_tdma_desc { 92 u32 byte_cnt; 93 u32 src_addr; 94 u32 dst_addr; 95 u32 nxt_desc; 96 }; 97 98 enum mmp_tdma_type { 99 MMP_AUD_TDMA = 0, 100 PXA910_SQU, 101 }; 102 103 #define TDMA_MAX_XFER_BYTES SZ_64K 104 105 struct mmp_tdma_chan { 106 struct device *dev; 107 struct dma_chan chan; 108 struct dma_async_tx_descriptor desc; 109 struct tasklet_struct tasklet; 110 111 struct mmp_tdma_desc *desc_arr; 112 dma_addr_t desc_arr_phys; 113 int desc_num; 114 enum dma_transfer_direction dir; 115 dma_addr_t dev_addr; 116 u32 burst_sz; 117 enum dma_slave_buswidth buswidth; 118 enum dma_status status; 119 120 int idx; 121 enum mmp_tdma_type type; 122 int irq; 123 void __iomem *reg_base; 124 125 size_t buf_len; 126 size_t period_len; 127 size_t pos; 128 129 struct gen_pool *pool; 130 }; 131 132 #define TDMA_CHANNEL_NUM 2 133 struct mmp_tdma_device { 134 struct device *dev; 135 void __iomem *base; 136 struct dma_device device; 137 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; 138 }; 139 140 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) 141 142 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) 143 { 144 writel(phys, tdmac->reg_base + TDNDPR); 145 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 146 tdmac->reg_base + TDCR); 147 } 148 149 static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable) 150 { 151 if (enable) 152 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 153 else 154 writel(0, tdmac->reg_base + TDIMR); 155 } 156 157 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 158 { 159 /* enable dma chan */ 160 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 161 tdmac->reg_base + TDCR); 162 tdmac->status = DMA_IN_PROGRESS; 163 } 164 165 static int mmp_tdma_disable_chan(struct dma_chan *chan) 166 { 167 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 168 u32 tdcr; 169 170 tdcr = readl(tdmac->reg_base + TDCR); 171 tdcr |= TDCR_ABR; 172 tdcr &= ~TDCR_CHANEN; 173 writel(tdcr, tdmac->reg_base + TDCR); 174 175 tdmac->status = DMA_COMPLETE; 176 177 return 0; 178 } 179 180 static int mmp_tdma_resume_chan(struct dma_chan *chan) 181 { 182 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 183 184 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 185 tdmac->reg_base + TDCR); 186 tdmac->status = DMA_IN_PROGRESS; 187 188 return 0; 189 } 190 191 static int mmp_tdma_pause_chan(struct dma_chan *chan) 192 { 193 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 194 195 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 196 tdmac->reg_base + TDCR); 197 tdmac->status = DMA_PAUSED; 198 199 return 0; 200 } 201 202 static int mmp_tdma_config_chan(struct dma_chan *chan) 203 { 204 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 205 unsigned int tdcr = 0; 206 207 mmp_tdma_disable_chan(chan); 208 209 if (tdmac->dir == DMA_MEM_TO_DEV) 210 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; 211 else if (tdmac->dir == DMA_DEV_TO_MEM) 212 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; 213 214 if (tdmac->type == MMP_AUD_TDMA) { 215 tdcr |= TDCR_PACKMOD; 216 217 switch (tdmac->burst_sz) { 218 case 4: 219 tdcr |= TDCR_BURSTSZ_4B; 220 break; 221 case 8: 222 tdcr |= TDCR_BURSTSZ_8B; 223 break; 224 case 16: 225 tdcr |= TDCR_BURSTSZ_16B; 226 break; 227 case 32: 228 tdcr |= TDCR_BURSTSZ_32B; 229 break; 230 case 64: 231 tdcr |= TDCR_BURSTSZ_64B; 232 break; 233 case 128: 234 tdcr |= TDCR_BURSTSZ_128B; 235 break; 236 default: 237 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 238 return -EINVAL; 239 } 240 241 switch (tdmac->buswidth) { 242 case DMA_SLAVE_BUSWIDTH_1_BYTE: 243 tdcr |= TDCR_SSZ_8_BITS; 244 break; 245 case DMA_SLAVE_BUSWIDTH_2_BYTES: 246 tdcr |= TDCR_SSZ_16_BITS; 247 break; 248 case DMA_SLAVE_BUSWIDTH_4_BYTES: 249 tdcr |= TDCR_SSZ_32_BITS; 250 break; 251 default: 252 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); 253 return -EINVAL; 254 } 255 } else if (tdmac->type == PXA910_SQU) { 256 tdcr |= TDCR_SSPMOD; 257 258 switch (tdmac->burst_sz) { 259 case 1: 260 tdcr |= TDCR_BURSTSZ_SQU_1B; 261 break; 262 case 2: 263 tdcr |= TDCR_BURSTSZ_SQU_2B; 264 break; 265 case 4: 266 tdcr |= TDCR_BURSTSZ_SQU_4B; 267 break; 268 case 8: 269 tdcr |= TDCR_BURSTSZ_SQU_8B; 270 break; 271 case 16: 272 tdcr |= TDCR_BURSTSZ_SQU_16B; 273 break; 274 case 32: 275 tdcr |= TDCR_BURSTSZ_SQU_32B; 276 break; 277 default: 278 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 279 return -EINVAL; 280 } 281 } 282 283 writel(tdcr, tdmac->reg_base + TDCR); 284 return 0; 285 } 286 287 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) 288 { 289 u32 reg = readl(tdmac->reg_base + TDISR); 290 291 if (reg & TDISR_COMP) { 292 /* clear irq */ 293 reg &= ~TDISR_COMP; 294 writel(reg, tdmac->reg_base + TDISR); 295 296 return 0; 297 } 298 return -EAGAIN; 299 } 300 301 static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac) 302 { 303 size_t reg; 304 305 if (tdmac->idx == 0) { 306 reg = __raw_readl(tdmac->reg_base + TDSAR); 307 reg -= tdmac->desc_arr[0].src_addr; 308 } else if (tdmac->idx == 1) { 309 reg = __raw_readl(tdmac->reg_base + TDDAR); 310 reg -= tdmac->desc_arr[0].dst_addr; 311 } else 312 return -EINVAL; 313 314 return reg; 315 } 316 317 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) 318 { 319 struct mmp_tdma_chan *tdmac = dev_id; 320 321 if (mmp_tdma_clear_chan_irq(tdmac) == 0) { 322 tasklet_schedule(&tdmac->tasklet); 323 return IRQ_HANDLED; 324 } else 325 return IRQ_NONE; 326 } 327 328 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) 329 { 330 struct mmp_tdma_device *tdev = dev_id; 331 int i, ret; 332 int irq_num = 0; 333 334 for (i = 0; i < TDMA_CHANNEL_NUM; i++) { 335 struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; 336 337 ret = mmp_tdma_chan_handler(irq, tdmac); 338 if (ret == IRQ_HANDLED) 339 irq_num++; 340 } 341 342 if (irq_num) 343 return IRQ_HANDLED; 344 else 345 return IRQ_NONE; 346 } 347 348 static void dma_do_tasklet(unsigned long data) 349 { 350 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; 351 352 if (tdmac->desc.callback) 353 tdmac->desc.callback(tdmac->desc.callback_param); 354 355 } 356 357 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) 358 { 359 struct gen_pool *gpool; 360 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 361 362 gpool = tdmac->pool; 363 if (gpool && tdmac->desc_arr) 364 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, 365 size); 366 tdmac->desc_arr = NULL; 367 368 return; 369 } 370 371 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) 372 { 373 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); 374 375 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); 376 377 return 0; 378 } 379 380 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) 381 { 382 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 383 int ret; 384 385 dma_async_tx_descriptor_init(&tdmac->desc, chan); 386 tdmac->desc.tx_submit = mmp_tdma_tx_submit; 387 388 if (tdmac->irq) { 389 ret = devm_request_irq(tdmac->dev, tdmac->irq, 390 mmp_tdma_chan_handler, 0, "tdma", tdmac); 391 if (ret) 392 return ret; 393 } 394 return 1; 395 } 396 397 static void mmp_tdma_free_chan_resources(struct dma_chan *chan) 398 { 399 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 400 401 if (tdmac->irq) 402 devm_free_irq(tdmac->dev, tdmac->irq, tdmac); 403 mmp_tdma_free_descriptor(tdmac); 404 return; 405 } 406 407 static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) 408 { 409 struct gen_pool *gpool; 410 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 411 412 gpool = tdmac->pool; 413 if (!gpool) 414 return NULL; 415 416 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys); 417 418 return tdmac->desc_arr; 419 } 420 421 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( 422 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 423 size_t period_len, enum dma_transfer_direction direction, 424 unsigned long flags) 425 { 426 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 427 struct mmp_tdma_desc *desc; 428 int num_periods = buf_len / period_len; 429 int i = 0, buf = 0; 430 431 if (tdmac->status != DMA_COMPLETE) 432 return NULL; 433 434 if (period_len > TDMA_MAX_XFER_BYTES) { 435 dev_err(tdmac->dev, 436 "maximum period size exceeded: %d > %d\n", 437 period_len, TDMA_MAX_XFER_BYTES); 438 goto err_out; 439 } 440 441 tdmac->status = DMA_IN_PROGRESS; 442 tdmac->desc_num = num_periods; 443 desc = mmp_tdma_alloc_descriptor(tdmac); 444 if (!desc) 445 goto err_out; 446 447 while (buf < buf_len) { 448 desc = &tdmac->desc_arr[i]; 449 450 if (i + 1 == num_periods) 451 desc->nxt_desc = tdmac->desc_arr_phys; 452 else 453 desc->nxt_desc = tdmac->desc_arr_phys + 454 sizeof(*desc) * (i + 1); 455 456 if (direction == DMA_MEM_TO_DEV) { 457 desc->src_addr = dma_addr; 458 desc->dst_addr = tdmac->dev_addr; 459 } else { 460 desc->src_addr = tdmac->dev_addr; 461 desc->dst_addr = dma_addr; 462 } 463 desc->byte_cnt = period_len; 464 dma_addr += period_len; 465 buf += period_len; 466 i++; 467 } 468 469 /* enable interrupt */ 470 if (flags & DMA_PREP_INTERRUPT) 471 mmp_tdma_enable_irq(tdmac, true); 472 473 tdmac->buf_len = buf_len; 474 tdmac->period_len = period_len; 475 tdmac->pos = 0; 476 477 return &tdmac->desc; 478 479 err_out: 480 tdmac->status = DMA_ERROR; 481 return NULL; 482 } 483 484 static int mmp_tdma_terminate_all(struct dma_chan *chan) 485 { 486 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 487 488 mmp_tdma_disable_chan(chan); 489 /* disable interrupt */ 490 mmp_tdma_enable_irq(tdmac, false); 491 492 return 0; 493 } 494 495 static int mmp_tdma_config(struct dma_chan *chan, 496 struct dma_slave_config *dmaengine_cfg) 497 { 498 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 499 500 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 501 tdmac->dev_addr = dmaengine_cfg->src_addr; 502 tdmac->burst_sz = dmaengine_cfg->src_maxburst; 503 tdmac->buswidth = dmaengine_cfg->src_addr_width; 504 } else { 505 tdmac->dev_addr = dmaengine_cfg->dst_addr; 506 tdmac->burst_sz = dmaengine_cfg->dst_maxburst; 507 tdmac->buswidth = dmaengine_cfg->dst_addr_width; 508 } 509 tdmac->dir = dmaengine_cfg->direction; 510 511 return mmp_tdma_config_chan(chan); 512 } 513 514 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, 515 dma_cookie_t cookie, struct dma_tx_state *txstate) 516 { 517 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 518 519 tdmac->pos = mmp_tdma_get_pos(tdmac); 520 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 521 tdmac->buf_len - tdmac->pos); 522 523 return tdmac->status; 524 } 525 526 static void mmp_tdma_issue_pending(struct dma_chan *chan) 527 { 528 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 529 530 mmp_tdma_enable_chan(tdmac); 531 } 532 533 static int mmp_tdma_remove(struct platform_device *pdev) 534 { 535 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); 536 537 dma_async_device_unregister(&tdev->device); 538 return 0; 539 } 540 541 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, 542 int idx, int irq, 543 int type, struct gen_pool *pool) 544 { 545 struct mmp_tdma_chan *tdmac; 546 547 if (idx >= TDMA_CHANNEL_NUM) { 548 dev_err(tdev->dev, "too many channels for device!\n"); 549 return -EINVAL; 550 } 551 552 /* alloc channel */ 553 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); 554 if (!tdmac) 555 return -ENOMEM; 556 557 if (irq) 558 tdmac->irq = irq; 559 tdmac->dev = tdev->dev; 560 tdmac->chan.device = &tdev->device; 561 tdmac->idx = idx; 562 tdmac->type = type; 563 tdmac->reg_base = tdev->base + idx * 4; 564 tdmac->pool = pool; 565 tdmac->status = DMA_COMPLETE; 566 tdev->tdmac[tdmac->idx] = tdmac; 567 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); 568 569 /* add the channel to tdma_chan list */ 570 list_add_tail(&tdmac->chan.device_node, 571 &tdev->device.channels); 572 return 0; 573 } 574 575 struct mmp_tdma_filter_param { 576 struct device_node *of_node; 577 unsigned int chan_id; 578 }; 579 580 static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param) 581 { 582 struct mmp_tdma_filter_param *param = fn_param; 583 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 584 struct dma_device *pdma_device = tdmac->chan.device; 585 586 if (pdma_device->dev->of_node != param->of_node) 587 return false; 588 589 if (chan->chan_id != param->chan_id) 590 return false; 591 592 return true; 593 } 594 595 static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec, 596 struct of_dma *ofdma) 597 { 598 struct mmp_tdma_device *tdev = ofdma->of_dma_data; 599 dma_cap_mask_t mask = tdev->device.cap_mask; 600 struct mmp_tdma_filter_param param; 601 602 if (dma_spec->args_count != 1) 603 return NULL; 604 605 param.of_node = ofdma->of_node; 606 param.chan_id = dma_spec->args[0]; 607 608 if (param.chan_id >= TDMA_CHANNEL_NUM) 609 return NULL; 610 611 return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m); 612 } 613 614 static const struct of_device_id mmp_tdma_dt_ids[] = { 615 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, 616 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, 617 {} 618 }; 619 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); 620 621 static int mmp_tdma_probe(struct platform_device *pdev) 622 { 623 enum mmp_tdma_type type; 624 const struct of_device_id *of_id; 625 struct mmp_tdma_device *tdev; 626 struct resource *iores; 627 int i, ret; 628 int irq = 0, irq_num = 0; 629 int chan_num = TDMA_CHANNEL_NUM; 630 struct gen_pool *pool = NULL; 631 632 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); 633 if (of_id) 634 type = (enum mmp_tdma_type) of_id->data; 635 else 636 type = platform_get_device_id(pdev)->driver_data; 637 638 /* always have couple channels */ 639 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); 640 if (!tdev) 641 return -ENOMEM; 642 643 tdev->dev = &pdev->dev; 644 645 for (i = 0; i < chan_num; i++) { 646 if (platform_get_irq(pdev, i) > 0) 647 irq_num++; 648 } 649 650 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 651 tdev->base = devm_ioremap_resource(&pdev->dev, iores); 652 if (IS_ERR(tdev->base)) 653 return PTR_ERR(tdev->base); 654 655 INIT_LIST_HEAD(&tdev->device.channels); 656 657 if (pdev->dev.of_node) 658 pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0); 659 else 660 pool = sram_get_gpool("asram"); 661 if (!pool) { 662 dev_err(&pdev->dev, "asram pool not available\n"); 663 return -ENOMEM; 664 } 665 666 if (irq_num != chan_num) { 667 irq = platform_get_irq(pdev, 0); 668 ret = devm_request_irq(&pdev->dev, irq, 669 mmp_tdma_int_handler, 0, "tdma", tdev); 670 if (ret) 671 return ret; 672 } 673 674 /* initialize channel parameters */ 675 for (i = 0; i < chan_num; i++) { 676 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); 677 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool); 678 if (ret) 679 return ret; 680 } 681 682 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); 683 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); 684 tdev->device.dev = &pdev->dev; 685 tdev->device.device_alloc_chan_resources = 686 mmp_tdma_alloc_chan_resources; 687 tdev->device.device_free_chan_resources = 688 mmp_tdma_free_chan_resources; 689 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; 690 tdev->device.device_tx_status = mmp_tdma_tx_status; 691 tdev->device.device_issue_pending = mmp_tdma_issue_pending; 692 tdev->device.device_config = mmp_tdma_config; 693 tdev->device.device_pause = mmp_tdma_pause_chan; 694 tdev->device.device_resume = mmp_tdma_resume_chan; 695 tdev->device.device_terminate_all = mmp_tdma_terminate_all; 696 tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES; 697 698 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 699 platform_set_drvdata(pdev, tdev); 700 701 ret = dma_async_device_register(&tdev->device); 702 if (ret) { 703 dev_err(tdev->device.dev, "unable to register\n"); 704 return ret; 705 } 706 707 if (pdev->dev.of_node) { 708 ret = of_dma_controller_register(pdev->dev.of_node, 709 mmp_tdma_xlate, tdev); 710 if (ret) { 711 dev_err(tdev->device.dev, 712 "failed to register controller\n"); 713 dma_async_device_unregister(&tdev->device); 714 } 715 } 716 717 dev_info(tdev->device.dev, "initialized\n"); 718 return 0; 719 } 720 721 static const struct platform_device_id mmp_tdma_id_table[] = { 722 { "mmp-adma", MMP_AUD_TDMA }, 723 { "pxa910-squ", PXA910_SQU }, 724 { }, 725 }; 726 727 static struct platform_driver mmp_tdma_driver = { 728 .driver = { 729 .name = "mmp-tdma", 730 .of_match_table = mmp_tdma_dt_ids, 731 }, 732 .id_table = mmp_tdma_id_table, 733 .probe = mmp_tdma_probe, 734 .remove = mmp_tdma_remove, 735 }; 736 737 module_platform_driver(mmp_tdma_driver); 738 739 MODULE_LICENSE("GPL"); 740 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); 741 MODULE_ALIAS("platform:mmp-tdma"); 742 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 743 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); 744