1 /* 2 * Driver For Marvell Two-channel DMA Engine 3 * 4 * Copyright: Marvell International Ltd. 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 */ 11 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/dmaengine.h> 20 #include <linux/platform_device.h> 21 #include <linux/device.h> 22 #include <linux/platform_data/dma-mmp_tdma.h> 23 #include <linux/of_device.h> 24 #include <linux/of_dma.h> 25 26 #include "dmaengine.h" 27 28 /* 29 * Two-Channel DMA registers 30 */ 31 #define TDBCR 0x00 /* Byte Count */ 32 #define TDSAR 0x10 /* Src Addr */ 33 #define TDDAR 0x20 /* Dst Addr */ 34 #define TDNDPR 0x30 /* Next Desc */ 35 #define TDCR 0x40 /* Control */ 36 #define TDCP 0x60 /* Priority*/ 37 #define TDCDPR 0x70 /* Current Desc */ 38 #define TDIMR 0x80 /* Int Mask */ 39 #define TDISR 0xa0 /* Int Status */ 40 41 /* Two-Channel DMA Control Register */ 42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ 43 #define TDCR_SSZ_12_BITS (0x1 << 22) 44 #define TDCR_SSZ_16_BITS (0x2 << 22) 45 #define TDCR_SSZ_20_BITS (0x3 << 22) 46 #define TDCR_SSZ_24_BITS (0x4 << 22) 47 #define TDCR_SSZ_32_BITS (0x5 << 22) 48 #define TDCR_SSZ_SHIFT (0x1 << 22) 49 #define TDCR_SSZ_MASK (0x7 << 22) 50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ 51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */ 52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ 53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ 54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ 55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ 56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ 57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ 58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ 59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ 60 #define TDCR_BURSTSZ_4B (0x0 << 6) 61 #define TDCR_BURSTSZ_8B (0x1 << 6) 62 #define TDCR_BURSTSZ_16B (0x3 << 6) 63 #define TDCR_BURSTSZ_32B (0x6 << 6) 64 #define TDCR_BURSTSZ_64B (0x7 << 6) 65 #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) 66 #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) 67 #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) 68 #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) 69 #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) 70 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) 71 #define TDCR_BURSTSZ_128B (0x5 << 6) 72 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ 73 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ 74 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ 75 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ 76 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ 77 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ 78 #define TDCR_DSTDESCCONT (0x1 << 1) 79 #define TDCR_SRCDESTCONT (0x1 << 0) 80 81 /* Two-Channel DMA Int Mask Register */ 82 #define TDIMR_COMP (0x1 << 0) 83 84 /* Two-Channel DMA Int Status Register */ 85 #define TDISR_COMP (0x1 << 0) 86 87 /* 88 * Two-Channel DMA Descriptor Struct 89 * NOTE: desc's buf must be aligned to 16 bytes. 90 */ 91 struct mmp_tdma_desc { 92 u32 byte_cnt; 93 u32 src_addr; 94 u32 dst_addr; 95 u32 nxt_desc; 96 }; 97 98 enum mmp_tdma_type { 99 MMP_AUD_TDMA = 0, 100 PXA910_SQU, 101 }; 102 103 #define TDMA_ALIGNMENT 3 104 #define TDMA_MAX_XFER_BYTES SZ_64K 105 106 struct mmp_tdma_chan { 107 struct device *dev; 108 struct dma_chan chan; 109 struct dma_async_tx_descriptor desc; 110 struct tasklet_struct tasklet; 111 112 struct mmp_tdma_desc *desc_arr; 113 phys_addr_t desc_arr_phys; 114 int desc_num; 115 enum dma_transfer_direction dir; 116 dma_addr_t dev_addr; 117 u32 burst_sz; 118 enum dma_slave_buswidth buswidth; 119 enum dma_status status; 120 121 int idx; 122 enum mmp_tdma_type type; 123 int irq; 124 void __iomem *reg_base; 125 126 size_t buf_len; 127 size_t period_len; 128 size_t pos; 129 130 struct gen_pool *pool; 131 }; 132 133 #define TDMA_CHANNEL_NUM 2 134 struct mmp_tdma_device { 135 struct device *dev; 136 void __iomem *base; 137 struct dma_device device; 138 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; 139 }; 140 141 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) 142 143 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) 144 { 145 writel(phys, tdmac->reg_base + TDNDPR); 146 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 147 tdmac->reg_base + TDCR); 148 } 149 150 static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable) 151 { 152 if (enable) 153 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 154 else 155 writel(0, tdmac->reg_base + TDIMR); 156 } 157 158 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 159 { 160 /* enable dma chan */ 161 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 162 tdmac->reg_base + TDCR); 163 tdmac->status = DMA_IN_PROGRESS; 164 } 165 166 static int mmp_tdma_disable_chan(struct dma_chan *chan) 167 { 168 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 169 170 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 171 tdmac->reg_base + TDCR); 172 173 tdmac->status = DMA_COMPLETE; 174 175 return 0; 176 } 177 178 static int mmp_tdma_resume_chan(struct dma_chan *chan) 179 { 180 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 181 182 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 183 tdmac->reg_base + TDCR); 184 tdmac->status = DMA_IN_PROGRESS; 185 186 return 0; 187 } 188 189 static int mmp_tdma_pause_chan(struct dma_chan *chan) 190 { 191 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 192 193 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 194 tdmac->reg_base + TDCR); 195 tdmac->status = DMA_PAUSED; 196 197 return 0; 198 } 199 200 static int mmp_tdma_config_chan(struct dma_chan *chan) 201 { 202 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 203 unsigned int tdcr = 0; 204 205 mmp_tdma_disable_chan(chan); 206 207 if (tdmac->dir == DMA_MEM_TO_DEV) 208 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; 209 else if (tdmac->dir == DMA_DEV_TO_MEM) 210 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; 211 212 if (tdmac->type == MMP_AUD_TDMA) { 213 tdcr |= TDCR_PACKMOD; 214 215 switch (tdmac->burst_sz) { 216 case 4: 217 tdcr |= TDCR_BURSTSZ_4B; 218 break; 219 case 8: 220 tdcr |= TDCR_BURSTSZ_8B; 221 break; 222 case 16: 223 tdcr |= TDCR_BURSTSZ_16B; 224 break; 225 case 32: 226 tdcr |= TDCR_BURSTSZ_32B; 227 break; 228 case 64: 229 tdcr |= TDCR_BURSTSZ_64B; 230 break; 231 case 128: 232 tdcr |= TDCR_BURSTSZ_128B; 233 break; 234 default: 235 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 236 return -EINVAL; 237 } 238 239 switch (tdmac->buswidth) { 240 case DMA_SLAVE_BUSWIDTH_1_BYTE: 241 tdcr |= TDCR_SSZ_8_BITS; 242 break; 243 case DMA_SLAVE_BUSWIDTH_2_BYTES: 244 tdcr |= TDCR_SSZ_16_BITS; 245 break; 246 case DMA_SLAVE_BUSWIDTH_4_BYTES: 247 tdcr |= TDCR_SSZ_32_BITS; 248 break; 249 default: 250 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); 251 return -EINVAL; 252 } 253 } else if (tdmac->type == PXA910_SQU) { 254 tdcr |= TDCR_SSPMOD; 255 256 switch (tdmac->burst_sz) { 257 case 1: 258 tdcr |= TDCR_BURSTSZ_SQU_1B; 259 break; 260 case 2: 261 tdcr |= TDCR_BURSTSZ_SQU_2B; 262 break; 263 case 4: 264 tdcr |= TDCR_BURSTSZ_SQU_4B; 265 break; 266 case 8: 267 tdcr |= TDCR_BURSTSZ_SQU_8B; 268 break; 269 case 16: 270 tdcr |= TDCR_BURSTSZ_SQU_16B; 271 break; 272 case 32: 273 tdcr |= TDCR_BURSTSZ_SQU_32B; 274 break; 275 default: 276 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); 277 return -EINVAL; 278 } 279 } 280 281 writel(tdcr, tdmac->reg_base + TDCR); 282 return 0; 283 } 284 285 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) 286 { 287 u32 reg = readl(tdmac->reg_base + TDISR); 288 289 if (reg & TDISR_COMP) { 290 /* clear irq */ 291 reg &= ~TDISR_COMP; 292 writel(reg, tdmac->reg_base + TDISR); 293 294 return 0; 295 } 296 return -EAGAIN; 297 } 298 299 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) 300 { 301 struct mmp_tdma_chan *tdmac = dev_id; 302 303 if (mmp_tdma_clear_chan_irq(tdmac) == 0) { 304 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len; 305 tasklet_schedule(&tdmac->tasklet); 306 return IRQ_HANDLED; 307 } else 308 return IRQ_NONE; 309 } 310 311 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) 312 { 313 struct mmp_tdma_device *tdev = dev_id; 314 int i, ret; 315 int irq_num = 0; 316 317 for (i = 0; i < TDMA_CHANNEL_NUM; i++) { 318 struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; 319 320 ret = mmp_tdma_chan_handler(irq, tdmac); 321 if (ret == IRQ_HANDLED) 322 irq_num++; 323 } 324 325 if (irq_num) 326 return IRQ_HANDLED; 327 else 328 return IRQ_NONE; 329 } 330 331 static void dma_do_tasklet(unsigned long data) 332 { 333 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; 334 335 if (tdmac->desc.callback) 336 tdmac->desc.callback(tdmac->desc.callback_param); 337 338 } 339 340 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) 341 { 342 struct gen_pool *gpool; 343 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 344 345 gpool = tdmac->pool; 346 if (tdmac->desc_arr) 347 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, 348 size); 349 tdmac->desc_arr = NULL; 350 351 return; 352 } 353 354 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) 355 { 356 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); 357 358 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); 359 360 return 0; 361 } 362 363 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) 364 { 365 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 366 int ret; 367 368 dma_async_tx_descriptor_init(&tdmac->desc, chan); 369 tdmac->desc.tx_submit = mmp_tdma_tx_submit; 370 371 if (tdmac->irq) { 372 ret = devm_request_irq(tdmac->dev, tdmac->irq, 373 mmp_tdma_chan_handler, 0, "tdma", tdmac); 374 if (ret) 375 return ret; 376 } 377 return 1; 378 } 379 380 static void mmp_tdma_free_chan_resources(struct dma_chan *chan) 381 { 382 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 383 384 if (tdmac->irq) 385 devm_free_irq(tdmac->dev, tdmac->irq, tdmac); 386 mmp_tdma_free_descriptor(tdmac); 387 return; 388 } 389 390 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) 391 { 392 struct gen_pool *gpool; 393 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); 394 395 gpool = tdmac->pool; 396 if (!gpool) 397 return NULL; 398 399 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys); 400 401 return tdmac->desc_arr; 402 } 403 404 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( 405 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 406 size_t period_len, enum dma_transfer_direction direction, 407 unsigned long flags) 408 { 409 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 410 struct mmp_tdma_desc *desc; 411 int num_periods = buf_len / period_len; 412 int i = 0, buf = 0; 413 414 if (tdmac->status != DMA_COMPLETE) 415 return NULL; 416 417 if (period_len > TDMA_MAX_XFER_BYTES) { 418 dev_err(tdmac->dev, 419 "maximum period size exceeded: %d > %d\n", 420 period_len, TDMA_MAX_XFER_BYTES); 421 goto err_out; 422 } 423 424 tdmac->status = DMA_IN_PROGRESS; 425 tdmac->desc_num = num_periods; 426 desc = mmp_tdma_alloc_descriptor(tdmac); 427 if (!desc) 428 goto err_out; 429 430 while (buf < buf_len) { 431 desc = &tdmac->desc_arr[i]; 432 433 if (i + 1 == num_periods) 434 desc->nxt_desc = tdmac->desc_arr_phys; 435 else 436 desc->nxt_desc = tdmac->desc_arr_phys + 437 sizeof(*desc) * (i + 1); 438 439 if (direction == DMA_MEM_TO_DEV) { 440 desc->src_addr = dma_addr; 441 desc->dst_addr = tdmac->dev_addr; 442 } else { 443 desc->src_addr = tdmac->dev_addr; 444 desc->dst_addr = dma_addr; 445 } 446 desc->byte_cnt = period_len; 447 dma_addr += period_len; 448 buf += period_len; 449 i++; 450 } 451 452 /* enable interrupt */ 453 if (flags & DMA_PREP_INTERRUPT) 454 mmp_tdma_enable_irq(tdmac, true); 455 456 tdmac->buf_len = buf_len; 457 tdmac->period_len = period_len; 458 tdmac->pos = 0; 459 460 return &tdmac->desc; 461 462 err_out: 463 tdmac->status = DMA_ERROR; 464 return NULL; 465 } 466 467 static int mmp_tdma_terminate_all(struct dma_chan *chan) 468 { 469 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 470 471 mmp_tdma_disable_chan(chan); 472 /* disable interrupt */ 473 mmp_tdma_enable_irq(tdmac, false); 474 475 return 0; 476 } 477 478 static int mmp_tdma_config(struct dma_chan *chan, 479 struct dma_slave_config *dmaengine_cfg) 480 { 481 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 482 483 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 484 tdmac->dev_addr = dmaengine_cfg->src_addr; 485 tdmac->burst_sz = dmaengine_cfg->src_maxburst; 486 tdmac->buswidth = dmaengine_cfg->src_addr_width; 487 } else { 488 tdmac->dev_addr = dmaengine_cfg->dst_addr; 489 tdmac->burst_sz = dmaengine_cfg->dst_maxburst; 490 tdmac->buswidth = dmaengine_cfg->dst_addr_width; 491 } 492 tdmac->dir = dmaengine_cfg->direction; 493 494 return mmp_tdma_config_chan(chan); 495 } 496 497 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, 498 dma_cookie_t cookie, struct dma_tx_state *txstate) 499 { 500 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 501 502 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 503 tdmac->buf_len - tdmac->pos); 504 505 return tdmac->status; 506 } 507 508 static void mmp_tdma_issue_pending(struct dma_chan *chan) 509 { 510 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 511 512 mmp_tdma_enable_chan(tdmac); 513 } 514 515 static int mmp_tdma_remove(struct platform_device *pdev) 516 { 517 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); 518 519 dma_async_device_unregister(&tdev->device); 520 return 0; 521 } 522 523 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, 524 int idx, int irq, 525 int type, struct gen_pool *pool) 526 { 527 struct mmp_tdma_chan *tdmac; 528 529 if (idx >= TDMA_CHANNEL_NUM) { 530 dev_err(tdev->dev, "too many channels for device!\n"); 531 return -EINVAL; 532 } 533 534 /* alloc channel */ 535 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); 536 if (!tdmac) { 537 dev_err(tdev->dev, "no free memory for DMA channels!\n"); 538 return -ENOMEM; 539 } 540 if (irq) 541 tdmac->irq = irq; 542 tdmac->dev = tdev->dev; 543 tdmac->chan.device = &tdev->device; 544 tdmac->idx = idx; 545 tdmac->type = type; 546 tdmac->reg_base = tdev->base + idx * 4; 547 tdmac->pool = pool; 548 tdmac->status = DMA_COMPLETE; 549 tdev->tdmac[tdmac->idx] = tdmac; 550 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); 551 552 /* add the channel to tdma_chan list */ 553 list_add_tail(&tdmac->chan.device_node, 554 &tdev->device.channels); 555 return 0; 556 } 557 558 struct mmp_tdma_filter_param { 559 struct device_node *of_node; 560 unsigned int chan_id; 561 }; 562 563 static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param) 564 { 565 struct mmp_tdma_filter_param *param = fn_param; 566 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); 567 struct dma_device *pdma_device = tdmac->chan.device; 568 569 if (pdma_device->dev->of_node != param->of_node) 570 return false; 571 572 if (chan->chan_id != param->chan_id) 573 return false; 574 575 return true; 576 } 577 578 struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec, 579 struct of_dma *ofdma) 580 { 581 struct mmp_tdma_device *tdev = ofdma->of_dma_data; 582 dma_cap_mask_t mask = tdev->device.cap_mask; 583 struct mmp_tdma_filter_param param; 584 585 if (dma_spec->args_count != 1) 586 return NULL; 587 588 param.of_node = ofdma->of_node; 589 param.chan_id = dma_spec->args[0]; 590 591 if (param.chan_id >= TDMA_CHANNEL_NUM) 592 return NULL; 593 594 return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m); 595 } 596 597 static struct of_device_id mmp_tdma_dt_ids[] = { 598 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, 599 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, 600 {} 601 }; 602 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); 603 604 static int mmp_tdma_probe(struct platform_device *pdev) 605 { 606 enum mmp_tdma_type type; 607 const struct of_device_id *of_id; 608 struct mmp_tdma_device *tdev; 609 struct resource *iores; 610 int i, ret; 611 int irq = 0, irq_num = 0; 612 int chan_num = TDMA_CHANNEL_NUM; 613 struct gen_pool *pool; 614 615 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); 616 if (of_id) 617 type = (enum mmp_tdma_type) of_id->data; 618 else 619 type = platform_get_device_id(pdev)->driver_data; 620 621 /* always have couple channels */ 622 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); 623 if (!tdev) 624 return -ENOMEM; 625 626 tdev->dev = &pdev->dev; 627 628 for (i = 0; i < chan_num; i++) { 629 if (platform_get_irq(pdev, i) > 0) 630 irq_num++; 631 } 632 633 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 634 tdev->base = devm_ioremap_resource(&pdev->dev, iores); 635 if (IS_ERR(tdev->base)) 636 return PTR_ERR(tdev->base); 637 638 INIT_LIST_HEAD(&tdev->device.channels); 639 640 if (pdev->dev.of_node) 641 pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0); 642 else 643 pool = sram_get_gpool("asram"); 644 if (!pool) { 645 dev_err(&pdev->dev, "asram pool not available\n"); 646 return -ENOMEM; 647 } 648 649 if (irq_num != chan_num) { 650 irq = platform_get_irq(pdev, 0); 651 ret = devm_request_irq(&pdev->dev, irq, 652 mmp_tdma_int_handler, 0, "tdma", tdev); 653 if (ret) 654 return ret; 655 } 656 657 /* initialize channel parameters */ 658 for (i = 0; i < chan_num; i++) { 659 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); 660 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool); 661 if (ret) 662 return ret; 663 } 664 665 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); 666 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); 667 tdev->device.dev = &pdev->dev; 668 tdev->device.device_alloc_chan_resources = 669 mmp_tdma_alloc_chan_resources; 670 tdev->device.device_free_chan_resources = 671 mmp_tdma_free_chan_resources; 672 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; 673 tdev->device.device_tx_status = mmp_tdma_tx_status; 674 tdev->device.device_issue_pending = mmp_tdma_issue_pending; 675 tdev->device.device_config = mmp_tdma_config; 676 tdev->device.device_pause = mmp_tdma_pause_chan; 677 tdev->device.device_resume = mmp_tdma_resume_chan; 678 tdev->device.device_terminate_all = mmp_tdma_terminate_all; 679 tdev->device.copy_align = TDMA_ALIGNMENT; 680 681 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 682 platform_set_drvdata(pdev, tdev); 683 684 ret = dma_async_device_register(&tdev->device); 685 if (ret) { 686 dev_err(tdev->device.dev, "unable to register\n"); 687 return ret; 688 } 689 690 if (pdev->dev.of_node) { 691 ret = of_dma_controller_register(pdev->dev.of_node, 692 mmp_tdma_xlate, tdev); 693 if (ret) { 694 dev_err(tdev->device.dev, 695 "failed to register controller\n"); 696 dma_async_device_unregister(&tdev->device); 697 } 698 } 699 700 dev_info(tdev->device.dev, "initialized\n"); 701 return 0; 702 } 703 704 static const struct platform_device_id mmp_tdma_id_table[] = { 705 { "mmp-adma", MMP_AUD_TDMA }, 706 { "pxa910-squ", PXA910_SQU }, 707 { }, 708 }; 709 710 static struct platform_driver mmp_tdma_driver = { 711 .driver = { 712 .name = "mmp-tdma", 713 .of_match_table = mmp_tdma_dt_ids, 714 }, 715 .id_table = mmp_tdma_id_table, 716 .probe = mmp_tdma_probe, 717 .remove = mmp_tdma_remove, 718 }; 719 720 module_platform_driver(mmp_tdma_driver); 721 722 MODULE_LICENSE("GPL"); 723 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); 724 MODULE_ALIAS("platform:mmp-tdma"); 725 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 726 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); 727