1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek UART APDMA driver. 4 * 5 * Copyright (c) 2019 MediaTek Inc. 6 * Author: Long Cheng <long.cheng@mediatek.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/of_dma.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 26 #include "../virt-dma.h" 27 28 /* The default number of virtual channel */ 29 #define MTK_UART_APDMA_NR_VCHANS 8 30 31 #define VFF_EN_B BIT(0) 32 #define VFF_STOP_B BIT(0) 33 #define VFF_FLUSH_B BIT(0) 34 #define VFF_4G_EN_B BIT(0) 35 /* rx valid size >= vff thre */ 36 #define VFF_RX_INT_EN_B (BIT(0) | BIT(1)) 37 /* tx left size >= vff thre */ 38 #define VFF_TX_INT_EN_B BIT(0) 39 #define VFF_WARM_RST_B BIT(0) 40 #define VFF_RX_INT_CLR_B (BIT(0) | BIT(1)) 41 #define VFF_TX_INT_CLR_B 0 42 #define VFF_STOP_CLR_B 0 43 #define VFF_EN_CLR_B 0 44 #define VFF_INT_EN_CLR_B 0 45 #define VFF_4G_SUPPORT_CLR_B 0 46 47 /* 48 * interrupt trigger level for tx 49 * if threshold is n, no polling is required to start tx. 50 * otherwise need polling VFF_FLUSH. 51 */ 52 #define VFF_TX_THRE(n) (n) 53 /* interrupt trigger level for rx */ 54 #define VFF_RX_THRE(n) ((n) * 3 / 4) 55 56 #define VFF_RING_SIZE 0xffff 57 /* invert this bit when wrap ring head again */ 58 #define VFF_RING_WRAP 0x10000 59 60 #define VFF_INT_FLAG 0x00 61 #define VFF_INT_EN 0x04 62 #define VFF_EN 0x08 63 #define VFF_RST 0x0c 64 #define VFF_STOP 0x10 65 #define VFF_FLUSH 0x14 66 #define VFF_ADDR 0x1c 67 #define VFF_LEN 0x24 68 #define VFF_THRE 0x28 69 #define VFF_WPT 0x2c 70 #define VFF_RPT 0x30 71 /* TX: the buffer size HW can read. RX: the buffer size SW can read. */ 72 #define VFF_VALID_SIZE 0x3c 73 /* TX: the buffer size SW can write. RX: the buffer size HW can write. */ 74 #define VFF_LEFT_SIZE 0x40 75 #define VFF_DEBUG_STATUS 0x50 76 #define VFF_4G_SUPPORT 0x54 77 78 struct mtk_uart_apdmadev { 79 struct dma_device ddev; 80 struct clk *clk; 81 bool support_33bits; 82 unsigned int dma_requests; 83 }; 84 85 struct mtk_uart_apdma_desc { 86 struct virt_dma_desc vd; 87 88 dma_addr_t addr; 89 unsigned int avail_len; 90 }; 91 92 struct mtk_chan { 93 struct virt_dma_chan vc; 94 struct dma_slave_config cfg; 95 struct mtk_uart_apdma_desc *desc; 96 enum dma_transfer_direction dir; 97 98 void __iomem *base; 99 unsigned int irq; 100 101 unsigned int rx_status; 102 }; 103 104 static inline struct mtk_uart_apdmadev * 105 to_mtk_uart_apdma_dev(struct dma_device *d) 106 { 107 return container_of(d, struct mtk_uart_apdmadev, ddev); 108 } 109 110 static inline struct mtk_chan *to_mtk_uart_apdma_chan(struct dma_chan *c) 111 { 112 return container_of(c, struct mtk_chan, vc.chan); 113 } 114 115 static inline struct mtk_uart_apdma_desc *to_mtk_uart_apdma_desc 116 (struct dma_async_tx_descriptor *t) 117 { 118 return container_of(t, struct mtk_uart_apdma_desc, vd.tx); 119 } 120 121 static void mtk_uart_apdma_write(struct mtk_chan *c, 122 unsigned int reg, unsigned int val) 123 { 124 writel(val, c->base + reg); 125 } 126 127 static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg) 128 { 129 return readl(c->base + reg); 130 } 131 132 static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd) 133 { 134 kfree(container_of(vd, struct mtk_uart_apdma_desc, vd)); 135 } 136 137 static void mtk_uart_apdma_start_tx(struct mtk_chan *c) 138 { 139 struct mtk_uart_apdmadev *mtkd = 140 to_mtk_uart_apdma_dev(c->vc.chan.device); 141 struct mtk_uart_apdma_desc *d = c->desc; 142 unsigned int wpt, vff_sz; 143 144 vff_sz = c->cfg.dst_port_window_size; 145 if (!mtk_uart_apdma_read(c, VFF_LEN)) { 146 mtk_uart_apdma_write(c, VFF_ADDR, d->addr); 147 mtk_uart_apdma_write(c, VFF_LEN, vff_sz); 148 mtk_uart_apdma_write(c, VFF_THRE, VFF_TX_THRE(vff_sz)); 149 mtk_uart_apdma_write(c, VFF_WPT, 0); 150 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); 151 152 if (mtkd->support_33bits) 153 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B); 154 } 155 156 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B); 157 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B) 158 dev_err(c->vc.chan.device->dev, "Enable TX fail\n"); 159 160 if (!mtk_uart_apdma_read(c, VFF_LEFT_SIZE)) { 161 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B); 162 return; 163 } 164 165 wpt = mtk_uart_apdma_read(c, VFF_WPT); 166 167 wpt += c->desc->avail_len; 168 if ((wpt & VFF_RING_SIZE) == vff_sz) 169 wpt = (wpt & VFF_RING_WRAP) ^ VFF_RING_WRAP; 170 171 /* Let DMA start moving data */ 172 mtk_uart_apdma_write(c, VFF_WPT, wpt); 173 174 /* HW auto set to 0 when left size >= threshold */ 175 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B); 176 if (!mtk_uart_apdma_read(c, VFF_FLUSH)) 177 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B); 178 } 179 180 static void mtk_uart_apdma_start_rx(struct mtk_chan *c) 181 { 182 struct mtk_uart_apdmadev *mtkd = 183 to_mtk_uart_apdma_dev(c->vc.chan.device); 184 struct mtk_uart_apdma_desc *d = c->desc; 185 unsigned int vff_sz; 186 187 vff_sz = c->cfg.src_port_window_size; 188 if (!mtk_uart_apdma_read(c, VFF_LEN)) { 189 mtk_uart_apdma_write(c, VFF_ADDR, d->addr); 190 mtk_uart_apdma_write(c, VFF_LEN, vff_sz); 191 mtk_uart_apdma_write(c, VFF_THRE, VFF_RX_THRE(vff_sz)); 192 mtk_uart_apdma_write(c, VFF_RPT, 0); 193 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); 194 195 if (mtkd->support_33bits) 196 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B); 197 } 198 199 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B); 200 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B); 201 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B) 202 dev_err(c->vc.chan.device->dev, "Enable RX fail\n"); 203 } 204 205 static void mtk_uart_apdma_tx_handler(struct mtk_chan *c) 206 { 207 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); 208 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B); 209 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B); 210 } 211 212 static void mtk_uart_apdma_rx_handler(struct mtk_chan *c) 213 { 214 struct mtk_uart_apdma_desc *d = c->desc; 215 unsigned int len, wg, rg; 216 int cnt; 217 218 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); 219 220 if (!mtk_uart_apdma_read(c, VFF_VALID_SIZE)) 221 return; 222 223 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B); 224 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B); 225 226 len = c->cfg.src_port_window_size; 227 rg = mtk_uart_apdma_read(c, VFF_RPT); 228 wg = mtk_uart_apdma_read(c, VFF_WPT); 229 cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE); 230 231 /* 232 * The buffer is ring buffer. If wrap bit different, 233 * represents the start of the next cycle for WPT 234 */ 235 if ((rg ^ wg) & VFF_RING_WRAP) 236 cnt += len; 237 238 c->rx_status = d->avail_len - cnt; 239 mtk_uart_apdma_write(c, VFF_RPT, wg); 240 } 241 242 static void mtk_uart_apdma_chan_complete_handler(struct mtk_chan *c) 243 { 244 struct mtk_uart_apdma_desc *d = c->desc; 245 246 if (d) { 247 list_del(&d->vd.node); 248 vchan_cookie_complete(&d->vd); 249 c->desc = NULL; 250 } 251 } 252 253 static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id) 254 { 255 struct dma_chan *chan = (struct dma_chan *)dev_id; 256 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 257 unsigned long flags; 258 259 spin_lock_irqsave(&c->vc.lock, flags); 260 if (c->dir == DMA_DEV_TO_MEM) 261 mtk_uart_apdma_rx_handler(c); 262 else if (c->dir == DMA_MEM_TO_DEV) 263 mtk_uart_apdma_tx_handler(c); 264 mtk_uart_apdma_chan_complete_handler(c); 265 spin_unlock_irqrestore(&c->vc.lock, flags); 266 267 return IRQ_HANDLED; 268 } 269 270 static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan) 271 { 272 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device); 273 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 274 unsigned int status; 275 int ret; 276 277 ret = pm_runtime_get_sync(mtkd->ddev.dev); 278 if (ret < 0) { 279 pm_runtime_put_noidle(chan->device->dev); 280 return ret; 281 } 282 283 mtk_uart_apdma_write(c, VFF_ADDR, 0); 284 mtk_uart_apdma_write(c, VFF_THRE, 0); 285 mtk_uart_apdma_write(c, VFF_LEN, 0); 286 mtk_uart_apdma_write(c, VFF_RST, VFF_WARM_RST_B); 287 288 ret = readx_poll_timeout(readl, c->base + VFF_EN, 289 status, !status, 10, 100); 290 if (ret) 291 return ret; 292 293 ret = request_irq(c->irq, mtk_uart_apdma_irq_handler, 294 IRQF_TRIGGER_NONE, KBUILD_MODNAME, chan); 295 if (ret < 0) { 296 dev_err(chan->device->dev, "Can't request dma IRQ\n"); 297 return -EINVAL; 298 } 299 300 if (mtkd->support_33bits) 301 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B); 302 303 return ret; 304 } 305 306 static void mtk_uart_apdma_free_chan_resources(struct dma_chan *chan) 307 { 308 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device); 309 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 310 311 free_irq(c->irq, chan); 312 313 tasklet_kill(&c->vc.task); 314 315 vchan_free_chan_resources(&c->vc); 316 317 pm_runtime_put_sync(mtkd->ddev.dev); 318 } 319 320 static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan, 321 dma_cookie_t cookie, 322 struct dma_tx_state *txstate) 323 { 324 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 325 enum dma_status ret; 326 327 ret = dma_cookie_status(chan, cookie, txstate); 328 if (!txstate) 329 return ret; 330 331 dma_set_residue(txstate, c->rx_status); 332 333 return ret; 334 } 335 336 /* 337 * dmaengine_prep_slave_single will call the function. and sglen is 1. 338 * 8250 uart using one ring buffer, and deal with one sg. 339 */ 340 static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg 341 (struct dma_chan *chan, struct scatterlist *sgl, 342 unsigned int sglen, enum dma_transfer_direction dir, 343 unsigned long tx_flags, void *context) 344 { 345 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 346 struct mtk_uart_apdma_desc *d; 347 348 if (!is_slave_direction(dir) || sglen != 1) 349 return NULL; 350 351 /* Now allocate and setup the descriptor */ 352 d = kzalloc(sizeof(*d), GFP_NOWAIT); 353 if (!d) 354 return NULL; 355 356 d->avail_len = sg_dma_len(sgl); 357 d->addr = sg_dma_address(sgl); 358 c->dir = dir; 359 360 return vchan_tx_prep(&c->vc, &d->vd, tx_flags); 361 } 362 363 static void mtk_uart_apdma_issue_pending(struct dma_chan *chan) 364 { 365 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 366 struct virt_dma_desc *vd; 367 unsigned long flags; 368 369 spin_lock_irqsave(&c->vc.lock, flags); 370 if (vchan_issue_pending(&c->vc) && !c->desc) { 371 vd = vchan_next_desc(&c->vc); 372 c->desc = to_mtk_uart_apdma_desc(&vd->tx); 373 374 if (c->dir == DMA_DEV_TO_MEM) 375 mtk_uart_apdma_start_rx(c); 376 else if (c->dir == DMA_MEM_TO_DEV) 377 mtk_uart_apdma_start_tx(c); 378 } 379 380 spin_unlock_irqrestore(&c->vc.lock, flags); 381 } 382 383 static int mtk_uart_apdma_slave_config(struct dma_chan *chan, 384 struct dma_slave_config *config) 385 { 386 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 387 388 memcpy(&c->cfg, config, sizeof(*config)); 389 390 return 0; 391 } 392 393 static int mtk_uart_apdma_terminate_all(struct dma_chan *chan) 394 { 395 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 396 unsigned long flags; 397 unsigned int status; 398 LIST_HEAD(head); 399 int ret; 400 401 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B); 402 403 ret = readx_poll_timeout(readl, c->base + VFF_FLUSH, 404 status, status != VFF_FLUSH_B, 10, 100); 405 if (ret) 406 dev_err(c->vc.chan.device->dev, "flush: fail, status=0x%x\n", 407 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS)); 408 409 /* 410 * Stop need 3 steps. 411 * 1. set stop to 1 412 * 2. wait en to 0 413 * 3. set stop as 0 414 */ 415 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_B); 416 ret = readx_poll_timeout(readl, c->base + VFF_EN, 417 status, !status, 10, 100); 418 if (ret) 419 dev_err(c->vc.chan.device->dev, "stop: fail, status=0x%x\n", 420 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS)); 421 422 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_CLR_B); 423 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B); 424 425 if (c->dir == DMA_DEV_TO_MEM) 426 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); 427 else if (c->dir == DMA_MEM_TO_DEV) 428 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); 429 430 synchronize_irq(c->irq); 431 432 spin_lock_irqsave(&c->vc.lock, flags); 433 vchan_get_all_descriptors(&c->vc, &head); 434 spin_unlock_irqrestore(&c->vc.lock, flags); 435 436 vchan_dma_desc_free_list(&c->vc, &head); 437 438 return 0; 439 } 440 441 static int mtk_uart_apdma_device_pause(struct dma_chan *chan) 442 { 443 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); 444 unsigned long flags; 445 446 spin_lock_irqsave(&c->vc.lock, flags); 447 448 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B); 449 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B); 450 451 synchronize_irq(c->irq); 452 453 spin_unlock_irqrestore(&c->vc.lock, flags); 454 455 return 0; 456 } 457 458 static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd) 459 { 460 while (!list_empty(&mtkd->ddev.channels)) { 461 struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels, 462 struct mtk_chan, vc.chan.device_node); 463 464 list_del(&c->vc.chan.device_node); 465 tasklet_kill(&c->vc.task); 466 } 467 } 468 469 static const struct of_device_id mtk_uart_apdma_match[] = { 470 { .compatible = "mediatek,mt6577-uart-dma", }, 471 { /* sentinel */ }, 472 }; 473 MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match); 474 475 static int mtk_uart_apdma_probe(struct platform_device *pdev) 476 { 477 struct device_node *np = pdev->dev.of_node; 478 struct mtk_uart_apdmadev *mtkd; 479 int bit_mask = 32, rc; 480 struct mtk_chan *c; 481 unsigned int i; 482 483 mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL); 484 if (!mtkd) 485 return -ENOMEM; 486 487 mtkd->clk = devm_clk_get(&pdev->dev, NULL); 488 if (IS_ERR(mtkd->clk)) { 489 dev_err(&pdev->dev, "No clock specified\n"); 490 rc = PTR_ERR(mtkd->clk); 491 return rc; 492 } 493 494 if (of_property_read_bool(np, "mediatek,dma-33bits")) 495 mtkd->support_33bits = true; 496 497 if (mtkd->support_33bits) 498 bit_mask = 33; 499 500 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask)); 501 if (rc) 502 return rc; 503 504 dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask); 505 mtkd->ddev.device_alloc_chan_resources = 506 mtk_uart_apdma_alloc_chan_resources; 507 mtkd->ddev.device_free_chan_resources = 508 mtk_uart_apdma_free_chan_resources; 509 mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status; 510 mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending; 511 mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg; 512 mtkd->ddev.device_config = mtk_uart_apdma_slave_config; 513 mtkd->ddev.device_pause = mtk_uart_apdma_device_pause; 514 mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all; 515 mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); 516 mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); 517 mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 518 mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 519 mtkd->ddev.dev = &pdev->dev; 520 INIT_LIST_HEAD(&mtkd->ddev.channels); 521 522 mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS; 523 if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) { 524 dev_info(&pdev->dev, 525 "Using %u as missing dma-requests property\n", 526 MTK_UART_APDMA_NR_VCHANS); 527 } 528 529 for (i = 0; i < mtkd->dma_requests; i++) { 530 c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL); 531 if (!c) { 532 rc = -ENODEV; 533 goto err_no_dma; 534 } 535 536 c->base = devm_platform_ioremap_resource(pdev, i); 537 if (IS_ERR(c->base)) { 538 rc = PTR_ERR(c->base); 539 goto err_no_dma; 540 } 541 c->vc.desc_free = mtk_uart_apdma_desc_free; 542 vchan_init(&c->vc, &mtkd->ddev); 543 544 rc = platform_get_irq(pdev, i); 545 if (rc < 0) 546 goto err_no_dma; 547 c->irq = rc; 548 } 549 550 pm_runtime_enable(&pdev->dev); 551 pm_runtime_set_active(&pdev->dev); 552 553 rc = dma_async_device_register(&mtkd->ddev); 554 if (rc) 555 goto rpm_disable; 556 557 platform_set_drvdata(pdev, mtkd); 558 559 /* Device-tree DMA controller registration */ 560 rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd); 561 if (rc) 562 goto dma_remove; 563 564 return rc; 565 566 dma_remove: 567 dma_async_device_unregister(&mtkd->ddev); 568 rpm_disable: 569 pm_runtime_disable(&pdev->dev); 570 err_no_dma: 571 mtk_uart_apdma_free(mtkd); 572 return rc; 573 } 574 575 static int mtk_uart_apdma_remove(struct platform_device *pdev) 576 { 577 struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev); 578 579 of_dma_controller_free(pdev->dev.of_node); 580 581 mtk_uart_apdma_free(mtkd); 582 583 dma_async_device_unregister(&mtkd->ddev); 584 585 pm_runtime_disable(&pdev->dev); 586 587 return 0; 588 } 589 590 #ifdef CONFIG_PM_SLEEP 591 static int mtk_uart_apdma_suspend(struct device *dev) 592 { 593 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); 594 595 if (!pm_runtime_suspended(dev)) 596 clk_disable_unprepare(mtkd->clk); 597 598 return 0; 599 } 600 601 static int mtk_uart_apdma_resume(struct device *dev) 602 { 603 int ret; 604 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); 605 606 if (!pm_runtime_suspended(dev)) { 607 ret = clk_prepare_enable(mtkd->clk); 608 if (ret) 609 return ret; 610 } 611 612 return 0; 613 } 614 #endif /* CONFIG_PM_SLEEP */ 615 616 #ifdef CONFIG_PM 617 static int mtk_uart_apdma_runtime_suspend(struct device *dev) 618 { 619 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); 620 621 clk_disable_unprepare(mtkd->clk); 622 623 return 0; 624 } 625 626 static int mtk_uart_apdma_runtime_resume(struct device *dev) 627 { 628 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); 629 630 return clk_prepare_enable(mtkd->clk); 631 } 632 #endif /* CONFIG_PM */ 633 634 static const struct dev_pm_ops mtk_uart_apdma_pm_ops = { 635 SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume) 636 SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend, 637 mtk_uart_apdma_runtime_resume, NULL) 638 }; 639 640 static struct platform_driver mtk_uart_apdma_driver = { 641 .probe = mtk_uart_apdma_probe, 642 .remove = mtk_uart_apdma_remove, 643 .driver = { 644 .name = KBUILD_MODNAME, 645 .pm = &mtk_uart_apdma_pm_ops, 646 .of_match_table = of_match_ptr(mtk_uart_apdma_match), 647 }, 648 }; 649 650 module_platform_driver(mtk_uart_apdma_driver); 651 652 MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver"); 653 MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>"); 654 MODULE_LICENSE("GPL v2"); 655