1*ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2548c4597SSean Wang 3548c4597SSean Wangconfig MTK_HSDMA 4548c4597SSean Wang tristate "MediaTek High-Speed DMA controller support" 5548c4597SSean Wang depends on ARCH_MEDIATEK || COMPILE_TEST 6548c4597SSean Wang select DMA_ENGINE 7548c4597SSean Wang select DMA_VIRTUAL_CHANNELS 8548c4597SSean Wang ---help--- 9548c4597SSean Wang Enable support for High-Speed DMA controller on MediaTek 10548c4597SSean Wang SoCs. 11548c4597SSean Wang 12548c4597SSean Wang This controller provides the channels which is dedicated to 13548c4597SSean Wang memory-to-memory transfer to offload from CPU through ring- 14548c4597SSean Wang based descriptor management. 15b1f01e48SShun-Chih Yu 16b1f01e48SShun-Chih Yuconfig MTK_CQDMA 17b1f01e48SShun-Chih Yu tristate "MediaTek Command-Queue DMA controller support" 18b1f01e48SShun-Chih Yu depends on ARCH_MEDIATEK || COMPILE_TEST 19b1f01e48SShun-Chih Yu select DMA_ENGINE 20b1f01e48SShun-Chih Yu select DMA_VIRTUAL_CHANNELS 21b1f01e48SShun-Chih Yu select ASYNC_TX_ENABLE_CHANNEL_SWITCH 22b1f01e48SShun-Chih Yu help 23b1f01e48SShun-Chih Yu Enable support for Command-Queue DMA controller on MediaTek 24b1f01e48SShun-Chih Yu SoCs. 25b1f01e48SShun-Chih Yu 26b1f01e48SShun-Chih Yu This controller provides the channels which is dedicated to 27b1f01e48SShun-Chih Yu memory-to-memory transfer to offload from CPU. 28