xref: /openbmc/linux/drivers/dma/mediatek/Kconfig (revision b1f01e48)
1548c4597SSean Wang
2548c4597SSean Wangconfig MTK_HSDMA
3548c4597SSean Wang	tristate "MediaTek High-Speed DMA controller support"
4548c4597SSean Wang	depends on ARCH_MEDIATEK || COMPILE_TEST
5548c4597SSean Wang	select DMA_ENGINE
6548c4597SSean Wang	select DMA_VIRTUAL_CHANNELS
7548c4597SSean Wang	---help---
8548c4597SSean Wang	  Enable support for High-Speed DMA controller on MediaTek
9548c4597SSean Wang	  SoCs.
10548c4597SSean Wang
11548c4597SSean Wang	  This controller provides the channels which is dedicated to
12548c4597SSean Wang	  memory-to-memory transfer to offload from CPU through ring-
13548c4597SSean Wang	  based descriptor management.
14*b1f01e48SShun-Chih Yu
15*b1f01e48SShun-Chih Yuconfig MTK_CQDMA
16*b1f01e48SShun-Chih Yu	tristate "MediaTek Command-Queue DMA controller support"
17*b1f01e48SShun-Chih Yu	depends on ARCH_MEDIATEK || COMPILE_TEST
18*b1f01e48SShun-Chih Yu	select DMA_ENGINE
19*b1f01e48SShun-Chih Yu	select DMA_VIRTUAL_CHANNELS
20*b1f01e48SShun-Chih Yu	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
21*b1f01e48SShun-Chih Yu	help
22*b1f01e48SShun-Chih Yu	  Enable support for Command-Queue DMA controller on MediaTek
23*b1f01e48SShun-Chih Yu	  SoCs.
24*b1f01e48SShun-Chih Yu
25*b1f01e48SShun-Chih Yu	  This controller provides the channels which is dedicated to
26*b1f01e48SShun-Chih Yu	  memory-to-memory transfer to offload from CPU.
27