1548c4597SSean Wang 2548c4597SSean Wangconfig MTK_HSDMA 3548c4597SSean Wang tristate "MediaTek High-Speed DMA controller support" 4548c4597SSean Wang depends on ARCH_MEDIATEK || COMPILE_TEST 5548c4597SSean Wang select DMA_ENGINE 6548c4597SSean Wang select DMA_VIRTUAL_CHANNELS 7548c4597SSean Wang ---help--- 8548c4597SSean Wang Enable support for High-Speed DMA controller on MediaTek 9548c4597SSean Wang SoCs. 10548c4597SSean Wang 11548c4597SSean Wang This controller provides the channels which is dedicated to 12548c4597SSean Wang memory-to-memory transfer to offload from CPU through ring- 13548c4597SSean Wang based descriptor management. 14b1f01e48SShun-Chih Yu 15b1f01e48SShun-Chih Yuconfig MTK_CQDMA 16b1f01e48SShun-Chih Yu tristate "MediaTek Command-Queue DMA controller support" 17b1f01e48SShun-Chih Yu depends on ARCH_MEDIATEK || COMPILE_TEST 18b1f01e48SShun-Chih Yu select DMA_ENGINE 19b1f01e48SShun-Chih Yu select DMA_VIRTUAL_CHANNELS 20b1f01e48SShun-Chih Yu select ASYNC_TX_ENABLE_CHANNEL_SWITCH 21b1f01e48SShun-Chih Yu help 22b1f01e48SShun-Chih Yu Enable support for Command-Queue DMA controller on MediaTek 23b1f01e48SShun-Chih Yu SoCs. 24b1f01e48SShun-Chih Yu 25b1f01e48SShun-Chih Yu This controller provides the channels which is dedicated to 26b1f01e48SShun-Chih Yu memory-to-memory transfer to offload from CPU. 27*9135408cSLong Cheng 28*9135408cSLong Chengconfig MTK_UART_APDMA 29*9135408cSLong Cheng tristate "MediaTek SoCs APDMA support for UART" 30*9135408cSLong Cheng depends on OF && SERIAL_8250_MT6577 31*9135408cSLong Cheng select DMA_ENGINE 32*9135408cSLong Cheng select DMA_VIRTUAL_CHANNELS 33*9135408cSLong Cheng help 34*9135408cSLong Cheng Support for the UART DMA engine found on MediaTek MTK SoCs. 35*9135408cSLong Cheng When SERIAL_8250_MT6577 is enabled, and if you want to use DMA, 36*9135408cSLong Cheng you can enable the config. The DMA engine can only be used 37*9135408cSLong Cheng with MediaTek SoCs. 38