1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef _IOAT_REGISTERS_H_ 18 #define _IOAT_REGISTERS_H_ 19 20 #define IOAT_PCI_DMACTRL_OFFSET 0x48 21 #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 22 #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 23 24 #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 25 #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 26 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 27 #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 28 29 /* MMIO Device Registers */ 30 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 31 32 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 33 #define IOAT_XFERCAP_4KB 12 34 #define IOAT_XFERCAP_8KB 13 35 #define IOAT_XFERCAP_16KB 14 36 #define IOAT_XFERCAP_32KB 15 37 #define IOAT_XFERCAP_32GB 0 38 39 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 40 #define IOAT_GENCTRL_DEBUG_EN 0x01 41 42 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 43 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 44 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 45 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 46 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 47 48 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 49 50 #define IOAT_VER_OFFSET 0x08 /* 8-bit */ 51 #define IOAT_VER_MAJOR_MASK 0xF0 52 #define IOAT_VER_MINOR_MASK 0x0F 53 #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 54 #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 55 56 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 57 58 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 59 #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 60 #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 61 62 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 63 #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 64 #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 65 #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 66 #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 67 68 #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 69 #define IOAT_CAP_PAGE_BREAK 0x00000001 70 #define IOAT_CAP_CRC 0x00000002 71 #define IOAT_CAP_SKIP_MARKER 0x00000004 72 #define IOAT_CAP_DCA 0x00000010 73 #define IOAT_CAP_CRC_MOVE 0x00000020 74 #define IOAT_CAP_FILL_BLOCK 0x00000040 75 #define IOAT_CAP_APIC 0x00000080 76 #define IOAT_CAP_XOR 0x00000100 77 #define IOAT_CAP_PQ 0x00000200 78 #define IOAT_CAP_DWBES 0x00002000 79 #define IOAT_CAP_RAID16SS 0x00020000 80 81 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 82 83 /* DMA Channel Registers */ 84 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 85 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 86 #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 87 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 88 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 89 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 90 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 91 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 92 #define IOAT_CHANCTRL_INT_REARM 0x0001 93 #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 94 IOAT_CHANCTRL_ERR_INT_EN |\ 95 IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 96 IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 97 98 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 99 #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 100 #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 101 102 /* IOAT1 define left for i7300_idle driver to not fail compiling */ 103 #define IOAT1_CHANSTS_OFFSET 0x04 104 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 105 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 106 #define IOAT_CHANSTS_SOFT_ERR 0x10ULL 107 #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 108 #define IOAT_CHANSTS_STATUS 0x7ULL 109 #define IOAT_CHANSTS_ACTIVE 0x0 110 #define IOAT_CHANSTS_DONE 0x1 111 #define IOAT_CHANSTS_SUSPENDED 0x2 112 #define IOAT_CHANSTS_HALTED 0x3 113 114 115 116 #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 117 118 #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 119 #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 120 #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 121 122 /* CB DCA Memory Space Registers */ 123 #define IOAT_DCAOFFSET_OFFSET 0x14 124 /* CB_BAR + IOAT_DCAOFFSET value */ 125 #define IOAT_DCA_VER_OFFSET 0x00 126 #define IOAT_DCA_VER_MAJOR_MASK 0xF0 127 #define IOAT_DCA_VER_MINOR_MASK 0x0F 128 129 #define IOAT_DCA_COMP_OFFSET 0x02 130 #define IOAT_DCA_COMP_V1 0x1 131 132 #define IOAT_FSB_CAPABILITY_OFFSET 0x04 133 #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 134 135 #define IOAT_PCI_CAPABILITY_OFFSET 0x06 136 #define IOAT_PCI_CAPABILITY_MEMWR 0x1 137 138 #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 139 #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 140 141 #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 142 #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 143 144 #define IOAT_APICID_TAG_MAP_OFFSET 0x0C 145 #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 146 #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 147 #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 148 #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 149 #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 150 #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 151 #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 152 #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 153 #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 154 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 155 #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 156 157 #define IOAT_DCA_GREQID_OFFSET 0x10 158 #define IOAT_DCA_GREQID_SIZE 0x04 159 #define IOAT_DCA_GREQID_MASK 0xFFFF 160 #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 161 #define IOAT_DCA_GREQID_VALID 0x20000000 162 #define IOAT_DCA_GREQID_LASTID 0x80000000 163 164 #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 165 #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 166 167 #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 168 #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 169 170 #define IOAT3_CSI_CONTROL_OFFSET 0x0C 171 #define IOAT3_CSI_CONTROL_PREFETCH 0x1 172 173 #define IOAT3_PCI_CONTROL_OFFSET 0x0E 174 #define IOAT3_PCI_CONTROL_MEMWR 0x1 175 176 #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 177 #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 178 #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 179 180 #define IOAT3_DCA_GREQID_OFFSET 0x02 181 182 #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 183 #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 184 #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 185 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 186 #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 187 #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 188 #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 189 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 190 #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 191 #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 192 #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 193 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 194 195 #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 196 #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 197 #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 198 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 199 #define IOAT_CHANCMD_RESET 0x20 200 #define IOAT_CHANCMD_RESUME 0x10 201 #define IOAT_CHANCMD_ABORT 0x08 202 #define IOAT_CHANCMD_SUSPEND 0x04 203 #define IOAT_CHANCMD_APPEND 0x02 204 #define IOAT_CHANCMD_START 0x01 205 206 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 207 #define IOAT_CHANCMP_OFFSET_LOW 0x18 208 #define IOAT_CHANCMP_OFFSET_HIGH 0x1C 209 210 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 211 #define IOAT_CDAR_OFFSET_LOW 0x20 212 #define IOAT_CDAR_OFFSET_HIGH 0x24 213 214 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 215 #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 216 #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 217 #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 218 #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 219 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 220 #define IOAT_CHANERR_CHANCMD_ERR 0x0020 221 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 222 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 223 #define IOAT_CHANERR_READ_DATA_ERR 0x0100 224 #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 225 #define IOAT_CHANERR_CONTROL_ERR 0x0400 226 #define IOAT_CHANERR_LENGTH_ERR 0x0800 227 #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 228 #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 229 #define IOAT_CHANERR_SOFT_ERR 0x4000 230 #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 231 #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 232 #define IOAT_CHANERR_XOR_Q_ERR 0x20000 233 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 234 235 #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 236 237 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 238 239 #endif /* _IOAT_REGISTERS_H_ */ 240