1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include <linux/aer.h> 31 #include <linux/sizes.h> 32 #include "dma.h" 33 #include "registers.h" 34 #include "hw.h" 35 36 #include "../dmaengine.h" 37 38 MODULE_VERSION(IOAT_DMA_VERSION); 39 MODULE_LICENSE("Dual BSD/GPL"); 40 MODULE_AUTHOR("Intel Corporation"); 41 42 static const struct pci_device_id ioat_pci_tbl[] = { 43 /* I/OAT v3 platforms */ 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 52 53 /* I/OAT v3.2 platforms */ 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 64 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 75 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 86 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 97 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 108 109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 110 111 /* I/OAT v3.3 platforms */ 112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 116 117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 121 122 /* I/OAT v3.4 platforms */ 123 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) }, 124 125 { 0, } 126 }; 127 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 128 129 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 130 static void ioat_remove(struct pci_dev *pdev); 131 static void 132 ioat_init_channel(struct ioatdma_device *ioat_dma, 133 struct ioatdma_chan *ioat_chan, int idx); 134 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 135 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 136 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 137 138 static int ioat_dca_enabled = 1; 139 module_param(ioat_dca_enabled, int, 0644); 140 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 141 int ioat_pending_level = 7; 142 module_param(ioat_pending_level, int, 0644); 143 MODULE_PARM_DESC(ioat_pending_level, 144 "high-water mark for pushing ioat descriptors (default: 7)"); 145 static char ioat_interrupt_style[32] = "msix"; 146 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 147 sizeof(ioat_interrupt_style), 0644); 148 MODULE_PARM_DESC(ioat_interrupt_style, 149 "set ioat interrupt style: msix (default), msi, intx"); 150 151 struct kmem_cache *ioat_cache; 152 struct kmem_cache *ioat_sed_cache; 153 154 static bool is_jf_ioat(struct pci_dev *pdev) 155 { 156 switch (pdev->device) { 157 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 158 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 159 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 160 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 161 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 162 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 163 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 164 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 165 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 166 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 167 return true; 168 default: 169 return false; 170 } 171 } 172 173 static bool is_snb_ioat(struct pci_dev *pdev) 174 { 175 switch (pdev->device) { 176 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 177 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 178 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 179 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 180 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 181 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 182 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 183 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 184 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 185 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 186 return true; 187 default: 188 return false; 189 } 190 } 191 192 static bool is_ivb_ioat(struct pci_dev *pdev) 193 { 194 switch (pdev->device) { 195 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 196 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 197 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 198 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 199 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 200 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 201 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 202 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 203 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 204 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 205 return true; 206 default: 207 return false; 208 } 209 210 } 211 212 static bool is_hsw_ioat(struct pci_dev *pdev) 213 { 214 switch (pdev->device) { 215 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 216 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 217 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 218 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 219 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 220 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 221 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 222 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 223 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 224 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 225 return true; 226 default: 227 return false; 228 } 229 230 } 231 232 static bool is_bdx_ioat(struct pci_dev *pdev) 233 { 234 switch (pdev->device) { 235 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 236 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 237 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 238 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 239 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 240 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 241 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 242 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 243 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 244 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 245 return true; 246 default: 247 return false; 248 } 249 } 250 251 static inline bool is_skx_ioat(struct pci_dev *pdev) 252 { 253 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 254 } 255 256 static bool is_xeon_cb32(struct pci_dev *pdev) 257 { 258 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 259 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 260 } 261 262 bool is_bwd_ioat(struct pci_dev *pdev) 263 { 264 switch (pdev->device) { 265 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 266 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 267 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 268 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 269 /* even though not Atom, BDX-DE has same DMA silicon */ 270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 271 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 272 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 274 return true; 275 default: 276 return false; 277 } 278 } 279 280 static bool is_bwd_noraid(struct pci_dev *pdev) 281 { 282 switch (pdev->device) { 283 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 284 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 286 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 287 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 288 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 289 return true; 290 default: 291 return false; 292 } 293 294 } 295 296 /* 297 * Perform a IOAT transaction to verify the HW works. 298 */ 299 #define IOAT_TEST_SIZE 2000 300 301 static void ioat_dma_test_callback(void *dma_async_param) 302 { 303 struct completion *cmp = dma_async_param; 304 305 complete(cmp); 306 } 307 308 /** 309 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 310 * @ioat_dma: dma device to be tested 311 */ 312 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 313 { 314 int i; 315 u8 *src; 316 u8 *dest; 317 struct dma_device *dma = &ioat_dma->dma_dev; 318 struct device *dev = &ioat_dma->pdev->dev; 319 struct dma_chan *dma_chan; 320 struct dma_async_tx_descriptor *tx; 321 dma_addr_t dma_dest, dma_src; 322 dma_cookie_t cookie; 323 int err = 0; 324 struct completion cmp; 325 unsigned long tmo; 326 unsigned long flags; 327 328 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 329 if (!src) 330 return -ENOMEM; 331 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 332 if (!dest) { 333 kfree(src); 334 return -ENOMEM; 335 } 336 337 /* Fill in src buffer */ 338 for (i = 0; i < IOAT_TEST_SIZE; i++) 339 src[i] = (u8)i; 340 341 /* Start copy, using first DMA channel */ 342 dma_chan = container_of(dma->channels.next, struct dma_chan, 343 device_node); 344 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 345 dev_err(dev, "selftest cannot allocate chan resource\n"); 346 err = -ENODEV; 347 goto out; 348 } 349 350 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 351 if (dma_mapping_error(dev, dma_src)) { 352 dev_err(dev, "mapping src buffer failed\n"); 353 err = -ENOMEM; 354 goto free_resources; 355 } 356 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 357 if (dma_mapping_error(dev, dma_dest)) { 358 dev_err(dev, "mapping dest buffer failed\n"); 359 err = -ENOMEM; 360 goto unmap_src; 361 } 362 flags = DMA_PREP_INTERRUPT; 363 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 364 dma_src, IOAT_TEST_SIZE, 365 flags); 366 if (!tx) { 367 dev_err(dev, "Self-test prep failed, disabling\n"); 368 err = -ENODEV; 369 goto unmap_dma; 370 } 371 372 async_tx_ack(tx); 373 init_completion(&cmp); 374 tx->callback = ioat_dma_test_callback; 375 tx->callback_param = &cmp; 376 cookie = tx->tx_submit(tx); 377 if (cookie < 0) { 378 dev_err(dev, "Self-test setup failed, disabling\n"); 379 err = -ENODEV; 380 goto unmap_dma; 381 } 382 dma->device_issue_pending(dma_chan); 383 384 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 385 386 if (tmo == 0 || 387 dma->device_tx_status(dma_chan, cookie, NULL) 388 != DMA_COMPLETE) { 389 dev_err(dev, "Self-test copy timed out, disabling\n"); 390 err = -ENODEV; 391 goto unmap_dma; 392 } 393 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 394 dev_err(dev, "Self-test copy failed compare, disabling\n"); 395 err = -ENODEV; 396 goto unmap_dma; 397 } 398 399 unmap_dma: 400 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 401 unmap_src: 402 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 403 free_resources: 404 dma->device_free_chan_resources(dma_chan); 405 out: 406 kfree(src); 407 kfree(dest); 408 return err; 409 } 410 411 /** 412 * ioat_dma_setup_interrupts - setup interrupt handler 413 * @ioat_dma: ioat dma device 414 */ 415 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 416 { 417 struct ioatdma_chan *ioat_chan; 418 struct pci_dev *pdev = ioat_dma->pdev; 419 struct device *dev = &pdev->dev; 420 struct msix_entry *msix; 421 int i, j, msixcnt; 422 int err = -EINVAL; 423 u8 intrctrl = 0; 424 425 if (!strcmp(ioat_interrupt_style, "msix")) 426 goto msix; 427 if (!strcmp(ioat_interrupt_style, "msi")) 428 goto msi; 429 if (!strcmp(ioat_interrupt_style, "intx")) 430 goto intx; 431 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 432 goto err_no_irq; 433 434 msix: 435 /* The number of MSI-X vectors should equal the number of channels */ 436 msixcnt = ioat_dma->dma_dev.chancnt; 437 for (i = 0; i < msixcnt; i++) 438 ioat_dma->msix_entries[i].entry = i; 439 440 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 441 if (err) 442 goto msi; 443 444 for (i = 0; i < msixcnt; i++) { 445 msix = &ioat_dma->msix_entries[i]; 446 ioat_chan = ioat_chan_by_index(ioat_dma, i); 447 err = devm_request_irq(dev, msix->vector, 448 ioat_dma_do_interrupt_msix, 0, 449 "ioat-msix", ioat_chan); 450 if (err) { 451 for (j = 0; j < i; j++) { 452 msix = &ioat_dma->msix_entries[j]; 453 ioat_chan = ioat_chan_by_index(ioat_dma, j); 454 devm_free_irq(dev, msix->vector, ioat_chan); 455 } 456 goto msi; 457 } 458 } 459 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 460 ioat_dma->irq_mode = IOAT_MSIX; 461 goto done; 462 463 msi: 464 err = pci_enable_msi(pdev); 465 if (err) 466 goto intx; 467 468 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 469 "ioat-msi", ioat_dma); 470 if (err) { 471 pci_disable_msi(pdev); 472 goto intx; 473 } 474 ioat_dma->irq_mode = IOAT_MSI; 475 goto done; 476 477 intx: 478 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 479 IRQF_SHARED, "ioat-intx", ioat_dma); 480 if (err) 481 goto err_no_irq; 482 483 ioat_dma->irq_mode = IOAT_INTX; 484 done: 485 if (is_bwd_ioat(pdev)) 486 ioat_intr_quirk(ioat_dma); 487 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 488 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 489 return 0; 490 491 err_no_irq: 492 /* Disable all interrupt generation */ 493 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 494 ioat_dma->irq_mode = IOAT_NOIRQ; 495 dev_err(dev, "no usable interrupts\n"); 496 return err; 497 } 498 499 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 500 { 501 /* Disable all interrupt generation */ 502 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 503 } 504 505 static int ioat_probe(struct ioatdma_device *ioat_dma) 506 { 507 int err = -ENODEV; 508 struct dma_device *dma = &ioat_dma->dma_dev; 509 struct pci_dev *pdev = ioat_dma->pdev; 510 struct device *dev = &pdev->dev; 511 512 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, 513 sizeof(u64), 514 SMP_CACHE_BYTES, 515 SMP_CACHE_BYTES); 516 517 if (!ioat_dma->completion_pool) { 518 err = -ENOMEM; 519 goto err_out; 520 } 521 522 ioat_enumerate_channels(ioat_dma); 523 524 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 525 dma->dev = &pdev->dev; 526 527 if (!dma->chancnt) { 528 dev_err(dev, "channel enumeration error\n"); 529 goto err_setup_interrupts; 530 } 531 532 err = ioat_dma_setup_interrupts(ioat_dma); 533 if (err) 534 goto err_setup_interrupts; 535 536 err = ioat3_dma_self_test(ioat_dma); 537 if (err) 538 goto err_self_test; 539 540 return 0; 541 542 err_self_test: 543 ioat_disable_interrupts(ioat_dma); 544 err_setup_interrupts: 545 dma_pool_destroy(ioat_dma->completion_pool); 546 err_out: 547 return err; 548 } 549 550 static int ioat_register(struct ioatdma_device *ioat_dma) 551 { 552 int err = dma_async_device_register(&ioat_dma->dma_dev); 553 554 if (err) { 555 ioat_disable_interrupts(ioat_dma); 556 dma_pool_destroy(ioat_dma->completion_pool); 557 } 558 559 return err; 560 } 561 562 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 563 { 564 struct dma_device *dma = &ioat_dma->dma_dev; 565 566 ioat_disable_interrupts(ioat_dma); 567 568 ioat_kobject_del(ioat_dma); 569 570 dma_async_device_unregister(dma); 571 572 dma_pool_destroy(ioat_dma->completion_pool); 573 574 INIT_LIST_HEAD(&dma->channels); 575 } 576 577 /** 578 * ioat_enumerate_channels - find and initialize the device's channels 579 * @ioat_dma: the ioat dma device to be enumerated 580 */ 581 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 582 { 583 struct ioatdma_chan *ioat_chan; 584 struct device *dev = &ioat_dma->pdev->dev; 585 struct dma_device *dma = &ioat_dma->dma_dev; 586 u8 xfercap_log; 587 int i; 588 589 INIT_LIST_HEAD(&dma->channels); 590 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 591 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 592 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 593 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 594 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 595 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 596 } 597 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 598 xfercap_log &= 0x1f; /* bits [4:0] valid */ 599 if (xfercap_log == 0) 600 return; 601 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 602 603 for (i = 0; i < dma->chancnt; i++) { 604 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 605 if (!ioat_chan) 606 break; 607 608 ioat_init_channel(ioat_dma, ioat_chan, i); 609 ioat_chan->xfercap_log = xfercap_log; 610 spin_lock_init(&ioat_chan->prep_lock); 611 if (ioat_reset_hw(ioat_chan)) { 612 i = 0; 613 break; 614 } 615 } 616 dma->chancnt = i; 617 } 618 619 /** 620 * ioat_free_chan_resources - release all the descriptors 621 * @chan: the channel to be cleaned 622 */ 623 static void ioat_free_chan_resources(struct dma_chan *c) 624 { 625 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 626 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 627 struct ioat_ring_ent *desc; 628 const int total_descs = 1 << ioat_chan->alloc_order; 629 int descs; 630 int i; 631 632 /* Before freeing channel resources first check 633 * if they have been previously allocated for this channel. 634 */ 635 if (!ioat_chan->ring) 636 return; 637 638 ioat_stop(ioat_chan); 639 ioat_reset_hw(ioat_chan); 640 641 /* Put LTR to idle */ 642 if (ioat_dma->version >= IOAT_VER_3_4) 643 writeb(IOAT_CHAN_LTR_SWSEL_IDLE, 644 ioat_chan->reg_base + IOAT_CHAN_LTR_SWSEL_OFFSET); 645 646 spin_lock_bh(&ioat_chan->cleanup_lock); 647 spin_lock_bh(&ioat_chan->prep_lock); 648 descs = ioat_ring_space(ioat_chan); 649 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 650 for (i = 0; i < descs; i++) { 651 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 652 ioat_free_ring_ent(desc, c); 653 } 654 655 if (descs < total_descs) 656 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 657 total_descs - descs); 658 659 for (i = 0; i < total_descs - descs; i++) { 660 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 661 dump_desc_dbg(ioat_chan, desc); 662 ioat_free_ring_ent(desc, c); 663 } 664 665 for (i = 0; i < ioat_chan->desc_chunks; i++) { 666 dma_free_coherent(to_dev(ioat_chan), SZ_2M, 667 ioat_chan->descs[i].virt, 668 ioat_chan->descs[i].hw); 669 ioat_chan->descs[i].virt = NULL; 670 ioat_chan->descs[i].hw = 0; 671 } 672 ioat_chan->desc_chunks = 0; 673 674 kfree(ioat_chan->ring); 675 ioat_chan->ring = NULL; 676 ioat_chan->alloc_order = 0; 677 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 678 ioat_chan->completion_dma); 679 spin_unlock_bh(&ioat_chan->prep_lock); 680 spin_unlock_bh(&ioat_chan->cleanup_lock); 681 682 ioat_chan->last_completion = 0; 683 ioat_chan->completion_dma = 0; 684 ioat_chan->dmacount = 0; 685 } 686 687 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 688 * @chan: channel to be initialized 689 */ 690 static int ioat_alloc_chan_resources(struct dma_chan *c) 691 { 692 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 693 struct ioat_ring_ent **ring; 694 u64 status; 695 int order; 696 int i = 0; 697 u32 chanerr; 698 699 /* have we already been set up? */ 700 if (ioat_chan->ring) 701 return 1 << ioat_chan->alloc_order; 702 703 /* Setup register to interrupt and write completion status on error */ 704 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 705 706 /* allocate a completion writeback area */ 707 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 708 ioat_chan->completion = 709 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 710 GFP_NOWAIT, &ioat_chan->completion_dma); 711 if (!ioat_chan->completion) 712 return -ENOMEM; 713 714 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 715 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 716 writel(((u64)ioat_chan->completion_dma) >> 32, 717 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 718 719 order = IOAT_MAX_ORDER; 720 ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 721 if (!ring) 722 return -ENOMEM; 723 724 spin_lock_bh(&ioat_chan->cleanup_lock); 725 spin_lock_bh(&ioat_chan->prep_lock); 726 ioat_chan->ring = ring; 727 ioat_chan->head = 0; 728 ioat_chan->issued = 0; 729 ioat_chan->tail = 0; 730 ioat_chan->alloc_order = order; 731 set_bit(IOAT_RUN, &ioat_chan->state); 732 spin_unlock_bh(&ioat_chan->prep_lock); 733 spin_unlock_bh(&ioat_chan->cleanup_lock); 734 735 /* Setting up LTR values for 3.4 or later */ 736 if (ioat_chan->ioat_dma->version >= IOAT_VER_3_4) { 737 u32 lat_val; 738 739 lat_val = IOAT_CHAN_LTR_ACTIVE_SNVAL | 740 IOAT_CHAN_LTR_ACTIVE_SNLATSCALE | 741 IOAT_CHAN_LTR_ACTIVE_SNREQMNT; 742 writel(lat_val, ioat_chan->reg_base + 743 IOAT_CHAN_LTR_ACTIVE_OFFSET); 744 745 lat_val = IOAT_CHAN_LTR_IDLE_SNVAL | 746 IOAT_CHAN_LTR_IDLE_SNLATSCALE | 747 IOAT_CHAN_LTR_IDLE_SNREQMNT; 748 writel(lat_val, ioat_chan->reg_base + 749 IOAT_CHAN_LTR_IDLE_OFFSET); 750 751 /* Select to active */ 752 writeb(IOAT_CHAN_LTR_SWSEL_ACTIVE, 753 ioat_chan->reg_base + 754 IOAT_CHAN_LTR_SWSEL_OFFSET); 755 } 756 757 ioat_start_null_desc(ioat_chan); 758 759 /* check that we got off the ground */ 760 do { 761 udelay(1); 762 status = ioat_chansts(ioat_chan); 763 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 764 765 if (is_ioat_active(status) || is_ioat_idle(status)) 766 return 1 << ioat_chan->alloc_order; 767 768 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 769 770 dev_WARN(to_dev(ioat_chan), 771 "failed to start channel chanerr: %#x\n", chanerr); 772 ioat_free_chan_resources(c); 773 return -EFAULT; 774 } 775 776 /* common channel initialization */ 777 static void 778 ioat_init_channel(struct ioatdma_device *ioat_dma, 779 struct ioatdma_chan *ioat_chan, int idx) 780 { 781 struct dma_device *dma = &ioat_dma->dma_dev; 782 struct dma_chan *c = &ioat_chan->dma_chan; 783 unsigned long data = (unsigned long) c; 784 785 ioat_chan->ioat_dma = ioat_dma; 786 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 787 spin_lock_init(&ioat_chan->cleanup_lock); 788 ioat_chan->dma_chan.device = dma; 789 dma_cookie_init(&ioat_chan->dma_chan); 790 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 791 ioat_dma->idx[idx] = ioat_chan; 792 timer_setup(&ioat_chan->timer, ioat_timer_event, 0); 793 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); 794 } 795 796 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 797 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 798 { 799 int i, src_idx; 800 struct page *dest; 801 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 802 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 803 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 804 dma_addr_t dest_dma; 805 struct dma_async_tx_descriptor *tx; 806 struct dma_chan *dma_chan; 807 dma_cookie_t cookie; 808 u8 cmp_byte = 0; 809 u32 cmp_word; 810 u32 xor_val_result; 811 int err = 0; 812 struct completion cmp; 813 unsigned long tmo; 814 struct device *dev = &ioat_dma->pdev->dev; 815 struct dma_device *dma = &ioat_dma->dma_dev; 816 u8 op = 0; 817 818 dev_dbg(dev, "%s\n", __func__); 819 820 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 821 return 0; 822 823 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 824 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 825 if (!xor_srcs[src_idx]) { 826 while (src_idx--) 827 __free_page(xor_srcs[src_idx]); 828 return -ENOMEM; 829 } 830 } 831 832 dest = alloc_page(GFP_KERNEL); 833 if (!dest) { 834 while (src_idx--) 835 __free_page(xor_srcs[src_idx]); 836 return -ENOMEM; 837 } 838 839 /* Fill in src buffers */ 840 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 841 u8 *ptr = page_address(xor_srcs[src_idx]); 842 843 for (i = 0; i < PAGE_SIZE; i++) 844 ptr[i] = (1 << src_idx); 845 } 846 847 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 848 cmp_byte ^= (u8) (1 << src_idx); 849 850 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 851 (cmp_byte << 8) | cmp_byte; 852 853 memset(page_address(dest), 0, PAGE_SIZE); 854 855 dma_chan = container_of(dma->channels.next, struct dma_chan, 856 device_node); 857 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 858 err = -ENODEV; 859 goto out; 860 } 861 862 /* test xor */ 863 op = IOAT_OP_XOR; 864 865 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 866 if (dma_mapping_error(dev, dest_dma)) { 867 err = -ENOMEM; 868 goto free_resources; 869 } 870 871 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 872 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 873 DMA_TO_DEVICE); 874 if (dma_mapping_error(dev, dma_srcs[i])) { 875 err = -ENOMEM; 876 goto dma_unmap; 877 } 878 } 879 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 880 IOAT_NUM_SRC_TEST, PAGE_SIZE, 881 DMA_PREP_INTERRUPT); 882 883 if (!tx) { 884 dev_err(dev, "Self-test xor prep failed\n"); 885 err = -ENODEV; 886 goto dma_unmap; 887 } 888 889 async_tx_ack(tx); 890 init_completion(&cmp); 891 tx->callback = ioat_dma_test_callback; 892 tx->callback_param = &cmp; 893 cookie = tx->tx_submit(tx); 894 if (cookie < 0) { 895 dev_err(dev, "Self-test xor setup failed\n"); 896 err = -ENODEV; 897 goto dma_unmap; 898 } 899 dma->device_issue_pending(dma_chan); 900 901 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 902 903 if (tmo == 0 || 904 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 905 dev_err(dev, "Self-test xor timed out\n"); 906 err = -ENODEV; 907 goto dma_unmap; 908 } 909 910 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 911 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 912 913 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 914 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 915 u32 *ptr = page_address(dest); 916 917 if (ptr[i] != cmp_word) { 918 dev_err(dev, "Self-test xor failed compare\n"); 919 err = -ENODEV; 920 goto free_resources; 921 } 922 } 923 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 924 925 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 926 927 /* skip validate if the capability is not present */ 928 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 929 goto free_resources; 930 931 op = IOAT_OP_XOR_VAL; 932 933 /* validate the sources with the destintation page */ 934 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 935 xor_val_srcs[i] = xor_srcs[i]; 936 xor_val_srcs[i] = dest; 937 938 xor_val_result = 1; 939 940 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 941 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 942 DMA_TO_DEVICE); 943 if (dma_mapping_error(dev, dma_srcs[i])) { 944 err = -ENOMEM; 945 goto dma_unmap; 946 } 947 } 948 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 949 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 950 &xor_val_result, DMA_PREP_INTERRUPT); 951 if (!tx) { 952 dev_err(dev, "Self-test zero prep failed\n"); 953 err = -ENODEV; 954 goto dma_unmap; 955 } 956 957 async_tx_ack(tx); 958 init_completion(&cmp); 959 tx->callback = ioat_dma_test_callback; 960 tx->callback_param = &cmp; 961 cookie = tx->tx_submit(tx); 962 if (cookie < 0) { 963 dev_err(dev, "Self-test zero setup failed\n"); 964 err = -ENODEV; 965 goto dma_unmap; 966 } 967 dma->device_issue_pending(dma_chan); 968 969 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 970 971 if (tmo == 0 || 972 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 973 dev_err(dev, "Self-test validate timed out\n"); 974 err = -ENODEV; 975 goto dma_unmap; 976 } 977 978 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 979 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 980 981 if (xor_val_result != 0) { 982 dev_err(dev, "Self-test validate failed compare\n"); 983 err = -ENODEV; 984 goto free_resources; 985 } 986 987 memset(page_address(dest), 0, PAGE_SIZE); 988 989 /* test for non-zero parity sum */ 990 op = IOAT_OP_XOR_VAL; 991 992 xor_val_result = 0; 993 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 994 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 995 DMA_TO_DEVICE); 996 if (dma_mapping_error(dev, dma_srcs[i])) { 997 err = -ENOMEM; 998 goto dma_unmap; 999 } 1000 } 1001 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 1002 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 1003 &xor_val_result, DMA_PREP_INTERRUPT); 1004 if (!tx) { 1005 dev_err(dev, "Self-test 2nd zero prep failed\n"); 1006 err = -ENODEV; 1007 goto dma_unmap; 1008 } 1009 1010 async_tx_ack(tx); 1011 init_completion(&cmp); 1012 tx->callback = ioat_dma_test_callback; 1013 tx->callback_param = &cmp; 1014 cookie = tx->tx_submit(tx); 1015 if (cookie < 0) { 1016 dev_err(dev, "Self-test 2nd zero setup failed\n"); 1017 err = -ENODEV; 1018 goto dma_unmap; 1019 } 1020 dma->device_issue_pending(dma_chan); 1021 1022 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 1023 1024 if (tmo == 0 || 1025 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 1026 dev_err(dev, "Self-test 2nd validate timed out\n"); 1027 err = -ENODEV; 1028 goto dma_unmap; 1029 } 1030 1031 if (xor_val_result != SUM_CHECK_P_RESULT) { 1032 dev_err(dev, "Self-test validate failed compare\n"); 1033 err = -ENODEV; 1034 goto dma_unmap; 1035 } 1036 1037 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1038 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1039 1040 goto free_resources; 1041 dma_unmap: 1042 if (op == IOAT_OP_XOR) { 1043 while (--i >= 0) 1044 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1045 DMA_TO_DEVICE); 1046 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 1047 } else if (op == IOAT_OP_XOR_VAL) { 1048 while (--i >= 0) 1049 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1050 DMA_TO_DEVICE); 1051 } 1052 free_resources: 1053 dma->device_free_chan_resources(dma_chan); 1054 out: 1055 src_idx = IOAT_NUM_SRC_TEST; 1056 while (src_idx--) 1057 __free_page(xor_srcs[src_idx]); 1058 __free_page(dest); 1059 return err; 1060 } 1061 1062 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1063 { 1064 int rc; 1065 1066 rc = ioat_dma_self_test(ioat_dma); 1067 if (rc) 1068 return rc; 1069 1070 rc = ioat_xor_val_self_test(ioat_dma); 1071 1072 return rc; 1073 } 1074 1075 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1076 { 1077 struct dma_device *dma; 1078 struct dma_chan *c; 1079 struct ioatdma_chan *ioat_chan; 1080 u32 errmask; 1081 1082 dma = &ioat_dma->dma_dev; 1083 1084 /* 1085 * if we have descriptor write back error status, we mask the 1086 * error interrupts 1087 */ 1088 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1089 list_for_each_entry(c, &dma->channels, device_node) { 1090 ioat_chan = to_ioat_chan(c); 1091 errmask = readl(ioat_chan->reg_base + 1092 IOAT_CHANERR_MASK_OFFSET); 1093 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1094 IOAT_CHANERR_XOR_Q_ERR; 1095 writel(errmask, ioat_chan->reg_base + 1096 IOAT_CHANERR_MASK_OFFSET); 1097 } 1098 } 1099 } 1100 1101 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1102 { 1103 struct pci_dev *pdev = ioat_dma->pdev; 1104 int dca_en = system_has_dca_enabled(pdev); 1105 struct dma_device *dma; 1106 struct dma_chan *c; 1107 struct ioatdma_chan *ioat_chan; 1108 int err; 1109 u16 val16; 1110 1111 dma = &ioat_dma->dma_dev; 1112 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1113 dma->device_issue_pending = ioat_issue_pending; 1114 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1115 dma->device_free_chan_resources = ioat_free_chan_resources; 1116 1117 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1118 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1119 1120 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1121 1122 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1123 ioat_dma->cap &= 1124 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1125 1126 /* dca is incompatible with raid operations */ 1127 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1128 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1129 1130 if (ioat_dma->cap & IOAT_CAP_XOR) { 1131 dma->max_xor = 8; 1132 1133 dma_cap_set(DMA_XOR, dma->cap_mask); 1134 dma->device_prep_dma_xor = ioat_prep_xor; 1135 1136 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1137 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1138 } 1139 1140 if (ioat_dma->cap & IOAT_CAP_PQ) { 1141 1142 dma->device_prep_dma_pq = ioat_prep_pq; 1143 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1144 dma_cap_set(DMA_PQ, dma->cap_mask); 1145 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1146 1147 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1148 dma_set_maxpq(dma, 16, 0); 1149 else 1150 dma_set_maxpq(dma, 8, 0); 1151 1152 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1153 dma->device_prep_dma_xor = ioat_prep_pqxor; 1154 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1155 dma_cap_set(DMA_XOR, dma->cap_mask); 1156 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1157 1158 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1159 dma->max_xor = 16; 1160 else 1161 dma->max_xor = 8; 1162 } 1163 } 1164 1165 dma->device_tx_status = ioat_tx_status; 1166 1167 /* starting with CB3.3 super extended descriptors are supported */ 1168 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1169 char pool_name[14]; 1170 int i; 1171 1172 for (i = 0; i < MAX_SED_POOLS; i++) { 1173 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1174 1175 /* allocate SED DMA pool */ 1176 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1177 &pdev->dev, 1178 SED_SIZE * (i + 1), 64, 0); 1179 if (!ioat_dma->sed_hw_pool[i]) 1180 return -ENOMEM; 1181 1182 } 1183 } 1184 1185 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1186 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1187 1188 err = ioat_probe(ioat_dma); 1189 if (err) 1190 return err; 1191 1192 list_for_each_entry(c, &dma->channels, device_node) { 1193 ioat_chan = to_ioat_chan(c); 1194 writel(IOAT_DMA_DCA_ANY_CPU, 1195 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1196 } 1197 1198 err = ioat_register(ioat_dma); 1199 if (err) 1200 return err; 1201 1202 ioat_kobject_add(ioat_dma, &ioat_ktype); 1203 1204 if (dca) 1205 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1206 1207 /* disable relaxed ordering */ 1208 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); 1209 if (err) 1210 return err; 1211 1212 /* clear relaxed ordering enable */ 1213 val16 &= ~IOAT_DEVCTRL_ROE; 1214 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); 1215 if (err) 1216 return err; 1217 1218 if (ioat_dma->cap & IOAT_CAP_DPS) 1219 writeb(ioat_pending_level + 1, 1220 ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET); 1221 1222 return 0; 1223 } 1224 1225 static void ioat_shutdown(struct pci_dev *pdev) 1226 { 1227 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1228 struct ioatdma_chan *ioat_chan; 1229 int i; 1230 1231 if (!ioat_dma) 1232 return; 1233 1234 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1235 ioat_chan = ioat_dma->idx[i]; 1236 if (!ioat_chan) 1237 continue; 1238 1239 spin_lock_bh(&ioat_chan->prep_lock); 1240 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1241 spin_unlock_bh(&ioat_chan->prep_lock); 1242 /* 1243 * Synchronization rule for del_timer_sync(): 1244 * - The caller must not hold locks which would prevent 1245 * completion of the timer's handler. 1246 * So prep_lock cannot be held before calling it. 1247 */ 1248 del_timer_sync(&ioat_chan->timer); 1249 1250 /* this should quiesce then reset */ 1251 ioat_reset_hw(ioat_chan); 1252 } 1253 1254 ioat_disable_interrupts(ioat_dma); 1255 } 1256 1257 static void ioat_resume(struct ioatdma_device *ioat_dma) 1258 { 1259 struct ioatdma_chan *ioat_chan; 1260 u32 chanerr; 1261 int i; 1262 1263 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1264 ioat_chan = ioat_dma->idx[i]; 1265 if (!ioat_chan) 1266 continue; 1267 1268 spin_lock_bh(&ioat_chan->prep_lock); 1269 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1270 spin_unlock_bh(&ioat_chan->prep_lock); 1271 1272 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1273 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1274 1275 /* no need to reset as shutdown already did that */ 1276 } 1277 } 1278 1279 #define DRV_NAME "ioatdma" 1280 1281 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, 1282 enum pci_channel_state error) 1283 { 1284 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); 1285 1286 /* quiesce and block I/O */ 1287 ioat_shutdown(pdev); 1288 1289 return PCI_ERS_RESULT_NEED_RESET; 1290 } 1291 1292 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) 1293 { 1294 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1295 1296 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); 1297 1298 if (pci_enable_device_mem(pdev) < 0) { 1299 dev_err(&pdev->dev, 1300 "Failed to enable PCIe device after reset.\n"); 1301 result = PCI_ERS_RESULT_DISCONNECT; 1302 } else { 1303 pci_set_master(pdev); 1304 pci_restore_state(pdev); 1305 pci_save_state(pdev); 1306 pci_wake_from_d3(pdev, false); 1307 } 1308 1309 return result; 1310 } 1311 1312 static void ioat_pcie_error_resume(struct pci_dev *pdev) 1313 { 1314 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1315 1316 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); 1317 1318 /* initialize and bring everything back */ 1319 ioat_resume(ioat_dma); 1320 } 1321 1322 static const struct pci_error_handlers ioat_err_handler = { 1323 .error_detected = ioat_pcie_error_detected, 1324 .slot_reset = ioat_pcie_error_slot_reset, 1325 .resume = ioat_pcie_error_resume, 1326 }; 1327 1328 static struct pci_driver ioat_pci_driver = { 1329 .name = DRV_NAME, 1330 .id_table = ioat_pci_tbl, 1331 .probe = ioat_pci_probe, 1332 .remove = ioat_remove, 1333 .shutdown = ioat_shutdown, 1334 .err_handler = &ioat_err_handler, 1335 }; 1336 1337 static struct ioatdma_device * 1338 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1339 { 1340 struct device *dev = &pdev->dev; 1341 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1342 1343 if (!d) 1344 return NULL; 1345 d->pdev = pdev; 1346 d->reg_base = iobase; 1347 return d; 1348 } 1349 1350 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1351 { 1352 void __iomem * const *iomap; 1353 struct device *dev = &pdev->dev; 1354 struct ioatdma_device *device; 1355 int err; 1356 1357 err = pcim_enable_device(pdev); 1358 if (err) 1359 return err; 1360 1361 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1362 if (err) 1363 return err; 1364 iomap = pcim_iomap_table(pdev); 1365 if (!iomap) 1366 return -ENOMEM; 1367 1368 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1369 if (err) 1370 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1371 if (err) 1372 return err; 1373 1374 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1375 if (err) 1376 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1377 if (err) 1378 return err; 1379 1380 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1381 if (!device) 1382 return -ENOMEM; 1383 pci_set_master(pdev); 1384 pci_set_drvdata(pdev, device); 1385 1386 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1387 if (device->version >= IOAT_VER_3_4) 1388 ioat_dca_enabled = 0; 1389 if (device->version >= IOAT_VER_3_0) { 1390 if (is_skx_ioat(pdev)) 1391 device->version = IOAT_VER_3_2; 1392 err = ioat3_dma_probe(device, ioat_dca_enabled); 1393 1394 if (device->version >= IOAT_VER_3_3) 1395 pci_enable_pcie_error_reporting(pdev); 1396 } else 1397 return -ENODEV; 1398 1399 if (err) { 1400 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1401 pci_disable_pcie_error_reporting(pdev); 1402 return -ENODEV; 1403 } 1404 1405 return 0; 1406 } 1407 1408 static void ioat_remove(struct pci_dev *pdev) 1409 { 1410 struct ioatdma_device *device = pci_get_drvdata(pdev); 1411 1412 if (!device) 1413 return; 1414 1415 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1416 if (device->dca) { 1417 unregister_dca_provider(device->dca, &pdev->dev); 1418 free_dca_provider(device->dca); 1419 device->dca = NULL; 1420 } 1421 1422 pci_disable_pcie_error_reporting(pdev); 1423 ioat_dma_remove(device); 1424 } 1425 1426 static int __init ioat_init_module(void) 1427 { 1428 int err = -ENOMEM; 1429 1430 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1431 DRV_NAME, IOAT_DMA_VERSION); 1432 1433 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1434 0, SLAB_HWCACHE_ALIGN, NULL); 1435 if (!ioat_cache) 1436 return -ENOMEM; 1437 1438 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1439 if (!ioat_sed_cache) 1440 goto err_ioat_cache; 1441 1442 err = pci_register_driver(&ioat_pci_driver); 1443 if (err) 1444 goto err_ioat3_cache; 1445 1446 return 0; 1447 1448 err_ioat3_cache: 1449 kmem_cache_destroy(ioat_sed_cache); 1450 1451 err_ioat_cache: 1452 kmem_cache_destroy(ioat_cache); 1453 1454 return err; 1455 } 1456 module_init(ioat_init_module); 1457 1458 static void __exit ioat_exit_module(void) 1459 { 1460 pci_unregister_driver(&ioat_pci_driver); 1461 kmem_cache_destroy(ioat_cache); 1462 } 1463 module_exit(ioat_exit_module); 1464