1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include <linux/aer.h> 31 #include <linux/sizes.h> 32 #include "dma.h" 33 #include "registers.h" 34 #include "hw.h" 35 36 #include "../dmaengine.h" 37 38 MODULE_VERSION(IOAT_DMA_VERSION); 39 MODULE_LICENSE("Dual BSD/GPL"); 40 MODULE_AUTHOR("Intel Corporation"); 41 42 static struct pci_device_id ioat_pci_tbl[] = { 43 /* I/OAT v3 platforms */ 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 52 53 /* I/OAT v3.2 platforms */ 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 64 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 75 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 86 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 97 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 108 109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 110 111 /* I/OAT v3.3 platforms */ 112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 116 117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 121 122 { 0, } 123 }; 124 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 125 126 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 127 static void ioat_remove(struct pci_dev *pdev); 128 static void 129 ioat_init_channel(struct ioatdma_device *ioat_dma, 130 struct ioatdma_chan *ioat_chan, int idx); 131 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 132 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 133 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 134 135 static int ioat_dca_enabled = 1; 136 module_param(ioat_dca_enabled, int, 0644); 137 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 138 int ioat_pending_level = 4; 139 module_param(ioat_pending_level, int, 0644); 140 MODULE_PARM_DESC(ioat_pending_level, 141 "high-water mark for pushing ioat descriptors (default: 4)"); 142 static char ioat_interrupt_style[32] = "msix"; 143 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 144 sizeof(ioat_interrupt_style), 0644); 145 MODULE_PARM_DESC(ioat_interrupt_style, 146 "set ioat interrupt style: msix (default), msi, intx"); 147 148 struct kmem_cache *ioat_cache; 149 struct kmem_cache *ioat_sed_cache; 150 151 static bool is_jf_ioat(struct pci_dev *pdev) 152 { 153 switch (pdev->device) { 154 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 155 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 156 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 157 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 158 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 159 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 160 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 161 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 162 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 163 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static bool is_snb_ioat(struct pci_dev *pdev) 171 { 172 switch (pdev->device) { 173 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 174 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 175 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 176 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 177 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 178 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 179 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 180 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 181 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 182 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 static bool is_ivb_ioat(struct pci_dev *pdev) 190 { 191 switch (pdev->device) { 192 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 193 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 194 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 195 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 196 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 197 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 198 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 199 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 200 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 201 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 202 return true; 203 default: 204 return false; 205 } 206 207 } 208 209 static bool is_hsw_ioat(struct pci_dev *pdev) 210 { 211 switch (pdev->device) { 212 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 213 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 214 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 215 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 216 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 217 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 218 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 219 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 220 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 221 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 222 return true; 223 default: 224 return false; 225 } 226 227 } 228 229 static bool is_bdx_ioat(struct pci_dev *pdev) 230 { 231 switch (pdev->device) { 232 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 233 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 234 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 235 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 236 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 237 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 238 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 239 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 240 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 241 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 242 return true; 243 default: 244 return false; 245 } 246 } 247 248 static inline bool is_skx_ioat(struct pci_dev *pdev) 249 { 250 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 251 } 252 253 static bool is_xeon_cb32(struct pci_dev *pdev) 254 { 255 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 256 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 257 } 258 259 bool is_bwd_ioat(struct pci_dev *pdev) 260 { 261 switch (pdev->device) { 262 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 263 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 264 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 265 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 266 /* even though not Atom, BDX-DE has same DMA silicon */ 267 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 268 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 269 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 271 return true; 272 default: 273 return false; 274 } 275 } 276 277 static bool is_bwd_noraid(struct pci_dev *pdev) 278 { 279 switch (pdev->device) { 280 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 281 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 282 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 283 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 284 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 286 return true; 287 default: 288 return false; 289 } 290 291 } 292 293 /* 294 * Perform a IOAT transaction to verify the HW works. 295 */ 296 #define IOAT_TEST_SIZE 2000 297 298 static void ioat_dma_test_callback(void *dma_async_param) 299 { 300 struct completion *cmp = dma_async_param; 301 302 complete(cmp); 303 } 304 305 /** 306 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 307 * @ioat_dma: dma device to be tested 308 */ 309 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 310 { 311 int i; 312 u8 *src; 313 u8 *dest; 314 struct dma_device *dma = &ioat_dma->dma_dev; 315 struct device *dev = &ioat_dma->pdev->dev; 316 struct dma_chan *dma_chan; 317 struct dma_async_tx_descriptor *tx; 318 dma_addr_t dma_dest, dma_src; 319 dma_cookie_t cookie; 320 int err = 0; 321 struct completion cmp; 322 unsigned long tmo; 323 unsigned long flags; 324 325 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 326 if (!src) 327 return -ENOMEM; 328 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 329 if (!dest) { 330 kfree(src); 331 return -ENOMEM; 332 } 333 334 /* Fill in src buffer */ 335 for (i = 0; i < IOAT_TEST_SIZE; i++) 336 src[i] = (u8)i; 337 338 /* Start copy, using first DMA channel */ 339 dma_chan = container_of(dma->channels.next, struct dma_chan, 340 device_node); 341 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 342 dev_err(dev, "selftest cannot allocate chan resource\n"); 343 err = -ENODEV; 344 goto out; 345 } 346 347 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 348 if (dma_mapping_error(dev, dma_src)) { 349 dev_err(dev, "mapping src buffer failed\n"); 350 err = -ENOMEM; 351 goto free_resources; 352 } 353 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 354 if (dma_mapping_error(dev, dma_dest)) { 355 dev_err(dev, "mapping dest buffer failed\n"); 356 err = -ENOMEM; 357 goto unmap_src; 358 } 359 flags = DMA_PREP_INTERRUPT; 360 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 361 dma_src, IOAT_TEST_SIZE, 362 flags); 363 if (!tx) { 364 dev_err(dev, "Self-test prep failed, disabling\n"); 365 err = -ENODEV; 366 goto unmap_dma; 367 } 368 369 async_tx_ack(tx); 370 init_completion(&cmp); 371 tx->callback = ioat_dma_test_callback; 372 tx->callback_param = &cmp; 373 cookie = tx->tx_submit(tx); 374 if (cookie < 0) { 375 dev_err(dev, "Self-test setup failed, disabling\n"); 376 err = -ENODEV; 377 goto unmap_dma; 378 } 379 dma->device_issue_pending(dma_chan); 380 381 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 382 383 if (tmo == 0 || 384 dma->device_tx_status(dma_chan, cookie, NULL) 385 != DMA_COMPLETE) { 386 dev_err(dev, "Self-test copy timed out, disabling\n"); 387 err = -ENODEV; 388 goto unmap_dma; 389 } 390 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 391 dev_err(dev, "Self-test copy failed compare, disabling\n"); 392 err = -ENODEV; 393 goto free_resources; 394 } 395 396 unmap_dma: 397 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 398 unmap_src: 399 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 400 free_resources: 401 dma->device_free_chan_resources(dma_chan); 402 out: 403 kfree(src); 404 kfree(dest); 405 return err; 406 } 407 408 /** 409 * ioat_dma_setup_interrupts - setup interrupt handler 410 * @ioat_dma: ioat dma device 411 */ 412 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 413 { 414 struct ioatdma_chan *ioat_chan; 415 struct pci_dev *pdev = ioat_dma->pdev; 416 struct device *dev = &pdev->dev; 417 struct msix_entry *msix; 418 int i, j, msixcnt; 419 int err = -EINVAL; 420 u8 intrctrl = 0; 421 422 if (!strcmp(ioat_interrupt_style, "msix")) 423 goto msix; 424 if (!strcmp(ioat_interrupt_style, "msi")) 425 goto msi; 426 if (!strcmp(ioat_interrupt_style, "intx")) 427 goto intx; 428 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 429 goto err_no_irq; 430 431 msix: 432 /* The number of MSI-X vectors should equal the number of channels */ 433 msixcnt = ioat_dma->dma_dev.chancnt; 434 for (i = 0; i < msixcnt; i++) 435 ioat_dma->msix_entries[i].entry = i; 436 437 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 438 if (err) 439 goto msi; 440 441 for (i = 0; i < msixcnt; i++) { 442 msix = &ioat_dma->msix_entries[i]; 443 ioat_chan = ioat_chan_by_index(ioat_dma, i); 444 err = devm_request_irq(dev, msix->vector, 445 ioat_dma_do_interrupt_msix, 0, 446 "ioat-msix", ioat_chan); 447 if (err) { 448 for (j = 0; j < i; j++) { 449 msix = &ioat_dma->msix_entries[j]; 450 ioat_chan = ioat_chan_by_index(ioat_dma, j); 451 devm_free_irq(dev, msix->vector, ioat_chan); 452 } 453 goto msi; 454 } 455 } 456 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 457 ioat_dma->irq_mode = IOAT_MSIX; 458 goto done; 459 460 msi: 461 err = pci_enable_msi(pdev); 462 if (err) 463 goto intx; 464 465 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 466 "ioat-msi", ioat_dma); 467 if (err) { 468 pci_disable_msi(pdev); 469 goto intx; 470 } 471 ioat_dma->irq_mode = IOAT_MSI; 472 goto done; 473 474 intx: 475 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 476 IRQF_SHARED, "ioat-intx", ioat_dma); 477 if (err) 478 goto err_no_irq; 479 480 ioat_dma->irq_mode = IOAT_INTX; 481 done: 482 if (is_bwd_ioat(pdev)) 483 ioat_intr_quirk(ioat_dma); 484 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 485 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 486 return 0; 487 488 err_no_irq: 489 /* Disable all interrupt generation */ 490 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 491 ioat_dma->irq_mode = IOAT_NOIRQ; 492 dev_err(dev, "no usable interrupts\n"); 493 return err; 494 } 495 496 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 497 { 498 /* Disable all interrupt generation */ 499 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 500 } 501 502 static int ioat_probe(struct ioatdma_device *ioat_dma) 503 { 504 int err = -ENODEV; 505 struct dma_device *dma = &ioat_dma->dma_dev; 506 struct pci_dev *pdev = ioat_dma->pdev; 507 struct device *dev = &pdev->dev; 508 509 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, 510 sizeof(u64), 511 SMP_CACHE_BYTES, 512 SMP_CACHE_BYTES); 513 514 if (!ioat_dma->completion_pool) { 515 err = -ENOMEM; 516 goto err_out; 517 } 518 519 ioat_enumerate_channels(ioat_dma); 520 521 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 522 dma->dev = &pdev->dev; 523 524 if (!dma->chancnt) { 525 dev_err(dev, "channel enumeration error\n"); 526 goto err_setup_interrupts; 527 } 528 529 err = ioat_dma_setup_interrupts(ioat_dma); 530 if (err) 531 goto err_setup_interrupts; 532 533 err = ioat3_dma_self_test(ioat_dma); 534 if (err) 535 goto err_self_test; 536 537 return 0; 538 539 err_self_test: 540 ioat_disable_interrupts(ioat_dma); 541 err_setup_interrupts: 542 dma_pool_destroy(ioat_dma->completion_pool); 543 err_out: 544 return err; 545 } 546 547 static int ioat_register(struct ioatdma_device *ioat_dma) 548 { 549 int err = dma_async_device_register(&ioat_dma->dma_dev); 550 551 if (err) { 552 ioat_disable_interrupts(ioat_dma); 553 dma_pool_destroy(ioat_dma->completion_pool); 554 } 555 556 return err; 557 } 558 559 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 560 { 561 struct dma_device *dma = &ioat_dma->dma_dev; 562 563 ioat_disable_interrupts(ioat_dma); 564 565 ioat_kobject_del(ioat_dma); 566 567 dma_async_device_unregister(dma); 568 569 dma_pool_destroy(ioat_dma->completion_pool); 570 571 INIT_LIST_HEAD(&dma->channels); 572 } 573 574 /** 575 * ioat_enumerate_channels - find and initialize the device's channels 576 * @ioat_dma: the ioat dma device to be enumerated 577 */ 578 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 579 { 580 struct ioatdma_chan *ioat_chan; 581 struct device *dev = &ioat_dma->pdev->dev; 582 struct dma_device *dma = &ioat_dma->dma_dev; 583 u8 xfercap_log; 584 int i; 585 586 INIT_LIST_HEAD(&dma->channels); 587 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 588 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 589 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 590 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 591 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 592 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 593 } 594 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 595 xfercap_log &= 0x1f; /* bits [4:0] valid */ 596 if (xfercap_log == 0) 597 return 0; 598 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 599 600 for (i = 0; i < dma->chancnt; i++) { 601 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 602 if (!ioat_chan) 603 break; 604 605 ioat_init_channel(ioat_dma, ioat_chan, i); 606 ioat_chan->xfercap_log = xfercap_log; 607 spin_lock_init(&ioat_chan->prep_lock); 608 if (ioat_reset_hw(ioat_chan)) { 609 i = 0; 610 break; 611 } 612 } 613 dma->chancnt = i; 614 return i; 615 } 616 617 /** 618 * ioat_free_chan_resources - release all the descriptors 619 * @chan: the channel to be cleaned 620 */ 621 static void ioat_free_chan_resources(struct dma_chan *c) 622 { 623 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 624 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 625 struct ioat_ring_ent *desc; 626 const int total_descs = 1 << ioat_chan->alloc_order; 627 int descs; 628 int i; 629 630 /* Before freeing channel resources first check 631 * if they have been previously allocated for this channel. 632 */ 633 if (!ioat_chan->ring) 634 return; 635 636 ioat_stop(ioat_chan); 637 ioat_reset_hw(ioat_chan); 638 639 spin_lock_bh(&ioat_chan->cleanup_lock); 640 spin_lock_bh(&ioat_chan->prep_lock); 641 descs = ioat_ring_space(ioat_chan); 642 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 643 for (i = 0; i < descs; i++) { 644 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 645 ioat_free_ring_ent(desc, c); 646 } 647 648 if (descs < total_descs) 649 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 650 total_descs - descs); 651 652 for (i = 0; i < total_descs - descs; i++) { 653 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 654 dump_desc_dbg(ioat_chan, desc); 655 ioat_free_ring_ent(desc, c); 656 } 657 658 for (i = 0; i < ioat_chan->desc_chunks; i++) { 659 dma_free_coherent(to_dev(ioat_chan), SZ_2M, 660 ioat_chan->descs[i].virt, 661 ioat_chan->descs[i].hw); 662 ioat_chan->descs[i].virt = NULL; 663 ioat_chan->descs[i].hw = 0; 664 } 665 ioat_chan->desc_chunks = 0; 666 667 kfree(ioat_chan->ring); 668 ioat_chan->ring = NULL; 669 ioat_chan->alloc_order = 0; 670 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 671 ioat_chan->completion_dma); 672 spin_unlock_bh(&ioat_chan->prep_lock); 673 spin_unlock_bh(&ioat_chan->cleanup_lock); 674 675 ioat_chan->last_completion = 0; 676 ioat_chan->completion_dma = 0; 677 ioat_chan->dmacount = 0; 678 } 679 680 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 681 * @chan: channel to be initialized 682 */ 683 static int ioat_alloc_chan_resources(struct dma_chan *c) 684 { 685 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 686 struct ioat_ring_ent **ring; 687 u64 status; 688 int order; 689 int i = 0; 690 u32 chanerr; 691 692 /* have we already been set up? */ 693 if (ioat_chan->ring) 694 return 1 << ioat_chan->alloc_order; 695 696 /* Setup register to interrupt and write completion status on error */ 697 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 698 699 /* allocate a completion writeback area */ 700 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 701 ioat_chan->completion = 702 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 703 GFP_NOWAIT, &ioat_chan->completion_dma); 704 if (!ioat_chan->completion) 705 return -ENOMEM; 706 707 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 708 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 709 writel(((u64)ioat_chan->completion_dma) >> 32, 710 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 711 712 order = IOAT_MAX_ORDER; 713 ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 714 if (!ring) 715 return -ENOMEM; 716 717 spin_lock_bh(&ioat_chan->cleanup_lock); 718 spin_lock_bh(&ioat_chan->prep_lock); 719 ioat_chan->ring = ring; 720 ioat_chan->head = 0; 721 ioat_chan->issued = 0; 722 ioat_chan->tail = 0; 723 ioat_chan->alloc_order = order; 724 set_bit(IOAT_RUN, &ioat_chan->state); 725 spin_unlock_bh(&ioat_chan->prep_lock); 726 spin_unlock_bh(&ioat_chan->cleanup_lock); 727 728 ioat_start_null_desc(ioat_chan); 729 730 /* check that we got off the ground */ 731 do { 732 udelay(1); 733 status = ioat_chansts(ioat_chan); 734 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 735 736 if (is_ioat_active(status) || is_ioat_idle(status)) 737 return 1 << ioat_chan->alloc_order; 738 739 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 740 741 dev_WARN(to_dev(ioat_chan), 742 "failed to start channel chanerr: %#x\n", chanerr); 743 ioat_free_chan_resources(c); 744 return -EFAULT; 745 } 746 747 /* common channel initialization */ 748 static void 749 ioat_init_channel(struct ioatdma_device *ioat_dma, 750 struct ioatdma_chan *ioat_chan, int idx) 751 { 752 struct dma_device *dma = &ioat_dma->dma_dev; 753 struct dma_chan *c = &ioat_chan->dma_chan; 754 unsigned long data = (unsigned long) c; 755 756 ioat_chan->ioat_dma = ioat_dma; 757 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 758 spin_lock_init(&ioat_chan->cleanup_lock); 759 ioat_chan->dma_chan.device = dma; 760 dma_cookie_init(&ioat_chan->dma_chan); 761 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 762 ioat_dma->idx[idx] = ioat_chan; 763 init_timer(&ioat_chan->timer); 764 ioat_chan->timer.function = ioat_timer_event; 765 ioat_chan->timer.data = data; 766 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); 767 } 768 769 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 770 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 771 { 772 int i, src_idx; 773 struct page *dest; 774 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 775 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 776 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 777 dma_addr_t dest_dma; 778 struct dma_async_tx_descriptor *tx; 779 struct dma_chan *dma_chan; 780 dma_cookie_t cookie; 781 u8 cmp_byte = 0; 782 u32 cmp_word; 783 u32 xor_val_result; 784 int err = 0; 785 struct completion cmp; 786 unsigned long tmo; 787 struct device *dev = &ioat_dma->pdev->dev; 788 struct dma_device *dma = &ioat_dma->dma_dev; 789 u8 op = 0; 790 791 dev_dbg(dev, "%s\n", __func__); 792 793 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 794 return 0; 795 796 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 797 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 798 if (!xor_srcs[src_idx]) { 799 while (src_idx--) 800 __free_page(xor_srcs[src_idx]); 801 return -ENOMEM; 802 } 803 } 804 805 dest = alloc_page(GFP_KERNEL); 806 if (!dest) { 807 while (src_idx--) 808 __free_page(xor_srcs[src_idx]); 809 return -ENOMEM; 810 } 811 812 /* Fill in src buffers */ 813 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 814 u8 *ptr = page_address(xor_srcs[src_idx]); 815 816 for (i = 0; i < PAGE_SIZE; i++) 817 ptr[i] = (1 << src_idx); 818 } 819 820 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 821 cmp_byte ^= (u8) (1 << src_idx); 822 823 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 824 (cmp_byte << 8) | cmp_byte; 825 826 memset(page_address(dest), 0, PAGE_SIZE); 827 828 dma_chan = container_of(dma->channels.next, struct dma_chan, 829 device_node); 830 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 831 err = -ENODEV; 832 goto out; 833 } 834 835 /* test xor */ 836 op = IOAT_OP_XOR; 837 838 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 839 if (dma_mapping_error(dev, dest_dma)) { 840 err = -ENOMEM; 841 goto free_resources; 842 } 843 844 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 845 dma_srcs[i] = DMA_ERROR_CODE; 846 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 847 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 848 DMA_TO_DEVICE); 849 if (dma_mapping_error(dev, dma_srcs[i])) { 850 err = -ENOMEM; 851 goto dma_unmap; 852 } 853 } 854 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 855 IOAT_NUM_SRC_TEST, PAGE_SIZE, 856 DMA_PREP_INTERRUPT); 857 858 if (!tx) { 859 dev_err(dev, "Self-test xor prep failed\n"); 860 err = -ENODEV; 861 goto dma_unmap; 862 } 863 864 async_tx_ack(tx); 865 init_completion(&cmp); 866 tx->callback = ioat_dma_test_callback; 867 tx->callback_param = &cmp; 868 cookie = tx->tx_submit(tx); 869 if (cookie < 0) { 870 dev_err(dev, "Self-test xor setup failed\n"); 871 err = -ENODEV; 872 goto dma_unmap; 873 } 874 dma->device_issue_pending(dma_chan); 875 876 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 877 878 if (tmo == 0 || 879 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 880 dev_err(dev, "Self-test xor timed out\n"); 881 err = -ENODEV; 882 goto dma_unmap; 883 } 884 885 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 886 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 887 888 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 889 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 890 u32 *ptr = page_address(dest); 891 892 if (ptr[i] != cmp_word) { 893 dev_err(dev, "Self-test xor failed compare\n"); 894 err = -ENODEV; 895 goto free_resources; 896 } 897 } 898 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 899 900 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 901 902 /* skip validate if the capability is not present */ 903 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 904 goto free_resources; 905 906 op = IOAT_OP_XOR_VAL; 907 908 /* validate the sources with the destintation page */ 909 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 910 xor_val_srcs[i] = xor_srcs[i]; 911 xor_val_srcs[i] = dest; 912 913 xor_val_result = 1; 914 915 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 916 dma_srcs[i] = DMA_ERROR_CODE; 917 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 918 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 919 DMA_TO_DEVICE); 920 if (dma_mapping_error(dev, dma_srcs[i])) { 921 err = -ENOMEM; 922 goto dma_unmap; 923 } 924 } 925 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 926 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 927 &xor_val_result, DMA_PREP_INTERRUPT); 928 if (!tx) { 929 dev_err(dev, "Self-test zero prep failed\n"); 930 err = -ENODEV; 931 goto dma_unmap; 932 } 933 934 async_tx_ack(tx); 935 init_completion(&cmp); 936 tx->callback = ioat_dma_test_callback; 937 tx->callback_param = &cmp; 938 cookie = tx->tx_submit(tx); 939 if (cookie < 0) { 940 dev_err(dev, "Self-test zero setup failed\n"); 941 err = -ENODEV; 942 goto dma_unmap; 943 } 944 dma->device_issue_pending(dma_chan); 945 946 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 947 948 if (tmo == 0 || 949 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 950 dev_err(dev, "Self-test validate timed out\n"); 951 err = -ENODEV; 952 goto dma_unmap; 953 } 954 955 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 956 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 957 958 if (xor_val_result != 0) { 959 dev_err(dev, "Self-test validate failed compare\n"); 960 err = -ENODEV; 961 goto free_resources; 962 } 963 964 memset(page_address(dest), 0, PAGE_SIZE); 965 966 /* test for non-zero parity sum */ 967 op = IOAT_OP_XOR_VAL; 968 969 xor_val_result = 0; 970 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 971 dma_srcs[i] = DMA_ERROR_CODE; 972 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 973 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 974 DMA_TO_DEVICE); 975 if (dma_mapping_error(dev, dma_srcs[i])) { 976 err = -ENOMEM; 977 goto dma_unmap; 978 } 979 } 980 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 981 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 982 &xor_val_result, DMA_PREP_INTERRUPT); 983 if (!tx) { 984 dev_err(dev, "Self-test 2nd zero prep failed\n"); 985 err = -ENODEV; 986 goto dma_unmap; 987 } 988 989 async_tx_ack(tx); 990 init_completion(&cmp); 991 tx->callback = ioat_dma_test_callback; 992 tx->callback_param = &cmp; 993 cookie = tx->tx_submit(tx); 994 if (cookie < 0) { 995 dev_err(dev, "Self-test 2nd zero setup failed\n"); 996 err = -ENODEV; 997 goto dma_unmap; 998 } 999 dma->device_issue_pending(dma_chan); 1000 1001 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 1002 1003 if (tmo == 0 || 1004 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 1005 dev_err(dev, "Self-test 2nd validate timed out\n"); 1006 err = -ENODEV; 1007 goto dma_unmap; 1008 } 1009 1010 if (xor_val_result != SUM_CHECK_P_RESULT) { 1011 dev_err(dev, "Self-test validate failed compare\n"); 1012 err = -ENODEV; 1013 goto dma_unmap; 1014 } 1015 1016 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1017 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1018 1019 goto free_resources; 1020 dma_unmap: 1021 if (op == IOAT_OP_XOR) { 1022 if (dest_dma != DMA_ERROR_CODE) 1023 dma_unmap_page(dev, dest_dma, PAGE_SIZE, 1024 DMA_FROM_DEVICE); 1025 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 1026 if (dma_srcs[i] != DMA_ERROR_CODE) 1027 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1028 DMA_TO_DEVICE); 1029 } else if (op == IOAT_OP_XOR_VAL) { 1030 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1031 if (dma_srcs[i] != DMA_ERROR_CODE) 1032 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1033 DMA_TO_DEVICE); 1034 } 1035 free_resources: 1036 dma->device_free_chan_resources(dma_chan); 1037 out: 1038 src_idx = IOAT_NUM_SRC_TEST; 1039 while (src_idx--) 1040 __free_page(xor_srcs[src_idx]); 1041 __free_page(dest); 1042 return err; 1043 } 1044 1045 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1046 { 1047 int rc; 1048 1049 rc = ioat_dma_self_test(ioat_dma); 1050 if (rc) 1051 return rc; 1052 1053 rc = ioat_xor_val_self_test(ioat_dma); 1054 1055 return rc; 1056 } 1057 1058 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1059 { 1060 struct dma_device *dma; 1061 struct dma_chan *c; 1062 struct ioatdma_chan *ioat_chan; 1063 u32 errmask; 1064 1065 dma = &ioat_dma->dma_dev; 1066 1067 /* 1068 * if we have descriptor write back error status, we mask the 1069 * error interrupts 1070 */ 1071 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1072 list_for_each_entry(c, &dma->channels, device_node) { 1073 ioat_chan = to_ioat_chan(c); 1074 errmask = readl(ioat_chan->reg_base + 1075 IOAT_CHANERR_MASK_OFFSET); 1076 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1077 IOAT_CHANERR_XOR_Q_ERR; 1078 writel(errmask, ioat_chan->reg_base + 1079 IOAT_CHANERR_MASK_OFFSET); 1080 } 1081 } 1082 } 1083 1084 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1085 { 1086 struct pci_dev *pdev = ioat_dma->pdev; 1087 int dca_en = system_has_dca_enabled(pdev); 1088 struct dma_device *dma; 1089 struct dma_chan *c; 1090 struct ioatdma_chan *ioat_chan; 1091 int err; 1092 u16 val16; 1093 1094 dma = &ioat_dma->dma_dev; 1095 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1096 dma->device_issue_pending = ioat_issue_pending; 1097 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1098 dma->device_free_chan_resources = ioat_free_chan_resources; 1099 1100 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1101 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1102 1103 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1104 1105 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1106 ioat_dma->cap &= 1107 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1108 1109 /* dca is incompatible with raid operations */ 1110 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1111 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1112 1113 if (ioat_dma->cap & IOAT_CAP_XOR) { 1114 dma->max_xor = 8; 1115 1116 dma_cap_set(DMA_XOR, dma->cap_mask); 1117 dma->device_prep_dma_xor = ioat_prep_xor; 1118 1119 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1120 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1121 } 1122 1123 if (ioat_dma->cap & IOAT_CAP_PQ) { 1124 1125 dma->device_prep_dma_pq = ioat_prep_pq; 1126 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1127 dma_cap_set(DMA_PQ, dma->cap_mask); 1128 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1129 1130 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1131 dma_set_maxpq(dma, 16, 0); 1132 else 1133 dma_set_maxpq(dma, 8, 0); 1134 1135 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1136 dma->device_prep_dma_xor = ioat_prep_pqxor; 1137 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1138 dma_cap_set(DMA_XOR, dma->cap_mask); 1139 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1140 1141 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1142 dma->max_xor = 16; 1143 else 1144 dma->max_xor = 8; 1145 } 1146 } 1147 1148 dma->device_tx_status = ioat_tx_status; 1149 1150 /* starting with CB3.3 super extended descriptors are supported */ 1151 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1152 char pool_name[14]; 1153 int i; 1154 1155 for (i = 0; i < MAX_SED_POOLS; i++) { 1156 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1157 1158 /* allocate SED DMA pool */ 1159 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1160 &pdev->dev, 1161 SED_SIZE * (i + 1), 64, 0); 1162 if (!ioat_dma->sed_hw_pool[i]) 1163 return -ENOMEM; 1164 1165 } 1166 } 1167 1168 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1169 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1170 1171 err = ioat_probe(ioat_dma); 1172 if (err) 1173 return err; 1174 1175 list_for_each_entry(c, &dma->channels, device_node) { 1176 ioat_chan = to_ioat_chan(c); 1177 writel(IOAT_DMA_DCA_ANY_CPU, 1178 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1179 } 1180 1181 err = ioat_register(ioat_dma); 1182 if (err) 1183 return err; 1184 1185 ioat_kobject_add(ioat_dma, &ioat_ktype); 1186 1187 if (dca) 1188 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1189 1190 /* disable relaxed ordering */ 1191 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); 1192 if (err) 1193 return err; 1194 1195 /* clear relaxed ordering enable */ 1196 val16 &= ~IOAT_DEVCTRL_ROE; 1197 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); 1198 if (err) 1199 return err; 1200 1201 return 0; 1202 } 1203 1204 static void ioat_shutdown(struct pci_dev *pdev) 1205 { 1206 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1207 struct ioatdma_chan *ioat_chan; 1208 int i; 1209 1210 if (!ioat_dma) 1211 return; 1212 1213 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1214 ioat_chan = ioat_dma->idx[i]; 1215 if (!ioat_chan) 1216 continue; 1217 1218 spin_lock_bh(&ioat_chan->prep_lock); 1219 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1220 del_timer_sync(&ioat_chan->timer); 1221 spin_unlock_bh(&ioat_chan->prep_lock); 1222 /* this should quiesce then reset */ 1223 ioat_reset_hw(ioat_chan); 1224 } 1225 1226 ioat_disable_interrupts(ioat_dma); 1227 } 1228 1229 static void ioat_resume(struct ioatdma_device *ioat_dma) 1230 { 1231 struct ioatdma_chan *ioat_chan; 1232 u32 chanerr; 1233 int i; 1234 1235 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1236 ioat_chan = ioat_dma->idx[i]; 1237 if (!ioat_chan) 1238 continue; 1239 1240 spin_lock_bh(&ioat_chan->prep_lock); 1241 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1242 spin_unlock_bh(&ioat_chan->prep_lock); 1243 1244 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1245 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1246 1247 /* no need to reset as shutdown already did that */ 1248 } 1249 } 1250 1251 #define DRV_NAME "ioatdma" 1252 1253 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, 1254 enum pci_channel_state error) 1255 { 1256 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); 1257 1258 /* quiesce and block I/O */ 1259 ioat_shutdown(pdev); 1260 1261 return PCI_ERS_RESULT_NEED_RESET; 1262 } 1263 1264 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) 1265 { 1266 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1267 int err; 1268 1269 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); 1270 1271 if (pci_enable_device_mem(pdev) < 0) { 1272 dev_err(&pdev->dev, 1273 "Failed to enable PCIe device after reset.\n"); 1274 result = PCI_ERS_RESULT_DISCONNECT; 1275 } else { 1276 pci_set_master(pdev); 1277 pci_restore_state(pdev); 1278 pci_save_state(pdev); 1279 pci_wake_from_d3(pdev, false); 1280 } 1281 1282 err = pci_cleanup_aer_uncorrect_error_status(pdev); 1283 if (err) { 1284 dev_err(&pdev->dev, 1285 "AER uncorrect error status clear failed: %#x\n", err); 1286 } 1287 1288 return result; 1289 } 1290 1291 static void ioat_pcie_error_resume(struct pci_dev *pdev) 1292 { 1293 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1294 1295 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); 1296 1297 /* initialize and bring everything back */ 1298 ioat_resume(ioat_dma); 1299 } 1300 1301 static const struct pci_error_handlers ioat_err_handler = { 1302 .error_detected = ioat_pcie_error_detected, 1303 .slot_reset = ioat_pcie_error_slot_reset, 1304 .resume = ioat_pcie_error_resume, 1305 }; 1306 1307 static struct pci_driver ioat_pci_driver = { 1308 .name = DRV_NAME, 1309 .id_table = ioat_pci_tbl, 1310 .probe = ioat_pci_probe, 1311 .remove = ioat_remove, 1312 .shutdown = ioat_shutdown, 1313 .err_handler = &ioat_err_handler, 1314 }; 1315 1316 static struct ioatdma_device * 1317 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1318 { 1319 struct device *dev = &pdev->dev; 1320 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1321 1322 if (!d) 1323 return NULL; 1324 d->pdev = pdev; 1325 d->reg_base = iobase; 1326 return d; 1327 } 1328 1329 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1330 { 1331 void __iomem * const *iomap; 1332 struct device *dev = &pdev->dev; 1333 struct ioatdma_device *device; 1334 int err; 1335 1336 err = pcim_enable_device(pdev); 1337 if (err) 1338 return err; 1339 1340 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1341 if (err) 1342 return err; 1343 iomap = pcim_iomap_table(pdev); 1344 if (!iomap) 1345 return -ENOMEM; 1346 1347 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1348 if (err) 1349 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1350 if (err) 1351 return err; 1352 1353 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1354 if (err) 1355 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1356 if (err) 1357 return err; 1358 1359 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1360 if (!device) 1361 return -ENOMEM; 1362 pci_set_master(pdev); 1363 pci_set_drvdata(pdev, device); 1364 1365 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1366 if (device->version >= IOAT_VER_3_0) { 1367 if (is_skx_ioat(pdev)) 1368 device->version = IOAT_VER_3_2; 1369 err = ioat3_dma_probe(device, ioat_dca_enabled); 1370 1371 if (device->version >= IOAT_VER_3_3) 1372 pci_enable_pcie_error_reporting(pdev); 1373 } else 1374 return -ENODEV; 1375 1376 if (err) { 1377 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1378 pci_disable_pcie_error_reporting(pdev); 1379 return -ENODEV; 1380 } 1381 1382 return 0; 1383 } 1384 1385 static void ioat_remove(struct pci_dev *pdev) 1386 { 1387 struct ioatdma_device *device = pci_get_drvdata(pdev); 1388 1389 if (!device) 1390 return; 1391 1392 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1393 if (device->dca) { 1394 unregister_dca_provider(device->dca, &pdev->dev); 1395 free_dca_provider(device->dca); 1396 device->dca = NULL; 1397 } 1398 1399 pci_disable_pcie_error_reporting(pdev); 1400 ioat_dma_remove(device); 1401 } 1402 1403 static int __init ioat_init_module(void) 1404 { 1405 int err = -ENOMEM; 1406 1407 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1408 DRV_NAME, IOAT_DMA_VERSION); 1409 1410 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1411 0, SLAB_HWCACHE_ALIGN, NULL); 1412 if (!ioat_cache) 1413 return -ENOMEM; 1414 1415 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1416 if (!ioat_sed_cache) 1417 goto err_ioat_cache; 1418 1419 err = pci_register_driver(&ioat_pci_driver); 1420 if (err) 1421 goto err_ioat3_cache; 1422 1423 return 0; 1424 1425 err_ioat3_cache: 1426 kmem_cache_destroy(ioat_sed_cache); 1427 1428 err_ioat_cache: 1429 kmem_cache_destroy(ioat_cache); 1430 1431 return err; 1432 } 1433 module_init(ioat_init_module); 1434 1435 static void __exit ioat_exit_module(void) 1436 { 1437 pci_unregister_driver(&ioat_pci_driver); 1438 kmem_cache_destroy(ioat_cache); 1439 } 1440 module_exit(ioat_exit_module); 1441