1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef _IOAT_HW_H_ 18 #define _IOAT_HW_H_ 19 20 /* PCI Configuration Space Values */ 21 #define IOAT_MMIO_BAR 0 22 23 /* CB device ID's */ 24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20 25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21 26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22 27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23 28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24 29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25 30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26 31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27 32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e 33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f 34 35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20 36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21 37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22 38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23 39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24 40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25 41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26 42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27 43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e 44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f 45 46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50 47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51 48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52 49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53 50 51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50 52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51 53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52 54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53 55 56 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20 57 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21 58 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22 59 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23 60 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24 61 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25 62 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26 63 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27 64 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e 65 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f 66 67 #define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021 68 69 #define PCI_DEVICE_ID_INTEL_IOAT_ICX 0x0b00 70 71 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 72 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 73 #define IOAT_VER_3_0 0x30 /* Version 3.0 */ 74 #define IOAT_VER_3_2 0x32 /* Version 3.2 */ 75 #define IOAT_VER_3_3 0x33 /* Version 3.3 */ 76 #define IOAT_VER_3_4 0x34 /* Version 3.4 */ 77 78 79 int system_has_dca_enabled(struct pci_dev *pdev); 80 81 #define IOAT_DESC_SZ 64 82 83 struct ioat_dma_descriptor { 84 uint32_t size; 85 union { 86 uint32_t ctl; 87 struct { 88 unsigned int int_en:1; 89 unsigned int src_snoop_dis:1; 90 unsigned int dest_snoop_dis:1; 91 unsigned int compl_write:1; 92 unsigned int fence:1; 93 unsigned int null:1; 94 unsigned int src_brk:1; 95 unsigned int dest_brk:1; 96 unsigned int bundle:1; 97 unsigned int dest_dca:1; 98 unsigned int hint:1; 99 unsigned int rsvd2:13; 100 #define IOAT_OP_COPY 0x00 101 unsigned int op:8; 102 } ctl_f; 103 }; 104 uint64_t src_addr; 105 uint64_t dst_addr; 106 uint64_t next; 107 uint64_t rsv1; 108 uint64_t rsv2; 109 /* store some driver data in an unused portion of the descriptor */ 110 union { 111 uint64_t user1; 112 uint64_t tx_cnt; 113 }; 114 uint64_t user2; 115 }; 116 117 struct ioat_xor_descriptor { 118 uint32_t size; 119 union { 120 uint32_t ctl; 121 struct { 122 unsigned int int_en:1; 123 unsigned int src_snoop_dis:1; 124 unsigned int dest_snoop_dis:1; 125 unsigned int compl_write:1; 126 unsigned int fence:1; 127 unsigned int src_cnt:3; 128 unsigned int bundle:1; 129 unsigned int dest_dca:1; 130 unsigned int hint:1; 131 unsigned int rsvd:13; 132 #define IOAT_OP_XOR 0x87 133 #define IOAT_OP_XOR_VAL 0x88 134 unsigned int op:8; 135 } ctl_f; 136 }; 137 uint64_t src_addr; 138 uint64_t dst_addr; 139 uint64_t next; 140 uint64_t src_addr2; 141 uint64_t src_addr3; 142 uint64_t src_addr4; 143 uint64_t src_addr5; 144 }; 145 146 struct ioat_xor_ext_descriptor { 147 uint64_t src_addr6; 148 uint64_t src_addr7; 149 uint64_t src_addr8; 150 uint64_t next; 151 uint64_t rsvd[4]; 152 }; 153 154 struct ioat_pq_descriptor { 155 union { 156 uint32_t size; 157 uint32_t dwbes; 158 struct { 159 unsigned int rsvd:25; 160 unsigned int p_val_err:1; 161 unsigned int q_val_err:1; 162 unsigned int rsvd1:4; 163 unsigned int wbes:1; 164 } dwbes_f; 165 }; 166 union { 167 uint32_t ctl; 168 struct { 169 unsigned int int_en:1; 170 unsigned int src_snoop_dis:1; 171 unsigned int dest_snoop_dis:1; 172 unsigned int compl_write:1; 173 unsigned int fence:1; 174 unsigned int src_cnt:3; 175 unsigned int bundle:1; 176 unsigned int dest_dca:1; 177 unsigned int hint:1; 178 unsigned int p_disable:1; 179 unsigned int q_disable:1; 180 unsigned int rsvd2:2; 181 unsigned int wb_en:1; 182 unsigned int prl_en:1; 183 unsigned int rsvd3:7; 184 #define IOAT_OP_PQ 0x89 185 #define IOAT_OP_PQ_VAL 0x8a 186 #define IOAT_OP_PQ_16S 0xa0 187 #define IOAT_OP_PQ_VAL_16S 0xa1 188 unsigned int op:8; 189 } ctl_f; 190 }; 191 uint64_t src_addr; 192 uint64_t p_addr; 193 uint64_t next; 194 uint64_t src_addr2; 195 union { 196 uint64_t src_addr3; 197 uint64_t sed_addr; 198 }; 199 uint8_t coef[8]; 200 uint64_t q_addr; 201 }; 202 203 struct ioat_pq_ext_descriptor { 204 uint64_t src_addr4; 205 uint64_t src_addr5; 206 uint64_t src_addr6; 207 uint64_t next; 208 uint64_t src_addr7; 209 uint64_t src_addr8; 210 uint64_t rsvd[2]; 211 }; 212 213 struct ioat_pq_update_descriptor { 214 uint32_t size; 215 union { 216 uint32_t ctl; 217 struct { 218 unsigned int int_en:1; 219 unsigned int src_snoop_dis:1; 220 unsigned int dest_snoop_dis:1; 221 unsigned int compl_write:1; 222 unsigned int fence:1; 223 unsigned int src_cnt:3; 224 unsigned int bundle:1; 225 unsigned int dest_dca:1; 226 unsigned int hint:1; 227 unsigned int p_disable:1; 228 unsigned int q_disable:1; 229 unsigned int rsvd:3; 230 unsigned int coef:8; 231 #define IOAT_OP_PQ_UP 0x8b 232 unsigned int op:8; 233 } ctl_f; 234 }; 235 uint64_t src_addr; 236 uint64_t p_addr; 237 uint64_t next; 238 uint64_t src_addr2; 239 uint64_t p_src; 240 uint64_t q_src; 241 uint64_t q_addr; 242 }; 243 244 struct ioat_raw_descriptor { 245 uint64_t field[8]; 246 }; 247 248 struct ioat_pq16a_descriptor { 249 uint8_t coef[8]; 250 uint64_t src_addr3; 251 uint64_t src_addr4; 252 uint64_t src_addr5; 253 uint64_t src_addr6; 254 uint64_t src_addr7; 255 uint64_t src_addr8; 256 uint64_t src_addr9; 257 }; 258 259 struct ioat_pq16b_descriptor { 260 uint64_t src_addr10; 261 uint64_t src_addr11; 262 uint64_t src_addr12; 263 uint64_t src_addr13; 264 uint64_t src_addr14; 265 uint64_t src_addr15; 266 uint64_t src_addr16; 267 uint64_t rsvd; 268 }; 269 270 union ioat_sed_pq_descriptor { 271 struct ioat_pq16a_descriptor a; 272 struct ioat_pq16b_descriptor b; 273 }; 274 275 #define SED_SIZE 64 276 277 struct ioat_sed_raw_descriptor { 278 uint64_t a[8]; 279 uint64_t b[8]; 280 uint64_t c[8]; 281 }; 282 283 #endif 284