1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef _IOAT_HW_H_ 22 #define _IOAT_HW_H_ 23 24 /* PCI Configuration Space Values */ 25 #define IOAT_PCI_VID 0x8086 26 #define IOAT_MMIO_BAR 0 27 28 /* CB device ID's */ 29 #define IOAT_PCI_DID_5000 0x1A38 30 #define IOAT_PCI_DID_CNB 0x360B 31 #define IOAT_PCI_DID_SCNB 0x65FF 32 #define IOAT_PCI_DID_SNB 0x402F 33 34 #define IOAT_PCI_RID 0x00 35 #define IOAT_PCI_SVID 0x8086 36 #define IOAT_PCI_SID 0x8086 37 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 38 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 39 #define IOAT_VER_3_0 0x30 /* Version 3.0 */ 40 #define IOAT_VER_3_2 0x32 /* Version 3.2 */ 41 42 struct ioat_dma_descriptor { 43 uint32_t size; 44 union { 45 uint32_t ctl; 46 struct { 47 unsigned int int_en:1; 48 unsigned int src_snoop_dis:1; 49 unsigned int dest_snoop_dis:1; 50 unsigned int compl_write:1; 51 unsigned int fence:1; 52 unsigned int null:1; 53 unsigned int src_brk:1; 54 unsigned int dest_brk:1; 55 unsigned int bundle:1; 56 unsigned int dest_dca:1; 57 unsigned int hint:1; 58 unsigned int rsvd2:13; 59 #define IOAT_OP_COPY 0x00 60 unsigned int op:8; 61 } ctl_f; 62 }; 63 uint64_t src_addr; 64 uint64_t dst_addr; 65 uint64_t next; 66 uint64_t rsv1; 67 uint64_t rsv2; 68 /* store some driver data in an unused portion of the descriptor */ 69 union { 70 uint64_t user1; 71 uint64_t tx_cnt; 72 }; 73 uint64_t user2; 74 }; 75 76 struct ioat_fill_descriptor { 77 uint32_t size; 78 union { 79 uint32_t ctl; 80 struct { 81 unsigned int int_en:1; 82 unsigned int rsvd:1; 83 unsigned int dest_snoop_dis:1; 84 unsigned int compl_write:1; 85 unsigned int fence:1; 86 unsigned int rsvd2:2; 87 unsigned int dest_brk:1; 88 unsigned int bundle:1; 89 unsigned int rsvd4:15; 90 #define IOAT_OP_FILL 0x01 91 unsigned int op:8; 92 } ctl_f; 93 }; 94 uint64_t src_data; 95 uint64_t dst_addr; 96 uint64_t next; 97 uint64_t rsv1; 98 uint64_t next_dst_addr; 99 uint64_t user1; 100 uint64_t user2; 101 }; 102 103 struct ioat_xor_descriptor { 104 uint32_t size; 105 union { 106 uint32_t ctl; 107 struct { 108 unsigned int int_en:1; 109 unsigned int src_snoop_dis:1; 110 unsigned int dest_snoop_dis:1; 111 unsigned int compl_write:1; 112 unsigned int fence:1; 113 unsigned int src_cnt:3; 114 unsigned int bundle:1; 115 unsigned int dest_dca:1; 116 unsigned int hint:1; 117 unsigned int rsvd:13; 118 #define IOAT_OP_XOR 0x87 119 #define IOAT_OP_XOR_VAL 0x88 120 unsigned int op:8; 121 } ctl_f; 122 }; 123 uint64_t src_addr; 124 uint64_t dst_addr; 125 uint64_t next; 126 uint64_t src_addr2; 127 uint64_t src_addr3; 128 uint64_t src_addr4; 129 uint64_t src_addr5; 130 }; 131 132 struct ioat_xor_ext_descriptor { 133 uint64_t src_addr6; 134 uint64_t src_addr7; 135 uint64_t src_addr8; 136 uint64_t next; 137 uint64_t rsvd[4]; 138 }; 139 140 struct ioat_pq_descriptor { 141 uint32_t size; 142 union { 143 uint32_t ctl; 144 struct { 145 unsigned int int_en:1; 146 unsigned int src_snoop_dis:1; 147 unsigned int dest_snoop_dis:1; 148 unsigned int compl_write:1; 149 unsigned int fence:1; 150 unsigned int src_cnt:3; 151 unsigned int bundle:1; 152 unsigned int dest_dca:1; 153 unsigned int hint:1; 154 unsigned int p_disable:1; 155 unsigned int q_disable:1; 156 unsigned int rsvd:11; 157 #define IOAT_OP_PQ 0x89 158 #define IOAT_OP_PQ_VAL 0x8a 159 unsigned int op:8; 160 } ctl_f; 161 }; 162 uint64_t src_addr; 163 uint64_t p_addr; 164 uint64_t next; 165 uint64_t src_addr2; 166 uint64_t src_addr3; 167 uint8_t coef[8]; 168 uint64_t q_addr; 169 }; 170 171 struct ioat_pq_ext_descriptor { 172 uint64_t src_addr4; 173 uint64_t src_addr5; 174 uint64_t src_addr6; 175 uint64_t next; 176 uint64_t src_addr7; 177 uint64_t src_addr8; 178 uint64_t rsvd[2]; 179 }; 180 181 struct ioat_pq_update_descriptor { 182 uint32_t size; 183 union { 184 uint32_t ctl; 185 struct { 186 unsigned int int_en:1; 187 unsigned int src_snoop_dis:1; 188 unsigned int dest_snoop_dis:1; 189 unsigned int compl_write:1; 190 unsigned int fence:1; 191 unsigned int src_cnt:3; 192 unsigned int bundle:1; 193 unsigned int dest_dca:1; 194 unsigned int hint:1; 195 unsigned int p_disable:1; 196 unsigned int q_disable:1; 197 unsigned int rsvd:3; 198 unsigned int coef:8; 199 #define IOAT_OP_PQ_UP 0x8b 200 unsigned int op:8; 201 } ctl_f; 202 }; 203 uint64_t src_addr; 204 uint64_t p_addr; 205 uint64_t next; 206 uint64_t src_addr2; 207 uint64_t p_src; 208 uint64_t q_src; 209 uint64_t q_addr; 210 }; 211 212 struct ioat_raw_descriptor { 213 uint64_t field[8]; 214 }; 215 #endif 216