1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef _IOAT_HW_H_ 22 #define _IOAT_HW_H_ 23 24 /* PCI Configuration Space Values */ 25 #define IOAT_MMIO_BAR 0 26 27 /* CB device ID's */ 28 #define IOAT_PCI_DID_5000 0x1A38 29 #define IOAT_PCI_DID_CNB 0x360B 30 #define IOAT_PCI_DID_SCNB 0x65FF 31 #define IOAT_PCI_DID_SNB 0x402F 32 33 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 34 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 35 #define IOAT_VER_3_0 0x30 /* Version 3.0 */ 36 #define IOAT_VER_3_2 0x32 /* Version 3.2 */ 37 38 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20 39 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21 40 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22 41 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23 42 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24 43 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25 44 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26 45 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27 46 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e 47 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f 48 49 int system_has_dca_enabled(struct pci_dev *pdev); 50 51 struct ioat_dma_descriptor { 52 uint32_t size; 53 union { 54 uint32_t ctl; 55 struct { 56 unsigned int int_en:1; 57 unsigned int src_snoop_dis:1; 58 unsigned int dest_snoop_dis:1; 59 unsigned int compl_write:1; 60 unsigned int fence:1; 61 unsigned int null:1; 62 unsigned int src_brk:1; 63 unsigned int dest_brk:1; 64 unsigned int bundle:1; 65 unsigned int dest_dca:1; 66 unsigned int hint:1; 67 unsigned int rsvd2:13; 68 #define IOAT_OP_COPY 0x00 69 unsigned int op:8; 70 } ctl_f; 71 }; 72 uint64_t src_addr; 73 uint64_t dst_addr; 74 uint64_t next; 75 uint64_t rsv1; 76 uint64_t rsv2; 77 /* store some driver data in an unused portion of the descriptor */ 78 union { 79 uint64_t user1; 80 uint64_t tx_cnt; 81 }; 82 uint64_t user2; 83 }; 84 85 struct ioat_fill_descriptor { 86 uint32_t size; 87 union { 88 uint32_t ctl; 89 struct { 90 unsigned int int_en:1; 91 unsigned int rsvd:1; 92 unsigned int dest_snoop_dis:1; 93 unsigned int compl_write:1; 94 unsigned int fence:1; 95 unsigned int rsvd2:2; 96 unsigned int dest_brk:1; 97 unsigned int bundle:1; 98 unsigned int rsvd4:15; 99 #define IOAT_OP_FILL 0x01 100 unsigned int op:8; 101 } ctl_f; 102 }; 103 uint64_t src_data; 104 uint64_t dst_addr; 105 uint64_t next; 106 uint64_t rsv1; 107 uint64_t next_dst_addr; 108 uint64_t user1; 109 uint64_t user2; 110 }; 111 112 struct ioat_xor_descriptor { 113 uint32_t size; 114 union { 115 uint32_t ctl; 116 struct { 117 unsigned int int_en:1; 118 unsigned int src_snoop_dis:1; 119 unsigned int dest_snoop_dis:1; 120 unsigned int compl_write:1; 121 unsigned int fence:1; 122 unsigned int src_cnt:3; 123 unsigned int bundle:1; 124 unsigned int dest_dca:1; 125 unsigned int hint:1; 126 unsigned int rsvd:13; 127 #define IOAT_OP_XOR 0x87 128 #define IOAT_OP_XOR_VAL 0x88 129 unsigned int op:8; 130 } ctl_f; 131 }; 132 uint64_t src_addr; 133 uint64_t dst_addr; 134 uint64_t next; 135 uint64_t src_addr2; 136 uint64_t src_addr3; 137 uint64_t src_addr4; 138 uint64_t src_addr5; 139 }; 140 141 struct ioat_xor_ext_descriptor { 142 uint64_t src_addr6; 143 uint64_t src_addr7; 144 uint64_t src_addr8; 145 uint64_t next; 146 uint64_t rsvd[4]; 147 }; 148 149 struct ioat_pq_descriptor { 150 uint32_t size; 151 union { 152 uint32_t ctl; 153 struct { 154 unsigned int int_en:1; 155 unsigned int src_snoop_dis:1; 156 unsigned int dest_snoop_dis:1; 157 unsigned int compl_write:1; 158 unsigned int fence:1; 159 unsigned int src_cnt:3; 160 unsigned int bundle:1; 161 unsigned int dest_dca:1; 162 unsigned int hint:1; 163 unsigned int p_disable:1; 164 unsigned int q_disable:1; 165 unsigned int rsvd:11; 166 #define IOAT_OP_PQ 0x89 167 #define IOAT_OP_PQ_VAL 0x8a 168 unsigned int op:8; 169 } ctl_f; 170 }; 171 uint64_t src_addr; 172 uint64_t p_addr; 173 uint64_t next; 174 uint64_t src_addr2; 175 uint64_t src_addr3; 176 uint8_t coef[8]; 177 uint64_t q_addr; 178 }; 179 180 struct ioat_pq_ext_descriptor { 181 uint64_t src_addr4; 182 uint64_t src_addr5; 183 uint64_t src_addr6; 184 uint64_t next; 185 uint64_t src_addr7; 186 uint64_t src_addr8; 187 uint64_t rsvd[2]; 188 }; 189 190 struct ioat_pq_update_descriptor { 191 uint32_t size; 192 union { 193 uint32_t ctl; 194 struct { 195 unsigned int int_en:1; 196 unsigned int src_snoop_dis:1; 197 unsigned int dest_snoop_dis:1; 198 unsigned int compl_write:1; 199 unsigned int fence:1; 200 unsigned int src_cnt:3; 201 unsigned int bundle:1; 202 unsigned int dest_dca:1; 203 unsigned int hint:1; 204 unsigned int p_disable:1; 205 unsigned int q_disable:1; 206 unsigned int rsvd:3; 207 unsigned int coef:8; 208 #define IOAT_OP_PQ_UP 0x8b 209 unsigned int op:8; 210 } ctl_f; 211 }; 212 uint64_t src_addr; 213 uint64_t p_addr; 214 uint64_t next; 215 uint64_t src_addr2; 216 uint64_t p_src; 217 uint64_t q_src; 218 uint64_t q_addr; 219 }; 220 221 struct ioat_raw_descriptor { 222 uint64_t field[8]; 223 }; 224 #endif 225