1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef IOATDMA_H 18 #define IOATDMA_H 19 20 #include <linux/dmaengine.h> 21 #include <linux/init.h> 22 #include <linux/dmapool.h> 23 #include <linux/cache.h> 24 #include <linux/pci_ids.h> 25 #include <linux/circ_buf.h> 26 #include <linux/interrupt.h> 27 #include "registers.h" 28 #include "hw.h" 29 30 #define IOAT_DMA_VERSION "4.00" 31 32 #define IOAT_DMA_DCA_ANY_CPU ~0 33 34 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev) 35 #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev) 36 #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev) 37 38 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) 39 40 /* ioat hardware assumes at least two sources for raid operations */ 41 #define src_cnt_to_sw(x) ((x) + 2) 42 #define src_cnt_to_hw(x) ((x) - 2) 43 #define ndest_to_sw(x) ((x) + 1) 44 #define ndest_to_hw(x) ((x) - 1) 45 #define src16_cnt_to_sw(x) ((x) + 9) 46 #define src16_cnt_to_hw(x) ((x) - 9) 47 48 /* 49 * workaround for IOAT ver.3.0 null descriptor issue 50 * (channel returns error when size is 0) 51 */ 52 #define NULL_DESC_BUFFER_SIZE 1 53 54 enum ioat_irq_mode { 55 IOAT_NOIRQ = 0, 56 IOAT_MSIX, 57 IOAT_MSI, 58 IOAT_INTX 59 }; 60 61 /** 62 * struct ioatdma_device - internal representation of a IOAT device 63 * @pdev: PCI-Express device 64 * @reg_base: MMIO register space base address 65 * @completion_pool: DMA buffers for completion ops 66 * @sed_hw_pool: DMA super descriptor pools 67 * @dma_dev: embedded struct dma_device 68 * @version: version of ioatdma device 69 * @msix_entries: irq handlers 70 * @idx: per channel data 71 * @dca: direct cache access context 72 * @irq_mode: interrupt mode (INTX, MSI, MSIX) 73 * @cap: read DMA capabilities register 74 */ 75 struct ioatdma_device { 76 struct pci_dev *pdev; 77 void __iomem *reg_base; 78 struct dma_pool *completion_pool; 79 #define MAX_SED_POOLS 5 80 struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; 81 struct dma_device dma_dev; 82 u8 version; 83 #define IOAT_MAX_CHANS 4 84 struct msix_entry msix_entries[IOAT_MAX_CHANS]; 85 struct ioatdma_chan *idx[IOAT_MAX_CHANS]; 86 struct dca_provider *dca; 87 enum ioat_irq_mode irq_mode; 88 u32 cap; 89 90 /* shadow version for CB3.3 chan reset errata workaround */ 91 u64 msixtba0; 92 u64 msixdata0; 93 u32 msixpba; 94 }; 95 96 struct ioat_descs { 97 void *virt; 98 dma_addr_t hw; 99 }; 100 101 struct ioatdma_chan { 102 struct dma_chan dma_chan; 103 void __iomem *reg_base; 104 dma_addr_t last_completion; 105 spinlock_t cleanup_lock; 106 unsigned long state; 107 #define IOAT_CHAN_DOWN 0 108 #define IOAT_COMPLETION_ACK 1 109 #define IOAT_RESET_PENDING 2 110 #define IOAT_KOBJ_INIT_FAIL 3 111 #define IOAT_RUN 5 112 #define IOAT_CHAN_ACTIVE 6 113 struct timer_list timer; 114 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 115 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 116 #define RESET_DELAY msecs_to_jiffies(100) 117 struct ioatdma_device *ioat_dma; 118 dma_addr_t completion_dma; 119 u64 *completion; 120 struct tasklet_struct cleanup_task; 121 struct kobject kobj; 122 123 /* ioat v2 / v3 channel attributes 124 * @xfercap_log; log2 of channel max transfer length (for fast division) 125 * @head: allocated index 126 * @issued: hardware notification point 127 * @tail: cleanup index 128 * @dmacount: identical to 'head' except for occasionally resetting to zero 129 * @alloc_order: log2 of the number of allocated descriptors 130 * @produce: number of descriptors to produce at submit time 131 * @ring: software ring buffer implementation of hardware ring 132 * @prep_lock: serializes descriptor preparation (producers) 133 */ 134 size_t xfercap_log; 135 u16 head; 136 u16 issued; 137 u16 tail; 138 u16 dmacount; 139 u16 alloc_order; 140 u16 produce; 141 struct ioat_ring_ent **ring; 142 spinlock_t prep_lock; 143 struct ioat_descs descs[2]; 144 int desc_chunks; 145 }; 146 147 struct ioat_sysfs_entry { 148 struct attribute attr; 149 ssize_t (*show)(struct dma_chan *, char *); 150 }; 151 152 /** 153 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 154 * @hw: hardware SED 155 * @dma: dma address for the SED 156 * @parent: point to the dma descriptor that's the parent 157 * @hw_pool: descriptor pool index 158 */ 159 struct ioat_sed_ent { 160 struct ioat_sed_raw_descriptor *hw; 161 dma_addr_t dma; 162 struct ioat_ring_ent *parent; 163 unsigned int hw_pool; 164 }; 165 166 /** 167 * struct ioat_ring_ent - wrapper around hardware descriptor 168 * @hw: hardware DMA descriptor (for memcpy) 169 * @xor: hardware xor descriptor 170 * @xor_ex: hardware xor extension descriptor 171 * @pq: hardware pq descriptor 172 * @pq_ex: hardware pq extension descriptor 173 * @pqu: hardware pq update descriptor 174 * @raw: hardware raw (un-typed) descriptor 175 * @txd: the generic software descriptor for all engines 176 * @len: total transaction length for unmap 177 * @result: asynchronous result of validate operations 178 * @id: identifier for debug 179 * @sed: pointer to super extended descriptor sw desc 180 */ 181 182 struct ioat_ring_ent { 183 union { 184 struct ioat_dma_descriptor *hw; 185 struct ioat_xor_descriptor *xor; 186 struct ioat_xor_ext_descriptor *xor_ex; 187 struct ioat_pq_descriptor *pq; 188 struct ioat_pq_ext_descriptor *pq_ex; 189 struct ioat_pq_update_descriptor *pqu; 190 struct ioat_raw_descriptor *raw; 191 }; 192 size_t len; 193 struct dma_async_tx_descriptor txd; 194 enum sum_check_flags *result; 195 #ifdef DEBUG 196 int id; 197 #endif 198 struct ioat_sed_ent *sed; 199 }; 200 201 extern const struct sysfs_ops ioat_sysfs_ops; 202 extern struct ioat_sysfs_entry ioat_version_attr; 203 extern struct ioat_sysfs_entry ioat_cap_attr; 204 extern int ioat_pending_level; 205 extern int ioat_ring_alloc_order; 206 extern struct kobj_type ioat_ktype; 207 extern struct kmem_cache *ioat_cache; 208 extern int ioat_ring_max_alloc_order; 209 extern struct kmem_cache *ioat_sed_cache; 210 211 static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c) 212 { 213 return container_of(c, struct ioatdma_chan, dma_chan); 214 } 215 216 /* wrapper around hardware descriptor format + additional software fields */ 217 #ifdef DEBUG 218 #define set_desc_id(desc, i) ((desc)->id = (i)) 219 #define desc_id(desc) ((desc)->id) 220 #else 221 #define set_desc_id(desc, i) 222 #define desc_id(desc) (0) 223 #endif 224 225 static inline void 226 __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw, 227 struct dma_async_tx_descriptor *tx, int id) 228 { 229 struct device *dev = to_dev(ioat_chan); 230 231 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 232 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, 233 (unsigned long long) tx->phys, 234 (unsigned long long) hw->next, tx->cookie, tx->flags, 235 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 236 } 237 238 #define dump_desc_dbg(c, d) \ 239 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; }) 240 241 static inline struct ioatdma_chan * 242 ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) 243 { 244 return ioat_dma->idx[index]; 245 } 246 247 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) 248 { 249 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); 250 } 251 252 static inline u64 ioat_chansts_to_addr(u64 status) 253 { 254 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 255 } 256 257 static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan) 258 { 259 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 260 } 261 262 static inline void ioat_suspend(struct ioatdma_chan *ioat_chan) 263 { 264 u8 ver = ioat_chan->ioat_dma->version; 265 266 writeb(IOAT_CHANCMD_SUSPEND, 267 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 268 } 269 270 static inline void ioat_reset(struct ioatdma_chan *ioat_chan) 271 { 272 u8 ver = ioat_chan->ioat_dma->version; 273 274 writeb(IOAT_CHANCMD_RESET, 275 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 276 } 277 278 static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan) 279 { 280 u8 ver = ioat_chan->ioat_dma->version; 281 u8 cmd; 282 283 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 284 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 285 } 286 287 static inline bool is_ioat_active(unsigned long status) 288 { 289 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 290 } 291 292 static inline bool is_ioat_idle(unsigned long status) 293 { 294 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 295 } 296 297 static inline bool is_ioat_halted(unsigned long status) 298 { 299 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 300 } 301 302 static inline bool is_ioat_suspended(unsigned long status) 303 { 304 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 305 } 306 307 /* channel was fatally programmed */ 308 static inline bool is_ioat_bug(unsigned long err) 309 { 310 return !!err; 311 } 312 313 #define IOAT_MAX_ORDER 16 314 #define IOAT_MAX_DESCS 65536 315 #define IOAT_DESCS_PER_2M 32768 316 317 static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan) 318 { 319 return 1 << ioat_chan->alloc_order; 320 } 321 322 /* count of descriptors in flight with the engine */ 323 static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan) 324 { 325 return CIRC_CNT(ioat_chan->head, ioat_chan->tail, 326 ioat_ring_size(ioat_chan)); 327 } 328 329 /* count of descriptors pending submission to hardware */ 330 static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan) 331 { 332 return CIRC_CNT(ioat_chan->head, ioat_chan->issued, 333 ioat_ring_size(ioat_chan)); 334 } 335 336 static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan) 337 { 338 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan); 339 } 340 341 static inline u16 342 ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len) 343 { 344 u16 num_descs = len >> ioat_chan->xfercap_log; 345 346 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1)); 347 return num_descs; 348 } 349 350 static inline struct ioat_ring_ent * 351 ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx) 352 { 353 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)]; 354 } 355 356 static inline void 357 ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr) 358 { 359 writel(addr & 0x00000000FFFFFFFF, 360 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); 361 writel(addr >> 32, 362 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); 363 } 364 365 /* IOAT Prep functions */ 366 struct dma_async_tx_descriptor * 367 ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, 368 dma_addr_t dma_src, size_t len, unsigned long flags); 369 struct dma_async_tx_descriptor * 370 ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags); 371 struct dma_async_tx_descriptor * 372 ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 373 unsigned int src_cnt, size_t len, unsigned long flags); 374 struct dma_async_tx_descriptor * 375 ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, 376 unsigned int src_cnt, size_t len, 377 enum sum_check_flags *result, unsigned long flags); 378 struct dma_async_tx_descriptor * 379 ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 380 unsigned int src_cnt, const unsigned char *scf, size_t len, 381 unsigned long flags); 382 struct dma_async_tx_descriptor * 383 ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 384 unsigned int src_cnt, const unsigned char *scf, size_t len, 385 enum sum_check_flags *pqres, unsigned long flags); 386 struct dma_async_tx_descriptor * 387 ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 388 unsigned int src_cnt, size_t len, unsigned long flags); 389 struct dma_async_tx_descriptor * 390 ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, 391 unsigned int src_cnt, size_t len, 392 enum sum_check_flags *result, unsigned long flags); 393 394 /* IOAT Operation functions */ 395 irqreturn_t ioat_dma_do_interrupt(int irq, void *data); 396 irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data); 397 struct ioat_ring_ent ** 398 ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags); 399 void ioat_start_null_desc(struct ioatdma_chan *ioat_chan); 400 void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan); 401 int ioat_reset_hw(struct ioatdma_chan *ioat_chan); 402 enum dma_status 403 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, 404 struct dma_tx_state *txstate); 405 void ioat_cleanup_event(unsigned long data); 406 void ioat_timer_event(unsigned long data); 407 int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs); 408 void ioat_issue_pending(struct dma_chan *chan); 409 void ioat_timer_event(unsigned long data); 410 411 /* IOAT Init functions */ 412 bool is_bwd_ioat(struct pci_dev *pdev); 413 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 414 void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type); 415 void ioat_kobject_del(struct ioatdma_device *ioat_dma); 416 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma); 417 void ioat_stop(struct ioatdma_chan *ioat_chan); 418 #endif /* IOATDMA_H */ 419