1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef IOATDMA_H 18 #define IOATDMA_H 19 20 #include <linux/dmaengine.h> 21 #include "hw.h" 22 #include "registers.h" 23 #include <linux/init.h> 24 #include <linux/dmapool.h> 25 #include <linux/cache.h> 26 #include <linux/pci_ids.h> 27 #include <net/tcp.h> 28 29 #define IOAT_DMA_VERSION "4.00" 30 31 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 32 #define IOAT_DMA_DCA_ANY_CPU ~0 33 34 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 35 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 36 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 37 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 38 #define to_pdev(ioat_chan) ((ioat_chan)->device->pdev) 39 40 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 41 42 /* 43 * workaround for IOAT ver.3.0 null descriptor issue 44 * (channel returns error when size is 0) 45 */ 46 #define NULL_DESC_BUFFER_SIZE 1 47 48 enum ioat_irq_mode { 49 IOAT_NOIRQ = 0, 50 IOAT_MSIX, 51 IOAT_MSI, 52 IOAT_INTX 53 }; 54 55 /** 56 * struct ioatdma_device - internal representation of a IOAT device 57 * @pdev: PCI-Express device 58 * @reg_base: MMIO register space base address 59 * @dma_pool: for allocating DMA descriptors 60 * @common: embedded struct dma_device 61 * @version: version of ioatdma device 62 * @msix_entries: irq handlers 63 * @idx: per channel data 64 * @dca: direct cache access context 65 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 66 * @enumerate_channels: hw version specific channel enumeration 67 * @reset_hw: hw version specific channel (re)initialization 68 * @cleanup_fn: select between the v2 and v3 cleanup routines 69 * @timer_fn: select between the v2 and v3 timer watchdog routines 70 * @self_test: hardware version specific self test for each supported op type 71 * 72 * Note: the v3 cleanup routine supports raid operations 73 */ 74 struct ioatdma_device { 75 struct pci_dev *pdev; 76 void __iomem *reg_base; 77 struct pci_pool *dma_pool; 78 struct pci_pool *completion_pool; 79 #define MAX_SED_POOLS 5 80 struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; 81 struct dma_device common; 82 u8 version; 83 struct msix_entry msix_entries[4]; 84 struct ioat_chan_common *idx[4]; 85 struct dca_provider *dca; 86 enum ioat_irq_mode irq_mode; 87 u32 cap; 88 void (*intr_quirk)(struct ioatdma_device *device); 89 int (*enumerate_channels)(struct ioatdma_device *device); 90 int (*reset_hw)(struct ioat_chan_common *chan); 91 void (*cleanup_fn)(unsigned long data); 92 void (*timer_fn)(unsigned long data); 93 int (*self_test)(struct ioatdma_device *device); 94 }; 95 96 struct ioat_chan_common { 97 struct dma_chan common; 98 void __iomem *reg_base; 99 dma_addr_t last_completion; 100 spinlock_t cleanup_lock; 101 unsigned long state; 102 #define IOAT_COMPLETION_PENDING 0 103 #define IOAT_COMPLETION_ACK 1 104 #define IOAT_RESET_PENDING 2 105 #define IOAT_KOBJ_INIT_FAIL 3 106 #define IOAT_RESHAPE_PENDING 4 107 #define IOAT_RUN 5 108 #define IOAT_CHAN_ACTIVE 6 109 struct timer_list timer; 110 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 111 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 112 #define RESET_DELAY msecs_to_jiffies(100) 113 struct ioatdma_device *device; 114 dma_addr_t completion_dma; 115 u64 *completion; 116 struct tasklet_struct cleanup_task; 117 struct kobject kobj; 118 }; 119 120 struct ioat_sysfs_entry { 121 struct attribute attr; 122 ssize_t (*show)(struct dma_chan *, char *); 123 }; 124 125 /** 126 * struct ioat_dma_chan - internal representation of a DMA channel 127 */ 128 struct ioat_dma_chan { 129 struct ioat_chan_common base; 130 131 size_t xfercap; /* XFERCAP register value expanded out */ 132 133 spinlock_t desc_lock; 134 struct list_head free_desc; 135 struct list_head used_desc; 136 137 int pending; 138 u16 desccount; 139 u16 active; 140 }; 141 142 /** 143 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 144 * @hw: hardware SED 145 * @sed_dma: dma address for the SED 146 * @list: list member 147 * @parent: point to the dma descriptor that's the parent 148 */ 149 struct ioat_sed_ent { 150 struct ioat_sed_raw_descriptor *hw; 151 dma_addr_t dma; 152 struct ioat_ring_ent *parent; 153 unsigned int hw_pool; 154 }; 155 156 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 157 { 158 return container_of(c, struct ioat_chan_common, common); 159 } 160 161 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 162 { 163 struct ioat_chan_common *chan = to_chan_common(c); 164 165 return container_of(chan, struct ioat_dma_chan, base); 166 } 167 168 /* wrapper around hardware descriptor format + additional software fields */ 169 170 /** 171 * struct ioat_desc_sw - wrapper around hardware descriptor 172 * @hw: hardware DMA descriptor (for memcpy) 173 * @node: this descriptor will either be on the free list, 174 * or attached to a transaction list (tx_list) 175 * @txd: the generic software descriptor for all engines 176 * @id: identifier for debug 177 */ 178 struct ioat_desc_sw { 179 struct ioat_dma_descriptor *hw; 180 struct list_head node; 181 size_t len; 182 struct list_head tx_list; 183 struct dma_async_tx_descriptor txd; 184 #ifdef DEBUG 185 int id; 186 #endif 187 }; 188 189 #ifdef DEBUG 190 #define set_desc_id(desc, i) ((desc)->id = (i)) 191 #define desc_id(desc) ((desc)->id) 192 #else 193 #define set_desc_id(desc, i) 194 #define desc_id(desc) (0) 195 #endif 196 197 static inline void 198 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 199 struct dma_async_tx_descriptor *tx, int id) 200 { 201 struct device *dev = to_dev(chan); 202 203 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 204 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, 205 (unsigned long long) tx->phys, 206 (unsigned long long) hw->next, tx->cookie, tx->flags, 207 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 208 } 209 210 #define dump_desc_dbg(c, d) \ 211 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 212 213 static inline struct ioat_chan_common * 214 ioat_chan_by_index(struct ioatdma_device *device, int index) 215 { 216 return device->idx[index]; 217 } 218 219 static inline u64 ioat_chansts_32(struct ioat_chan_common *chan) 220 { 221 u8 ver = chan->device->version; 222 u64 status; 223 u32 status_lo; 224 225 /* We need to read the low address first as this causes the 226 * chipset to latch the upper bits for the subsequent read 227 */ 228 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 229 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 230 status <<= 32; 231 status |= status_lo; 232 233 return status; 234 } 235 236 #if BITS_PER_LONG == 64 237 238 static inline u64 ioat_chansts(struct ioat_chan_common *chan) 239 { 240 u8 ver = chan->device->version; 241 u64 status; 242 243 /* With IOAT v3.3 the status register is 64bit. */ 244 if (ver >= IOAT_VER_3_3) 245 status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); 246 else 247 status = ioat_chansts_32(chan); 248 249 return status; 250 } 251 252 #else 253 #define ioat_chansts ioat_chansts_32 254 #endif 255 256 static inline void ioat_start(struct ioat_chan_common *chan) 257 { 258 u8 ver = chan->device->version; 259 260 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 261 } 262 263 static inline u64 ioat_chansts_to_addr(u64 status) 264 { 265 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 266 } 267 268 static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 269 { 270 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 271 } 272 273 static inline void ioat_suspend(struct ioat_chan_common *chan) 274 { 275 u8 ver = chan->device->version; 276 277 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 278 } 279 280 static inline void ioat_reset(struct ioat_chan_common *chan) 281 { 282 u8 ver = chan->device->version; 283 284 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 285 } 286 287 static inline bool ioat_reset_pending(struct ioat_chan_common *chan) 288 { 289 u8 ver = chan->device->version; 290 u8 cmd; 291 292 cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 293 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 294 } 295 296 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 297 { 298 struct ioat_chan_common *chan = &ioat->base; 299 300 writel(addr & 0x00000000FFFFFFFF, 301 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 302 writel(addr >> 32, 303 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 304 } 305 306 static inline bool is_ioat_active(unsigned long status) 307 { 308 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 309 } 310 311 static inline bool is_ioat_idle(unsigned long status) 312 { 313 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 314 } 315 316 static inline bool is_ioat_halted(unsigned long status) 317 { 318 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 319 } 320 321 static inline bool is_ioat_suspended(unsigned long status) 322 { 323 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 324 } 325 326 /* channel was fatally programmed */ 327 static inline bool is_ioat_bug(unsigned long err) 328 { 329 return !!err; 330 } 331 332 int ioat_probe(struct ioatdma_device *device); 333 int ioat_register(struct ioatdma_device *device); 334 int ioat1_dma_probe(struct ioatdma_device *dev, int dca); 335 int ioat_dma_self_test(struct ioatdma_device *device); 336 void ioat_dma_remove(struct ioatdma_device *device); 337 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 338 dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan); 339 void ioat_init_channel(struct ioatdma_device *device, 340 struct ioat_chan_common *chan, int idx); 341 enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, 342 struct dma_tx_state *txstate); 343 bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 344 dma_addr_t *phys_complete); 345 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 346 void ioat_kobject_del(struct ioatdma_device *device); 347 int ioat_dma_setup_interrupts(struct ioatdma_device *device); 348 void ioat_stop(struct ioat_chan_common *chan); 349 extern const struct sysfs_ops ioat_sysfs_ops; 350 extern struct ioat_sysfs_entry ioat_version_attr; 351 extern struct ioat_sysfs_entry ioat_cap_attr; 352 #endif /* IOATDMA_H */ 353