1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef IOATDMA_H 22 #define IOATDMA_H 23 24 #include <linux/dmaengine.h> 25 #include "hw.h" 26 #include "registers.h" 27 #include <linux/init.h> 28 #include <linux/dmapool.h> 29 #include <linux/cache.h> 30 #include <linux/pci_ids.h> 31 #include <net/tcp.h> 32 33 #define IOAT_DMA_VERSION "4.00" 34 35 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 36 #define IOAT_DMA_DCA_ANY_CPU ~0 37 38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 42 43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 44 45 /* 46 * workaround for IOAT ver.3.0 null descriptor issue 47 * (channel returns error when size is 0) 48 */ 49 #define NULL_DESC_BUFFER_SIZE 1 50 51 /** 52 * struct ioatdma_device - internal representation of a IOAT device 53 * @pdev: PCI-Express device 54 * @reg_base: MMIO register space base address 55 * @dma_pool: for allocating DMA descriptors 56 * @common: embedded struct dma_device 57 * @version: version of ioatdma device 58 * @msix_entries: irq handlers 59 * @idx: per channel data 60 * @dca: direct cache access context 61 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 62 * @enumerate_channels: hw version specific channel enumeration 63 * @reset_hw: hw version specific channel (re)initialization 64 * @cleanup_fn: select between the v2 and v3 cleanup routines 65 * @timer_fn: select between the v2 and v3 timer watchdog routines 66 * @self_test: hardware version specific self test for each supported op type 67 * 68 * Note: the v3 cleanup routine supports raid operations 69 */ 70 struct ioatdma_device { 71 struct pci_dev *pdev; 72 void __iomem *reg_base; 73 struct pci_pool *dma_pool; 74 struct pci_pool *completion_pool; 75 struct dma_device common; 76 u8 version; 77 struct msix_entry msix_entries[4]; 78 struct ioat_chan_common *idx[4]; 79 struct dca_provider *dca; 80 void (*intr_quirk)(struct ioatdma_device *device); 81 int (*enumerate_channels)(struct ioatdma_device *device); 82 int (*reset_hw)(struct ioat_chan_common *chan); 83 void (*cleanup_fn)(unsigned long data); 84 void (*timer_fn)(unsigned long data); 85 int (*self_test)(struct ioatdma_device *device); 86 }; 87 88 struct ioat_chan_common { 89 struct dma_chan common; 90 void __iomem *reg_base; 91 unsigned long last_completion; 92 spinlock_t cleanup_lock; 93 dma_cookie_t completed_cookie; 94 unsigned long state; 95 #define IOAT_COMPLETION_PENDING 0 96 #define IOAT_COMPLETION_ACK 1 97 #define IOAT_RESET_PENDING 2 98 #define IOAT_KOBJ_INIT_FAIL 3 99 #define IOAT_RESHAPE_PENDING 4 100 #define IOAT_RUN 5 101 struct timer_list timer; 102 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 103 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 104 #define RESET_DELAY msecs_to_jiffies(100) 105 struct ioatdma_device *device; 106 dma_addr_t completion_dma; 107 u64 *completion; 108 struct tasklet_struct cleanup_task; 109 struct kobject kobj; 110 }; 111 112 struct ioat_sysfs_entry { 113 struct attribute attr; 114 ssize_t (*show)(struct dma_chan *, char *); 115 }; 116 117 /** 118 * struct ioat_dma_chan - internal representation of a DMA channel 119 */ 120 struct ioat_dma_chan { 121 struct ioat_chan_common base; 122 123 size_t xfercap; /* XFERCAP register value expanded out */ 124 125 spinlock_t desc_lock; 126 struct list_head free_desc; 127 struct list_head used_desc; 128 129 int pending; 130 u16 desccount; 131 u16 active; 132 }; 133 134 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 135 { 136 return container_of(c, struct ioat_chan_common, common); 137 } 138 139 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 140 { 141 struct ioat_chan_common *chan = to_chan_common(c); 142 143 return container_of(chan, struct ioat_dma_chan, base); 144 } 145 146 /** 147 * ioat_tx_status - poll the status of an ioat transaction 148 * @c: channel handle 149 * @cookie: transaction identifier 150 * @txstate: if set, updated with the transaction state 151 */ 152 static inline enum dma_status 153 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, 154 struct dma_tx_state *txstate) 155 { 156 struct ioat_chan_common *chan = to_chan_common(c); 157 dma_cookie_t last_used; 158 dma_cookie_t last_complete; 159 160 last_used = c->cookie; 161 last_complete = chan->completed_cookie; 162 163 dma_set_tx_state(txstate, last_complete, last_used, 0); 164 165 return dma_async_is_complete(cookie, last_complete, last_used); 166 } 167 168 /* wrapper around hardware descriptor format + additional software fields */ 169 170 /** 171 * struct ioat_desc_sw - wrapper around hardware descriptor 172 * @hw: hardware DMA descriptor (for memcpy) 173 * @node: this descriptor will either be on the free list, 174 * or attached to a transaction list (tx_list) 175 * @txd: the generic software descriptor for all engines 176 * @id: identifier for debug 177 */ 178 struct ioat_desc_sw { 179 struct ioat_dma_descriptor *hw; 180 struct list_head node; 181 size_t len; 182 struct list_head tx_list; 183 struct dma_async_tx_descriptor txd; 184 #ifdef DEBUG 185 int id; 186 #endif 187 }; 188 189 #ifdef DEBUG 190 #define set_desc_id(desc, i) ((desc)->id = (i)) 191 #define desc_id(desc) ((desc)->id) 192 #else 193 #define set_desc_id(desc, i) 194 #define desc_id(desc) (0) 195 #endif 196 197 static inline void 198 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 199 struct dma_async_tx_descriptor *tx, int id) 200 { 201 struct device *dev = to_dev(chan); 202 203 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 204 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id, 205 (unsigned long long) tx->phys, 206 (unsigned long long) hw->next, tx->cookie, tx->flags, 207 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 208 } 209 210 #define dump_desc_dbg(c, d) \ 211 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 212 213 static inline void ioat_set_tcp_copy_break(unsigned long copybreak) 214 { 215 #ifdef CONFIG_NET_DMA 216 sysctl_tcp_dma_copybreak = copybreak; 217 #endif 218 } 219 220 static inline struct ioat_chan_common * 221 ioat_chan_by_index(struct ioatdma_device *device, int index) 222 { 223 return device->idx[index]; 224 } 225 226 static inline u64 ioat_chansts(struct ioat_chan_common *chan) 227 { 228 u8 ver = chan->device->version; 229 u64 status; 230 u32 status_lo; 231 232 /* We need to read the low address first as this causes the 233 * chipset to latch the upper bits for the subsequent read 234 */ 235 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 236 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 237 status <<= 32; 238 status |= status_lo; 239 240 return status; 241 } 242 243 static inline void ioat_start(struct ioat_chan_common *chan) 244 { 245 u8 ver = chan->device->version; 246 247 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 248 } 249 250 static inline u64 ioat_chansts_to_addr(u64 status) 251 { 252 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 253 } 254 255 static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 256 { 257 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 258 } 259 260 static inline void ioat_suspend(struct ioat_chan_common *chan) 261 { 262 u8 ver = chan->device->version; 263 264 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 265 } 266 267 static inline void ioat_reset(struct ioat_chan_common *chan) 268 { 269 u8 ver = chan->device->version; 270 271 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 272 } 273 274 static inline bool ioat_reset_pending(struct ioat_chan_common *chan) 275 { 276 u8 ver = chan->device->version; 277 u8 cmd; 278 279 cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 280 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 281 } 282 283 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 284 { 285 struct ioat_chan_common *chan = &ioat->base; 286 287 writel(addr & 0x00000000FFFFFFFF, 288 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 289 writel(addr >> 32, 290 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 291 } 292 293 static inline bool is_ioat_active(unsigned long status) 294 { 295 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 296 } 297 298 static inline bool is_ioat_idle(unsigned long status) 299 { 300 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 301 } 302 303 static inline bool is_ioat_halted(unsigned long status) 304 { 305 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 306 } 307 308 static inline bool is_ioat_suspended(unsigned long status) 309 { 310 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 311 } 312 313 /* channel was fatally programmed */ 314 static inline bool is_ioat_bug(unsigned long err) 315 { 316 return !!err; 317 } 318 319 static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, 320 int direction, enum dma_ctrl_flags flags, bool dst) 321 { 322 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || 323 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) 324 pci_unmap_single(pdev, addr, len, direction); 325 else 326 pci_unmap_page(pdev, addr, len, direction); 327 } 328 329 int __devinit ioat_probe(struct ioatdma_device *device); 330 int __devinit ioat_register(struct ioatdma_device *device); 331 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); 332 int __devinit ioat_dma_self_test(struct ioatdma_device *device); 333 void __devexit ioat_dma_remove(struct ioatdma_device *device); 334 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, 335 void __iomem *iobase); 336 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); 337 void ioat_init_channel(struct ioatdma_device *device, 338 struct ioat_chan_common *chan, int idx); 339 enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, 340 struct dma_tx_state *txstate); 341 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, 342 size_t len, struct ioat_dma_descriptor *hw); 343 bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 344 unsigned long *phys_complete); 345 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 346 void ioat_kobject_del(struct ioatdma_device *device); 347 extern const struct sysfs_ops ioat_sysfs_ops; 348 extern struct ioat_sysfs_entry ioat_version_attr; 349 extern struct ioat_sysfs_entry ioat_cap_attr; 350 #endif /* IOATDMA_H */ 351