1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef IOATDMA_H 22 #define IOATDMA_H 23 24 #include <linux/dmaengine.h> 25 #include "hw.h" 26 #include "registers.h" 27 #include <linux/init.h> 28 #include <linux/dmapool.h> 29 #include <linux/cache.h> 30 #include <linux/pci_ids.h> 31 #include <net/tcp.h> 32 33 #define IOAT_DMA_VERSION "4.00" 34 35 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 36 #define IOAT_DMA_DCA_ANY_CPU ~0 37 38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 42 43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 44 45 /* 46 * workaround for IOAT ver.3.0 null descriptor issue 47 * (channel returns error when size is 0) 48 */ 49 #define NULL_DESC_BUFFER_SIZE 1 50 51 /** 52 * struct ioatdma_device - internal representation of a IOAT device 53 * @pdev: PCI-Express device 54 * @reg_base: MMIO register space base address 55 * @dma_pool: for allocating DMA descriptors 56 * @common: embedded struct dma_device 57 * @version: version of ioatdma device 58 * @msix_entries: irq handlers 59 * @idx: per channel data 60 * @dca: direct cache access context 61 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 62 * @enumerate_channels: hw version specific channel enumeration 63 * @cleanup_tasklet: select between the v2 and v3 cleanup routines 64 * @timer_fn: select between the v2 and v3 timer watchdog routines 65 * @self_test: hardware version specific self test for each supported op type 66 * 67 * Note: the v3 cleanup routine supports raid operations 68 */ 69 struct ioatdma_device { 70 struct pci_dev *pdev; 71 void __iomem *reg_base; 72 struct pci_pool *dma_pool; 73 struct pci_pool *completion_pool; 74 struct dma_device common; 75 u8 version; 76 struct msix_entry msix_entries[4]; 77 struct ioat_chan_common *idx[4]; 78 struct dca_provider *dca; 79 void (*intr_quirk)(struct ioatdma_device *device); 80 int (*enumerate_channels)(struct ioatdma_device *device); 81 void (*cleanup_tasklet)(unsigned long data); 82 void (*timer_fn)(unsigned long data); 83 int (*self_test)(struct ioatdma_device *device); 84 }; 85 86 struct ioat_chan_common { 87 struct dma_chan common; 88 void __iomem *reg_base; 89 unsigned long last_completion; 90 spinlock_t cleanup_lock; 91 dma_cookie_t completed_cookie; 92 unsigned long state; 93 #define IOAT_COMPLETION_PENDING 0 94 #define IOAT_COMPLETION_ACK 1 95 #define IOAT_RESET_PENDING 2 96 #define IOAT_KOBJ_INIT_FAIL 3 97 struct timer_list timer; 98 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 99 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 100 #define RESET_DELAY msecs_to_jiffies(100) 101 struct ioatdma_device *device; 102 dma_addr_t completion_dma; 103 u64 *completion; 104 struct tasklet_struct cleanup_task; 105 struct kobject kobj; 106 }; 107 108 struct ioat_sysfs_entry { 109 struct attribute attr; 110 ssize_t (*show)(struct dma_chan *, char *); 111 }; 112 113 /** 114 * struct ioat_dma_chan - internal representation of a DMA channel 115 */ 116 struct ioat_dma_chan { 117 struct ioat_chan_common base; 118 119 size_t xfercap; /* XFERCAP register value expanded out */ 120 121 spinlock_t desc_lock; 122 struct list_head free_desc; 123 struct list_head used_desc; 124 125 int pending; 126 u16 desccount; 127 u16 active; 128 }; 129 130 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 131 { 132 return container_of(c, struct ioat_chan_common, common); 133 } 134 135 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 136 { 137 struct ioat_chan_common *chan = to_chan_common(c); 138 139 return container_of(chan, struct ioat_dma_chan, base); 140 } 141 142 /** 143 * ioat_is_complete - poll the status of an ioat transaction 144 * @c: channel handle 145 * @cookie: transaction identifier 146 * @done: if set, updated with last completed transaction 147 * @used: if set, updated with last used transaction 148 */ 149 static inline enum dma_status 150 ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, 151 dma_cookie_t *done, dma_cookie_t *used) 152 { 153 struct ioat_chan_common *chan = to_chan_common(c); 154 dma_cookie_t last_used; 155 dma_cookie_t last_complete; 156 157 last_used = c->cookie; 158 last_complete = chan->completed_cookie; 159 160 if (done) 161 *done = last_complete; 162 if (used) 163 *used = last_used; 164 165 return dma_async_is_complete(cookie, last_complete, last_used); 166 } 167 168 /* wrapper around hardware descriptor format + additional software fields */ 169 170 /** 171 * struct ioat_desc_sw - wrapper around hardware descriptor 172 * @hw: hardware DMA descriptor (for memcpy) 173 * @node: this descriptor will either be on the free list, 174 * or attached to a transaction list (tx_list) 175 * @txd: the generic software descriptor for all engines 176 * @id: identifier for debug 177 */ 178 struct ioat_desc_sw { 179 struct ioat_dma_descriptor *hw; 180 struct list_head node; 181 size_t len; 182 struct list_head tx_list; 183 struct dma_async_tx_descriptor txd; 184 #ifdef DEBUG 185 int id; 186 #endif 187 }; 188 189 #ifdef DEBUG 190 #define set_desc_id(desc, i) ((desc)->id = (i)) 191 #define desc_id(desc) ((desc)->id) 192 #else 193 #define set_desc_id(desc, i) 194 #define desc_id(desc) (0) 195 #endif 196 197 static inline void 198 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 199 struct dma_async_tx_descriptor *tx, int id) 200 { 201 struct device *dev = to_dev(chan); 202 203 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 204 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id, 205 (unsigned long long) tx->phys, 206 (unsigned long long) hw->next, tx->cookie, tx->flags, 207 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 208 } 209 210 #define dump_desc_dbg(c, d) \ 211 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 212 213 static inline void ioat_set_tcp_copy_break(unsigned long copybreak) 214 { 215 #ifdef CONFIG_NET_DMA 216 sysctl_tcp_dma_copybreak = copybreak; 217 #endif 218 } 219 220 static inline struct ioat_chan_common * 221 ioat_chan_by_index(struct ioatdma_device *device, int index) 222 { 223 return device->idx[index]; 224 } 225 226 static inline u64 ioat_chansts(struct ioat_chan_common *chan) 227 { 228 u8 ver = chan->device->version; 229 u64 status; 230 u32 status_lo; 231 232 /* We need to read the low address first as this causes the 233 * chipset to latch the upper bits for the subsequent read 234 */ 235 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 236 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 237 status <<= 32; 238 status |= status_lo; 239 240 return status; 241 } 242 243 static inline void ioat_start(struct ioat_chan_common *chan) 244 { 245 u8 ver = chan->device->version; 246 247 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 248 } 249 250 static inline u64 ioat_chansts_to_addr(u64 status) 251 { 252 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 253 } 254 255 static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 256 { 257 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 258 } 259 260 static inline void ioat_suspend(struct ioat_chan_common *chan) 261 { 262 u8 ver = chan->device->version; 263 264 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 265 } 266 267 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 268 { 269 struct ioat_chan_common *chan = &ioat->base; 270 271 writel(addr & 0x00000000FFFFFFFF, 272 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 273 writel(addr >> 32, 274 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 275 } 276 277 static inline bool is_ioat_active(unsigned long status) 278 { 279 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 280 } 281 282 static inline bool is_ioat_idle(unsigned long status) 283 { 284 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 285 } 286 287 static inline bool is_ioat_halted(unsigned long status) 288 { 289 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 290 } 291 292 static inline bool is_ioat_suspended(unsigned long status) 293 { 294 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 295 } 296 297 /* channel was fatally programmed */ 298 static inline bool is_ioat_bug(unsigned long err) 299 { 300 return !!err; 301 } 302 303 static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, 304 int direction, enum dma_ctrl_flags flags, bool dst) 305 { 306 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || 307 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) 308 pci_unmap_single(pdev, addr, len, direction); 309 else 310 pci_unmap_page(pdev, addr, len, direction); 311 } 312 313 int __devinit ioat_probe(struct ioatdma_device *device); 314 int __devinit ioat_register(struct ioatdma_device *device); 315 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); 316 int __devinit ioat_dma_self_test(struct ioatdma_device *device); 317 void __devexit ioat_dma_remove(struct ioatdma_device *device); 318 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, 319 void __iomem *iobase); 320 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); 321 void ioat_init_channel(struct ioatdma_device *device, 322 struct ioat_chan_common *chan, int idx, 323 void (*timer_fn)(unsigned long), 324 void (*tasklet)(unsigned long), 325 unsigned long ioat); 326 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, 327 size_t len, struct ioat_dma_descriptor *hw); 328 bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 329 unsigned long *phys_complete); 330 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 331 void ioat_kobject_del(struct ioatdma_device *device); 332 extern struct sysfs_ops ioat_sysfs_ops; 333 extern struct ioat_sysfs_entry ioat_version_attr; 334 extern struct ioat_sysfs_entry ioat_cap_attr; 335 #endif /* IOATDMA_H */ 336