1 /* 2 * drivers/dma/imx-sdma.c 3 * 4 * This file contains a driver for the Freescale Smart DMA engine 5 * 6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 7 * 8 * Based on code from Freescale: 9 * 10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 11 * 12 * The code contained herein is licensed under the GNU General Public 13 * License. You may obtain a copy of the GNU General Public License 14 * Version 2 or later at the following locations: 15 * 16 * http://www.opensource.org/licenses/gpl-license.html 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/mm.h> 25 #include <linux/interrupt.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/sched.h> 29 #include <linux/semaphore.h> 30 #include <linux/spinlock.h> 31 #include <linux/device.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/firmware.h> 34 #include <linux/slab.h> 35 #include <linux/platform_device.h> 36 #include <linux/dmaengine.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_dma.h> 40 41 #include <asm/irq.h> 42 #include <linux/platform_data/dma-imx-sdma.h> 43 #include <linux/platform_data/dma-imx.h> 44 45 #include "dmaengine.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * Mode/Count of data node descriptors - IPCv2 128 */ 129 struct sdma_mode_count { 130 u32 count : 16; /* size of the buffer pointed by this BD */ 131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 132 u32 command : 8; /* command mostlky used for channel 0 */ 133 }; 134 135 /* 136 * Buffer descriptor 137 */ 138 struct sdma_buffer_descriptor { 139 struct sdma_mode_count mode; 140 u32 buffer_addr; /* address of the buffer described */ 141 u32 ext_buffer_addr; /* extended buffer address */ 142 } __attribute__ ((packed)); 143 144 /** 145 * struct sdma_channel_control - Channel control Block 146 * 147 * @current_bd_ptr current buffer descriptor processed 148 * @base_bd_ptr first element of buffer descriptor array 149 * @unused padding. The SDMA engine expects an array of 128 byte 150 * control blocks 151 */ 152 struct sdma_channel_control { 153 u32 current_bd_ptr; 154 u32 base_bd_ptr; 155 u32 unused[2]; 156 } __attribute__ ((packed)); 157 158 /** 159 * struct sdma_state_registers - SDMA context for a channel 160 * 161 * @pc: program counter 162 * @t: test bit: status of arithmetic & test instruction 163 * @rpc: return program counter 164 * @sf: source fault while loading data 165 * @spc: loop start program counter 166 * @df: destination fault while storing data 167 * @epc: loop end program counter 168 * @lm: loop mode 169 */ 170 struct sdma_state_registers { 171 u32 pc :14; 172 u32 unused1: 1; 173 u32 t : 1; 174 u32 rpc :14; 175 u32 unused0: 1; 176 u32 sf : 1; 177 u32 spc :14; 178 u32 unused2: 1; 179 u32 df : 1; 180 u32 epc :14; 181 u32 lm : 2; 182 } __attribute__ ((packed)); 183 184 /** 185 * struct sdma_context_data - sdma context specific to a channel 186 * 187 * @channel_state: channel state bits 188 * @gReg: general registers 189 * @mda: burst dma destination address register 190 * @msa: burst dma source address register 191 * @ms: burst dma status register 192 * @md: burst dma data register 193 * @pda: peripheral dma destination address register 194 * @psa: peripheral dma source address register 195 * @ps: peripheral dma status register 196 * @pd: peripheral dma data register 197 * @ca: CRC polynomial register 198 * @cs: CRC accumulator register 199 * @dda: dedicated core destination address register 200 * @dsa: dedicated core source address register 201 * @ds: dedicated core status register 202 * @dd: dedicated core data register 203 */ 204 struct sdma_context_data { 205 struct sdma_state_registers channel_state; 206 u32 gReg[8]; 207 u32 mda; 208 u32 msa; 209 u32 ms; 210 u32 md; 211 u32 pda; 212 u32 psa; 213 u32 ps; 214 u32 pd; 215 u32 ca; 216 u32 cs; 217 u32 dda; 218 u32 dsa; 219 u32 ds; 220 u32 dd; 221 u32 scratch0; 222 u32 scratch1; 223 u32 scratch2; 224 u32 scratch3; 225 u32 scratch4; 226 u32 scratch5; 227 u32 scratch6; 228 u32 scratch7; 229 } __attribute__ ((packed)); 230 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 232 233 struct sdma_engine; 234 235 /** 236 * struct sdma_channel - housekeeping for a SDMA channel 237 * 238 * @sdma pointer to the SDMA engine for this channel 239 * @channel the channel number, matches dmaengine chan_id + 1 240 * @direction transfer type. Needed for setting SDMA script 241 * @peripheral_type Peripheral type. Needed for setting SDMA script 242 * @event_id0 aka dma request line 243 * @event_id1 for channels that use 2 events 244 * @word_size peripheral access size 245 * @buf_tail ID of the buffer that was processed 246 * @num_bd max NUM_BD. number of descriptors currently handling 247 */ 248 struct sdma_channel { 249 struct sdma_engine *sdma; 250 unsigned int channel; 251 enum dma_transfer_direction direction; 252 enum sdma_peripheral_type peripheral_type; 253 unsigned int event_id0; 254 unsigned int event_id1; 255 enum dma_slave_buswidth word_size; 256 unsigned int buf_tail; 257 unsigned int num_bd; 258 unsigned int period_len; 259 struct sdma_buffer_descriptor *bd; 260 dma_addr_t bd_phys; 261 unsigned int pc_from_device, pc_to_device; 262 unsigned long flags; 263 dma_addr_t per_address; 264 unsigned long event_mask[2]; 265 unsigned long watermark_level; 266 u32 shp_addr, per_addr; 267 struct dma_chan chan; 268 spinlock_t lock; 269 struct dma_async_tx_descriptor desc; 270 enum dma_status status; 271 unsigned int chn_count; 272 unsigned int chn_real_count; 273 struct tasklet_struct tasklet; 274 struct imx_dma_data data; 275 }; 276 277 #define IMX_DMA_SG_LOOP BIT(0) 278 279 #define MAX_DMA_CHANNELS 32 280 #define MXC_SDMA_DEFAULT_PRIORITY 1 281 #define MXC_SDMA_MIN_PRIORITY 1 282 #define MXC_SDMA_MAX_PRIORITY 7 283 284 #define SDMA_FIRMWARE_MAGIC 0x414d4453 285 286 /** 287 * struct sdma_firmware_header - Layout of the firmware image 288 * 289 * @magic "SDMA" 290 * @version_major increased whenever layout of struct sdma_script_start_addrs 291 * changes. 292 * @version_minor firmware minor version (for binary compatible changes) 293 * @script_addrs_start offset of struct sdma_script_start_addrs in this image 294 * @num_script_addrs Number of script addresses in this image 295 * @ram_code_start offset of SDMA ram image in this firmware image 296 * @ram_code_size size of SDMA ram image 297 * @script_addrs Stores the start address of the SDMA scripts 298 * (in SDMA memory space) 299 */ 300 struct sdma_firmware_header { 301 u32 magic; 302 u32 version_major; 303 u32 version_minor; 304 u32 script_addrs_start; 305 u32 num_script_addrs; 306 u32 ram_code_start; 307 u32 ram_code_size; 308 }; 309 310 struct sdma_driver_data { 311 int chnenbl0; 312 int num_events; 313 struct sdma_script_start_addrs *script_addrs; 314 }; 315 316 struct sdma_engine { 317 struct device *dev; 318 struct device_dma_parameters dma_parms; 319 struct sdma_channel channel[MAX_DMA_CHANNELS]; 320 struct sdma_channel_control *channel_control; 321 void __iomem *regs; 322 struct sdma_context_data *context; 323 dma_addr_t context_phys; 324 struct dma_device dma_device; 325 struct clk *clk_ipg; 326 struct clk *clk_ahb; 327 spinlock_t channel_0_lock; 328 u32 script_number; 329 struct sdma_script_start_addrs *script_addrs; 330 const struct sdma_driver_data *drvdata; 331 }; 332 333 static struct sdma_driver_data sdma_imx31 = { 334 .chnenbl0 = SDMA_CHNENBL0_IMX31, 335 .num_events = 32, 336 }; 337 338 static struct sdma_script_start_addrs sdma_script_imx25 = { 339 .ap_2_ap_addr = 729, 340 .uart_2_mcu_addr = 904, 341 .per_2_app_addr = 1255, 342 .mcu_2_app_addr = 834, 343 .uartsh_2_mcu_addr = 1120, 344 .per_2_shp_addr = 1329, 345 .mcu_2_shp_addr = 1048, 346 .ata_2_mcu_addr = 1560, 347 .mcu_2_ata_addr = 1479, 348 .app_2_per_addr = 1189, 349 .app_2_mcu_addr = 770, 350 .shp_2_per_addr = 1407, 351 .shp_2_mcu_addr = 979, 352 }; 353 354 static struct sdma_driver_data sdma_imx25 = { 355 .chnenbl0 = SDMA_CHNENBL0_IMX35, 356 .num_events = 48, 357 .script_addrs = &sdma_script_imx25, 358 }; 359 360 static struct sdma_driver_data sdma_imx35 = { 361 .chnenbl0 = SDMA_CHNENBL0_IMX35, 362 .num_events = 48, 363 }; 364 365 static struct sdma_script_start_addrs sdma_script_imx51 = { 366 .ap_2_ap_addr = 642, 367 .uart_2_mcu_addr = 817, 368 .mcu_2_app_addr = 747, 369 .mcu_2_shp_addr = 961, 370 .ata_2_mcu_addr = 1473, 371 .mcu_2_ata_addr = 1392, 372 .app_2_per_addr = 1033, 373 .app_2_mcu_addr = 683, 374 .shp_2_per_addr = 1251, 375 .shp_2_mcu_addr = 892, 376 }; 377 378 static struct sdma_driver_data sdma_imx51 = { 379 .chnenbl0 = SDMA_CHNENBL0_IMX35, 380 .num_events = 48, 381 .script_addrs = &sdma_script_imx51, 382 }; 383 384 static struct sdma_script_start_addrs sdma_script_imx53 = { 385 .ap_2_ap_addr = 642, 386 .app_2_mcu_addr = 683, 387 .mcu_2_app_addr = 747, 388 .uart_2_mcu_addr = 817, 389 .shp_2_mcu_addr = 891, 390 .mcu_2_shp_addr = 960, 391 .uartsh_2_mcu_addr = 1032, 392 .spdif_2_mcu_addr = 1100, 393 .mcu_2_spdif_addr = 1134, 394 .firi_2_mcu_addr = 1193, 395 .mcu_2_firi_addr = 1290, 396 }; 397 398 static struct sdma_driver_data sdma_imx53 = { 399 .chnenbl0 = SDMA_CHNENBL0_IMX35, 400 .num_events = 48, 401 .script_addrs = &sdma_script_imx53, 402 }; 403 404 static struct sdma_script_start_addrs sdma_script_imx6q = { 405 .ap_2_ap_addr = 642, 406 .uart_2_mcu_addr = 817, 407 .mcu_2_app_addr = 747, 408 .per_2_per_addr = 6331, 409 .uartsh_2_mcu_addr = 1032, 410 .mcu_2_shp_addr = 960, 411 .app_2_mcu_addr = 683, 412 .shp_2_mcu_addr = 891, 413 .spdif_2_mcu_addr = 1100, 414 .mcu_2_spdif_addr = 1134, 415 }; 416 417 static struct sdma_driver_data sdma_imx6q = { 418 .chnenbl0 = SDMA_CHNENBL0_IMX35, 419 .num_events = 48, 420 .script_addrs = &sdma_script_imx6q, 421 }; 422 423 static struct platform_device_id sdma_devtypes[] = { 424 { 425 .name = "imx25-sdma", 426 .driver_data = (unsigned long)&sdma_imx25, 427 }, { 428 .name = "imx31-sdma", 429 .driver_data = (unsigned long)&sdma_imx31, 430 }, { 431 .name = "imx35-sdma", 432 .driver_data = (unsigned long)&sdma_imx35, 433 }, { 434 .name = "imx51-sdma", 435 .driver_data = (unsigned long)&sdma_imx51, 436 }, { 437 .name = "imx53-sdma", 438 .driver_data = (unsigned long)&sdma_imx53, 439 }, { 440 .name = "imx6q-sdma", 441 .driver_data = (unsigned long)&sdma_imx6q, 442 }, { 443 /* sentinel */ 444 } 445 }; 446 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 447 448 static const struct of_device_id sdma_dt_ids[] = { 449 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 450 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 451 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 452 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 453 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 454 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 455 { /* sentinel */ } 456 }; 457 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 458 459 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 460 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 461 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 462 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 463 464 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 465 { 466 u32 chnenbl0 = sdma->drvdata->chnenbl0; 467 return chnenbl0 + event * 4; 468 } 469 470 static int sdma_config_ownership(struct sdma_channel *sdmac, 471 bool event_override, bool mcu_override, bool dsp_override) 472 { 473 struct sdma_engine *sdma = sdmac->sdma; 474 int channel = sdmac->channel; 475 unsigned long evt, mcu, dsp; 476 477 if (event_override && mcu_override && dsp_override) 478 return -EINVAL; 479 480 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 481 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 482 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 483 484 if (dsp_override) 485 __clear_bit(channel, &dsp); 486 else 487 __set_bit(channel, &dsp); 488 489 if (event_override) 490 __clear_bit(channel, &evt); 491 else 492 __set_bit(channel, &evt); 493 494 if (mcu_override) 495 __clear_bit(channel, &mcu); 496 else 497 __set_bit(channel, &mcu); 498 499 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 500 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 501 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 502 503 return 0; 504 } 505 506 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 507 { 508 writel(BIT(channel), sdma->regs + SDMA_H_START); 509 } 510 511 /* 512 * sdma_run_channel0 - run a channel and wait till it's done 513 */ 514 static int sdma_run_channel0(struct sdma_engine *sdma) 515 { 516 int ret; 517 unsigned long timeout = 500; 518 519 sdma_enable_channel(sdma, 0); 520 521 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { 522 if (timeout-- <= 0) 523 break; 524 udelay(1); 525 } 526 527 if (ret) { 528 /* Clear the interrupt status */ 529 writel_relaxed(ret, sdma->regs + SDMA_H_INTR); 530 } else { 531 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 532 } 533 534 return ret ? 0 : -ETIMEDOUT; 535 } 536 537 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 538 u32 address) 539 { 540 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 541 void *buf_virt; 542 dma_addr_t buf_phys; 543 int ret; 544 unsigned long flags; 545 546 buf_virt = dma_alloc_coherent(NULL, 547 size, 548 &buf_phys, GFP_KERNEL); 549 if (!buf_virt) { 550 return -ENOMEM; 551 } 552 553 spin_lock_irqsave(&sdma->channel_0_lock, flags); 554 555 bd0->mode.command = C0_SETPM; 556 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 557 bd0->mode.count = size / 2; 558 bd0->buffer_addr = buf_phys; 559 bd0->ext_buffer_addr = address; 560 561 memcpy(buf_virt, buf, size); 562 563 ret = sdma_run_channel0(sdma); 564 565 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 566 567 dma_free_coherent(NULL, size, buf_virt, buf_phys); 568 569 return ret; 570 } 571 572 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 573 { 574 struct sdma_engine *sdma = sdmac->sdma; 575 int channel = sdmac->channel; 576 unsigned long val; 577 u32 chnenbl = chnenbl_ofs(sdma, event); 578 579 val = readl_relaxed(sdma->regs + chnenbl); 580 __set_bit(channel, &val); 581 writel_relaxed(val, sdma->regs + chnenbl); 582 } 583 584 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 585 { 586 struct sdma_engine *sdma = sdmac->sdma; 587 int channel = sdmac->channel; 588 u32 chnenbl = chnenbl_ofs(sdma, event); 589 unsigned long val; 590 591 val = readl_relaxed(sdma->regs + chnenbl); 592 __clear_bit(channel, &val); 593 writel_relaxed(val, sdma->regs + chnenbl); 594 } 595 596 static void sdma_handle_channel_loop(struct sdma_channel *sdmac) 597 { 598 if (sdmac->desc.callback) 599 sdmac->desc.callback(sdmac->desc.callback_param); 600 } 601 602 static void sdma_update_channel_loop(struct sdma_channel *sdmac) 603 { 604 struct sdma_buffer_descriptor *bd; 605 606 /* 607 * loop mode. Iterate over descriptors, re-setup them and 608 * call callback function. 609 */ 610 while (1) { 611 bd = &sdmac->bd[sdmac->buf_tail]; 612 613 if (bd->mode.status & BD_DONE) 614 break; 615 616 if (bd->mode.status & BD_RROR) 617 sdmac->status = DMA_ERROR; 618 619 bd->mode.status |= BD_DONE; 620 sdmac->buf_tail++; 621 sdmac->buf_tail %= sdmac->num_bd; 622 } 623 } 624 625 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) 626 { 627 struct sdma_buffer_descriptor *bd; 628 int i, error = 0; 629 630 sdmac->chn_real_count = 0; 631 /* 632 * non loop mode. Iterate over all descriptors, collect 633 * errors and call callback function 634 */ 635 for (i = 0; i < sdmac->num_bd; i++) { 636 bd = &sdmac->bd[i]; 637 638 if (bd->mode.status & (BD_DONE | BD_RROR)) 639 error = -EIO; 640 sdmac->chn_real_count += bd->mode.count; 641 } 642 643 if (error) 644 sdmac->status = DMA_ERROR; 645 else 646 sdmac->status = DMA_COMPLETE; 647 648 dma_cookie_complete(&sdmac->desc); 649 if (sdmac->desc.callback) 650 sdmac->desc.callback(sdmac->desc.callback_param); 651 } 652 653 static void sdma_tasklet(unsigned long data) 654 { 655 struct sdma_channel *sdmac = (struct sdma_channel *) data; 656 657 if (sdmac->flags & IMX_DMA_SG_LOOP) 658 sdma_handle_channel_loop(sdmac); 659 else 660 mxc_sdma_handle_channel_normal(sdmac); 661 } 662 663 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 664 { 665 struct sdma_engine *sdma = dev_id; 666 unsigned long stat; 667 668 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 669 /* not interested in channel 0 interrupts */ 670 stat &= ~1; 671 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 672 673 while (stat) { 674 int channel = fls(stat) - 1; 675 struct sdma_channel *sdmac = &sdma->channel[channel]; 676 677 if (sdmac->flags & IMX_DMA_SG_LOOP) 678 sdma_update_channel_loop(sdmac); 679 680 tasklet_schedule(&sdmac->tasklet); 681 682 __clear_bit(channel, &stat); 683 } 684 685 return IRQ_HANDLED; 686 } 687 688 /* 689 * sets the pc of SDMA script according to the peripheral type 690 */ 691 static void sdma_get_pc(struct sdma_channel *sdmac, 692 enum sdma_peripheral_type peripheral_type) 693 { 694 struct sdma_engine *sdma = sdmac->sdma; 695 int per_2_emi = 0, emi_2_per = 0; 696 /* 697 * These are needed once we start to support transfers between 698 * two peripherals or memory-to-memory transfers 699 */ 700 int per_2_per = 0, emi_2_emi = 0; 701 702 sdmac->pc_from_device = 0; 703 sdmac->pc_to_device = 0; 704 705 switch (peripheral_type) { 706 case IMX_DMATYPE_MEMORY: 707 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 708 break; 709 case IMX_DMATYPE_DSP: 710 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 711 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 712 break; 713 case IMX_DMATYPE_FIRI: 714 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 715 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 716 break; 717 case IMX_DMATYPE_UART: 718 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 719 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 720 break; 721 case IMX_DMATYPE_UART_SP: 722 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 723 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 724 break; 725 case IMX_DMATYPE_ATA: 726 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 727 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 728 break; 729 case IMX_DMATYPE_CSPI: 730 case IMX_DMATYPE_EXT: 731 case IMX_DMATYPE_SSI: 732 case IMX_DMATYPE_SAI: 733 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 734 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 735 break; 736 case IMX_DMATYPE_SSI_DUAL: 737 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 738 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 739 break; 740 case IMX_DMATYPE_SSI_SP: 741 case IMX_DMATYPE_MMC: 742 case IMX_DMATYPE_SDHC: 743 case IMX_DMATYPE_CSPI_SP: 744 case IMX_DMATYPE_ESAI: 745 case IMX_DMATYPE_MSHC_SP: 746 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 747 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 748 break; 749 case IMX_DMATYPE_ASRC: 750 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 751 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 752 per_2_per = sdma->script_addrs->per_2_per_addr; 753 break; 754 case IMX_DMATYPE_ASRC_SP: 755 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 756 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 757 per_2_per = sdma->script_addrs->per_2_per_addr; 758 break; 759 case IMX_DMATYPE_MSHC: 760 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 761 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 762 break; 763 case IMX_DMATYPE_CCM: 764 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 765 break; 766 case IMX_DMATYPE_SPDIF: 767 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 768 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 769 break; 770 case IMX_DMATYPE_IPU_MEMORY: 771 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 772 break; 773 default: 774 break; 775 } 776 777 sdmac->pc_from_device = per_2_emi; 778 sdmac->pc_to_device = emi_2_per; 779 } 780 781 static int sdma_load_context(struct sdma_channel *sdmac) 782 { 783 struct sdma_engine *sdma = sdmac->sdma; 784 int channel = sdmac->channel; 785 int load_address; 786 struct sdma_context_data *context = sdma->context; 787 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 788 int ret; 789 unsigned long flags; 790 791 if (sdmac->direction == DMA_DEV_TO_MEM) { 792 load_address = sdmac->pc_from_device; 793 } else { 794 load_address = sdmac->pc_to_device; 795 } 796 797 if (load_address < 0) 798 return load_address; 799 800 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 801 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 802 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 803 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 804 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 805 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 806 807 spin_lock_irqsave(&sdma->channel_0_lock, flags); 808 809 memset(context, 0, sizeof(*context)); 810 context->channel_state.pc = load_address; 811 812 /* Send by context the event mask,base address for peripheral 813 * and watermark level 814 */ 815 context->gReg[0] = sdmac->event_mask[1]; 816 context->gReg[1] = sdmac->event_mask[0]; 817 context->gReg[2] = sdmac->per_addr; 818 context->gReg[6] = sdmac->shp_addr; 819 context->gReg[7] = sdmac->watermark_level; 820 821 bd0->mode.command = C0_SETDM; 822 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 823 bd0->mode.count = sizeof(*context) / 4; 824 bd0->buffer_addr = sdma->context_phys; 825 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 826 ret = sdma_run_channel0(sdma); 827 828 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 829 830 return ret; 831 } 832 833 static void sdma_disable_channel(struct sdma_channel *sdmac) 834 { 835 struct sdma_engine *sdma = sdmac->sdma; 836 int channel = sdmac->channel; 837 838 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 839 sdmac->status = DMA_ERROR; 840 } 841 842 static int sdma_config_channel(struct sdma_channel *sdmac) 843 { 844 int ret; 845 846 sdma_disable_channel(sdmac); 847 848 sdmac->event_mask[0] = 0; 849 sdmac->event_mask[1] = 0; 850 sdmac->shp_addr = 0; 851 sdmac->per_addr = 0; 852 853 if (sdmac->event_id0) { 854 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 855 return -EINVAL; 856 sdma_event_enable(sdmac, sdmac->event_id0); 857 } 858 859 switch (sdmac->peripheral_type) { 860 case IMX_DMATYPE_DSP: 861 sdma_config_ownership(sdmac, false, true, true); 862 break; 863 case IMX_DMATYPE_MEMORY: 864 sdma_config_ownership(sdmac, false, true, false); 865 break; 866 default: 867 sdma_config_ownership(sdmac, true, true, false); 868 break; 869 } 870 871 sdma_get_pc(sdmac, sdmac->peripheral_type); 872 873 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 874 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 875 /* Handle multiple event channels differently */ 876 if (sdmac->event_id1) { 877 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); 878 if (sdmac->event_id1 > 31) 879 __set_bit(31, &sdmac->watermark_level); 880 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); 881 if (sdmac->event_id0 > 31) 882 __set_bit(30, &sdmac->watermark_level); 883 } else { 884 __set_bit(sdmac->event_id0, sdmac->event_mask); 885 } 886 /* Watermark Level */ 887 sdmac->watermark_level |= sdmac->watermark_level; 888 /* Address */ 889 sdmac->shp_addr = sdmac->per_address; 890 } else { 891 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 892 } 893 894 ret = sdma_load_context(sdmac); 895 896 return ret; 897 } 898 899 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 900 unsigned int priority) 901 { 902 struct sdma_engine *sdma = sdmac->sdma; 903 int channel = sdmac->channel; 904 905 if (priority < MXC_SDMA_MIN_PRIORITY 906 || priority > MXC_SDMA_MAX_PRIORITY) { 907 return -EINVAL; 908 } 909 910 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 911 912 return 0; 913 } 914 915 static int sdma_request_channel(struct sdma_channel *sdmac) 916 { 917 struct sdma_engine *sdma = sdmac->sdma; 918 int channel = sdmac->channel; 919 int ret = -EBUSY; 920 921 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, 922 GFP_KERNEL); 923 if (!sdmac->bd) { 924 ret = -ENOMEM; 925 goto out; 926 } 927 928 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; 929 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 930 931 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); 932 return 0; 933 out: 934 935 return ret; 936 } 937 938 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 939 { 940 return container_of(chan, struct sdma_channel, chan); 941 } 942 943 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) 944 { 945 unsigned long flags; 946 struct sdma_channel *sdmac = to_sdma_chan(tx->chan); 947 dma_cookie_t cookie; 948 949 spin_lock_irqsave(&sdmac->lock, flags); 950 951 cookie = dma_cookie_assign(tx); 952 953 spin_unlock_irqrestore(&sdmac->lock, flags); 954 955 return cookie; 956 } 957 958 static int sdma_alloc_chan_resources(struct dma_chan *chan) 959 { 960 struct sdma_channel *sdmac = to_sdma_chan(chan); 961 struct imx_dma_data *data = chan->private; 962 int prio, ret; 963 964 if (!data) 965 return -EINVAL; 966 967 switch (data->priority) { 968 case DMA_PRIO_HIGH: 969 prio = 3; 970 break; 971 case DMA_PRIO_MEDIUM: 972 prio = 2; 973 break; 974 case DMA_PRIO_LOW: 975 default: 976 prio = 1; 977 break; 978 } 979 980 sdmac->peripheral_type = data->peripheral_type; 981 sdmac->event_id0 = data->dma_request; 982 983 clk_enable(sdmac->sdma->clk_ipg); 984 clk_enable(sdmac->sdma->clk_ahb); 985 986 ret = sdma_request_channel(sdmac); 987 if (ret) 988 return ret; 989 990 ret = sdma_set_channel_priority(sdmac, prio); 991 if (ret) 992 return ret; 993 994 dma_async_tx_descriptor_init(&sdmac->desc, chan); 995 sdmac->desc.tx_submit = sdma_tx_submit; 996 /* txd.flags will be overwritten in prep funcs */ 997 sdmac->desc.flags = DMA_CTRL_ACK; 998 999 return 0; 1000 } 1001 1002 static void sdma_free_chan_resources(struct dma_chan *chan) 1003 { 1004 struct sdma_channel *sdmac = to_sdma_chan(chan); 1005 struct sdma_engine *sdma = sdmac->sdma; 1006 1007 sdma_disable_channel(sdmac); 1008 1009 if (sdmac->event_id0) 1010 sdma_event_disable(sdmac, sdmac->event_id0); 1011 if (sdmac->event_id1) 1012 sdma_event_disable(sdmac, sdmac->event_id1); 1013 1014 sdmac->event_id0 = 0; 1015 sdmac->event_id1 = 0; 1016 1017 sdma_set_channel_priority(sdmac, 0); 1018 1019 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); 1020 1021 clk_disable(sdma->clk_ipg); 1022 clk_disable(sdma->clk_ahb); 1023 } 1024 1025 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1026 struct dma_chan *chan, struct scatterlist *sgl, 1027 unsigned int sg_len, enum dma_transfer_direction direction, 1028 unsigned long flags, void *context) 1029 { 1030 struct sdma_channel *sdmac = to_sdma_chan(chan); 1031 struct sdma_engine *sdma = sdmac->sdma; 1032 int ret, i, count; 1033 int channel = sdmac->channel; 1034 struct scatterlist *sg; 1035 1036 if (sdmac->status == DMA_IN_PROGRESS) 1037 return NULL; 1038 sdmac->status = DMA_IN_PROGRESS; 1039 1040 sdmac->flags = 0; 1041 1042 sdmac->buf_tail = 0; 1043 1044 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1045 sg_len, channel); 1046 1047 sdmac->direction = direction; 1048 ret = sdma_load_context(sdmac); 1049 if (ret) 1050 goto err_out; 1051 1052 if (sg_len > NUM_BD) { 1053 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1054 channel, sg_len, NUM_BD); 1055 ret = -EINVAL; 1056 goto err_out; 1057 } 1058 1059 sdmac->chn_count = 0; 1060 for_each_sg(sgl, sg, sg_len, i) { 1061 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1062 int param; 1063 1064 bd->buffer_addr = sg->dma_address; 1065 1066 count = sg_dma_len(sg); 1067 1068 if (count > 0xffff) { 1069 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1070 channel, count, 0xffff); 1071 ret = -EINVAL; 1072 goto err_out; 1073 } 1074 1075 bd->mode.count = count; 1076 sdmac->chn_count += count; 1077 1078 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { 1079 ret = -EINVAL; 1080 goto err_out; 1081 } 1082 1083 switch (sdmac->word_size) { 1084 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1085 bd->mode.command = 0; 1086 if (count & 3 || sg->dma_address & 3) 1087 return NULL; 1088 break; 1089 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1090 bd->mode.command = 2; 1091 if (count & 1 || sg->dma_address & 1) 1092 return NULL; 1093 break; 1094 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1095 bd->mode.command = 1; 1096 break; 1097 default: 1098 return NULL; 1099 } 1100 1101 param = BD_DONE | BD_EXTD | BD_CONT; 1102 1103 if (i + 1 == sg_len) { 1104 param |= BD_INTR; 1105 param |= BD_LAST; 1106 param &= ~BD_CONT; 1107 } 1108 1109 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1110 i, count, (u64)sg->dma_address, 1111 param & BD_WRAP ? "wrap" : "", 1112 param & BD_INTR ? " intr" : ""); 1113 1114 bd->mode.status = param; 1115 } 1116 1117 sdmac->num_bd = sg_len; 1118 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1119 1120 return &sdmac->desc; 1121 err_out: 1122 sdmac->status = DMA_ERROR; 1123 return NULL; 1124 } 1125 1126 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1127 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1128 size_t period_len, enum dma_transfer_direction direction, 1129 unsigned long flags) 1130 { 1131 struct sdma_channel *sdmac = to_sdma_chan(chan); 1132 struct sdma_engine *sdma = sdmac->sdma; 1133 int num_periods = buf_len / period_len; 1134 int channel = sdmac->channel; 1135 int ret, i = 0, buf = 0; 1136 1137 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1138 1139 if (sdmac->status == DMA_IN_PROGRESS) 1140 return NULL; 1141 1142 sdmac->status = DMA_IN_PROGRESS; 1143 1144 sdmac->buf_tail = 0; 1145 sdmac->period_len = period_len; 1146 1147 sdmac->flags |= IMX_DMA_SG_LOOP; 1148 sdmac->direction = direction; 1149 ret = sdma_load_context(sdmac); 1150 if (ret) 1151 goto err_out; 1152 1153 if (num_periods > NUM_BD) { 1154 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1155 channel, num_periods, NUM_BD); 1156 goto err_out; 1157 } 1158 1159 if (period_len > 0xffff) { 1160 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", 1161 channel, period_len, 0xffff); 1162 goto err_out; 1163 } 1164 1165 while (buf < buf_len) { 1166 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1167 int param; 1168 1169 bd->buffer_addr = dma_addr; 1170 1171 bd->mode.count = period_len; 1172 1173 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1174 goto err_out; 1175 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1176 bd->mode.command = 0; 1177 else 1178 bd->mode.command = sdmac->word_size; 1179 1180 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1181 if (i + 1 == num_periods) 1182 param |= BD_WRAP; 1183 1184 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1185 i, period_len, (u64)dma_addr, 1186 param & BD_WRAP ? "wrap" : "", 1187 param & BD_INTR ? " intr" : ""); 1188 1189 bd->mode.status = param; 1190 1191 dma_addr += period_len; 1192 buf += period_len; 1193 1194 i++; 1195 } 1196 1197 sdmac->num_bd = num_periods; 1198 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1199 1200 return &sdmac->desc; 1201 err_out: 1202 sdmac->status = DMA_ERROR; 1203 return NULL; 1204 } 1205 1206 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1207 unsigned long arg) 1208 { 1209 struct sdma_channel *sdmac = to_sdma_chan(chan); 1210 struct dma_slave_config *dmaengine_cfg = (void *)arg; 1211 1212 switch (cmd) { 1213 case DMA_TERMINATE_ALL: 1214 sdma_disable_channel(sdmac); 1215 return 0; 1216 case DMA_SLAVE_CONFIG: 1217 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 1218 sdmac->per_address = dmaengine_cfg->src_addr; 1219 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1220 dmaengine_cfg->src_addr_width; 1221 sdmac->word_size = dmaengine_cfg->src_addr_width; 1222 } else { 1223 sdmac->per_address = dmaengine_cfg->dst_addr; 1224 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1225 dmaengine_cfg->dst_addr_width; 1226 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1227 } 1228 sdmac->direction = dmaengine_cfg->direction; 1229 return sdma_config_channel(sdmac); 1230 default: 1231 return -ENOSYS; 1232 } 1233 1234 return -EINVAL; 1235 } 1236 1237 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1238 dma_cookie_t cookie, 1239 struct dma_tx_state *txstate) 1240 { 1241 struct sdma_channel *sdmac = to_sdma_chan(chan); 1242 u32 residue; 1243 1244 if (sdmac->flags & IMX_DMA_SG_LOOP) 1245 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len; 1246 else 1247 residue = sdmac->chn_count - sdmac->chn_real_count; 1248 1249 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1250 residue); 1251 1252 return sdmac->status; 1253 } 1254 1255 static void sdma_issue_pending(struct dma_chan *chan) 1256 { 1257 struct sdma_channel *sdmac = to_sdma_chan(chan); 1258 struct sdma_engine *sdma = sdmac->sdma; 1259 1260 if (sdmac->status == DMA_IN_PROGRESS) 1261 sdma_enable_channel(sdma, sdmac->channel); 1262 } 1263 1264 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1265 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1266 1267 static void sdma_add_scripts(struct sdma_engine *sdma, 1268 const struct sdma_script_start_addrs *addr) 1269 { 1270 s32 *addr_arr = (u32 *)addr; 1271 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1272 int i; 1273 1274 /* use the default firmware in ROM if missing external firmware */ 1275 if (!sdma->script_number) 1276 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1277 1278 for (i = 0; i < sdma->script_number; i++) 1279 if (addr_arr[i] > 0) 1280 saddr_arr[i] = addr_arr[i]; 1281 } 1282 1283 static void sdma_load_firmware(const struct firmware *fw, void *context) 1284 { 1285 struct sdma_engine *sdma = context; 1286 const struct sdma_firmware_header *header; 1287 const struct sdma_script_start_addrs *addr; 1288 unsigned short *ram_code; 1289 1290 if (!fw) { 1291 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); 1292 /* In this case we just use the ROM firmware. */ 1293 return; 1294 } 1295 1296 if (fw->size < sizeof(*header)) 1297 goto err_firmware; 1298 1299 header = (struct sdma_firmware_header *)fw->data; 1300 1301 if (header->magic != SDMA_FIRMWARE_MAGIC) 1302 goto err_firmware; 1303 if (header->ram_code_start + header->ram_code_size > fw->size) 1304 goto err_firmware; 1305 switch (header->version_major) { 1306 case 1: 1307 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1308 break; 1309 case 2: 1310 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1311 break; 1312 default: 1313 dev_err(sdma->dev, "unknown firmware version\n"); 1314 goto err_firmware; 1315 } 1316 1317 addr = (void *)header + header->script_addrs_start; 1318 ram_code = (void *)header + header->ram_code_start; 1319 1320 clk_enable(sdma->clk_ipg); 1321 clk_enable(sdma->clk_ahb); 1322 /* download the RAM image for SDMA */ 1323 sdma_load_script(sdma, ram_code, 1324 header->ram_code_size, 1325 addr->ram_code_start_addr); 1326 clk_disable(sdma->clk_ipg); 1327 clk_disable(sdma->clk_ahb); 1328 1329 sdma_add_scripts(sdma, addr); 1330 1331 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1332 header->version_major, 1333 header->version_minor); 1334 1335 err_firmware: 1336 release_firmware(fw); 1337 } 1338 1339 static int sdma_get_firmware(struct sdma_engine *sdma, 1340 const char *fw_name) 1341 { 1342 int ret; 1343 1344 ret = request_firmware_nowait(THIS_MODULE, 1345 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1346 GFP_KERNEL, sdma, sdma_load_firmware); 1347 1348 return ret; 1349 } 1350 1351 static int sdma_init(struct sdma_engine *sdma) 1352 { 1353 int i, ret; 1354 dma_addr_t ccb_phys; 1355 1356 clk_enable(sdma->clk_ipg); 1357 clk_enable(sdma->clk_ahb); 1358 1359 /* Be sure SDMA has not started yet */ 1360 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1361 1362 sdma->channel_control = dma_alloc_coherent(NULL, 1363 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1364 sizeof(struct sdma_context_data), 1365 &ccb_phys, GFP_KERNEL); 1366 1367 if (!sdma->channel_control) { 1368 ret = -ENOMEM; 1369 goto err_dma_alloc; 1370 } 1371 1372 sdma->context = (void *)sdma->channel_control + 1373 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1374 sdma->context_phys = ccb_phys + 1375 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1376 1377 /* Zero-out the CCB structures array just allocated */ 1378 memset(sdma->channel_control, 0, 1379 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1380 1381 /* disable all channels */ 1382 for (i = 0; i < sdma->drvdata->num_events; i++) 1383 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1384 1385 /* All channels have priority 0 */ 1386 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1387 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1388 1389 ret = sdma_request_channel(&sdma->channel[0]); 1390 if (ret) 1391 goto err_dma_alloc; 1392 1393 sdma_config_ownership(&sdma->channel[0], false, true, false); 1394 1395 /* Set Command Channel (Channel Zero) */ 1396 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1397 1398 /* Set bits of CONFIG register but with static context switching */ 1399 /* FIXME: Check whether to set ACR bit depending on clock ratios */ 1400 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1401 1402 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1403 1404 /* Set bits of CONFIG register with given context switching mode */ 1405 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 1406 1407 /* Initializes channel's priorities */ 1408 sdma_set_channel_priority(&sdma->channel[0], 7); 1409 1410 clk_disable(sdma->clk_ipg); 1411 clk_disable(sdma->clk_ahb); 1412 1413 return 0; 1414 1415 err_dma_alloc: 1416 clk_disable(sdma->clk_ipg); 1417 clk_disable(sdma->clk_ahb); 1418 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1419 return ret; 1420 } 1421 1422 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1423 { 1424 struct sdma_channel *sdmac = to_sdma_chan(chan); 1425 struct imx_dma_data *data = fn_param; 1426 1427 if (!imx_dma_is_general_purpose(chan)) 1428 return false; 1429 1430 sdmac->data = *data; 1431 chan->private = &sdmac->data; 1432 1433 return true; 1434 } 1435 1436 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1437 struct of_dma *ofdma) 1438 { 1439 struct sdma_engine *sdma = ofdma->of_dma_data; 1440 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1441 struct imx_dma_data data; 1442 1443 if (dma_spec->args_count != 3) 1444 return NULL; 1445 1446 data.dma_request = dma_spec->args[0]; 1447 data.peripheral_type = dma_spec->args[1]; 1448 data.priority = dma_spec->args[2]; 1449 1450 return dma_request_channel(mask, sdma_filter_fn, &data); 1451 } 1452 1453 static int sdma_probe(struct platform_device *pdev) 1454 { 1455 const struct of_device_id *of_id = 1456 of_match_device(sdma_dt_ids, &pdev->dev); 1457 struct device_node *np = pdev->dev.of_node; 1458 const char *fw_name; 1459 int ret; 1460 int irq; 1461 struct resource *iores; 1462 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1463 int i; 1464 struct sdma_engine *sdma; 1465 s32 *saddr_arr; 1466 const struct sdma_driver_data *drvdata = NULL; 1467 1468 if (of_id) 1469 drvdata = of_id->data; 1470 else if (pdev->id_entry) 1471 drvdata = (void *)pdev->id_entry->driver_data; 1472 1473 if (!drvdata) { 1474 dev_err(&pdev->dev, "unable to find driver data\n"); 1475 return -EINVAL; 1476 } 1477 1478 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1479 if (ret) 1480 return ret; 1481 1482 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); 1483 if (!sdma) 1484 return -ENOMEM; 1485 1486 spin_lock_init(&sdma->channel_0_lock); 1487 1488 sdma->dev = &pdev->dev; 1489 sdma->drvdata = drvdata; 1490 1491 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1492 irq = platform_get_irq(pdev, 0); 1493 if (!iores || irq < 0) { 1494 ret = -EINVAL; 1495 goto err_irq; 1496 } 1497 1498 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { 1499 ret = -EBUSY; 1500 goto err_request_region; 1501 } 1502 1503 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1504 if (IS_ERR(sdma->clk_ipg)) { 1505 ret = PTR_ERR(sdma->clk_ipg); 1506 goto err_clk; 1507 } 1508 1509 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1510 if (IS_ERR(sdma->clk_ahb)) { 1511 ret = PTR_ERR(sdma->clk_ahb); 1512 goto err_clk; 1513 } 1514 1515 clk_prepare(sdma->clk_ipg); 1516 clk_prepare(sdma->clk_ahb); 1517 1518 sdma->regs = ioremap(iores->start, resource_size(iores)); 1519 if (!sdma->regs) { 1520 ret = -ENOMEM; 1521 goto err_ioremap; 1522 } 1523 1524 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); 1525 if (ret) 1526 goto err_request_irq; 1527 1528 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 1529 if (!sdma->script_addrs) { 1530 ret = -ENOMEM; 1531 goto err_alloc; 1532 } 1533 1534 /* initially no scripts available */ 1535 saddr_arr = (s32 *)sdma->script_addrs; 1536 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 1537 saddr_arr[i] = -EINVAL; 1538 1539 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1540 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1541 1542 INIT_LIST_HEAD(&sdma->dma_device.channels); 1543 /* Initialize channel parameters */ 1544 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1545 struct sdma_channel *sdmac = &sdma->channel[i]; 1546 1547 sdmac->sdma = sdma; 1548 spin_lock_init(&sdmac->lock); 1549 1550 sdmac->chan.device = &sdma->dma_device; 1551 dma_cookie_init(&sdmac->chan); 1552 sdmac->channel = i; 1553 1554 tasklet_init(&sdmac->tasklet, sdma_tasklet, 1555 (unsigned long) sdmac); 1556 /* 1557 * Add the channel to the DMAC list. Do not add channel 0 though 1558 * because we need it internally in the SDMA driver. This also means 1559 * that channel 0 in dmaengine counting matches sdma channel 1. 1560 */ 1561 if (i) 1562 list_add_tail(&sdmac->chan.device_node, 1563 &sdma->dma_device.channels); 1564 } 1565 1566 ret = sdma_init(sdma); 1567 if (ret) 1568 goto err_init; 1569 1570 if (sdma->drvdata->script_addrs) 1571 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 1572 if (pdata && pdata->script_addrs) 1573 sdma_add_scripts(sdma, pdata->script_addrs); 1574 1575 if (pdata) { 1576 ret = sdma_get_firmware(sdma, pdata->fw_name); 1577 if (ret) 1578 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 1579 } else { 1580 /* 1581 * Because that device tree does not encode ROM script address, 1582 * the RAM script in firmware is mandatory for device tree 1583 * probe, otherwise it fails. 1584 */ 1585 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 1586 &fw_name); 1587 if (ret) 1588 dev_warn(&pdev->dev, "failed to get firmware name\n"); 1589 else { 1590 ret = sdma_get_firmware(sdma, fw_name); 1591 if (ret) 1592 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 1593 } 1594 } 1595 1596 sdma->dma_device.dev = &pdev->dev; 1597 1598 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 1599 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 1600 sdma->dma_device.device_tx_status = sdma_tx_status; 1601 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 1602 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1603 sdma->dma_device.device_control = sdma_control; 1604 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1605 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1606 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1607 1608 platform_set_drvdata(pdev, sdma); 1609 1610 ret = dma_async_device_register(&sdma->dma_device); 1611 if (ret) { 1612 dev_err(&pdev->dev, "unable to register\n"); 1613 goto err_init; 1614 } 1615 1616 if (np) { 1617 ret = of_dma_controller_register(np, sdma_xlate, sdma); 1618 if (ret) { 1619 dev_err(&pdev->dev, "failed to register controller\n"); 1620 goto err_register; 1621 } 1622 } 1623 1624 dev_info(sdma->dev, "initialized\n"); 1625 1626 return 0; 1627 1628 err_register: 1629 dma_async_device_unregister(&sdma->dma_device); 1630 err_init: 1631 kfree(sdma->script_addrs); 1632 err_alloc: 1633 free_irq(irq, sdma); 1634 err_request_irq: 1635 iounmap(sdma->regs); 1636 err_ioremap: 1637 err_clk: 1638 release_mem_region(iores->start, resource_size(iores)); 1639 err_request_region: 1640 err_irq: 1641 kfree(sdma); 1642 return ret; 1643 } 1644 1645 static int sdma_remove(struct platform_device *pdev) 1646 { 1647 struct sdma_engine *sdma = platform_get_drvdata(pdev); 1648 struct resource *iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1649 int irq = platform_get_irq(pdev, 0); 1650 int i; 1651 1652 dma_async_device_unregister(&sdma->dma_device); 1653 kfree(sdma->script_addrs); 1654 free_irq(irq, sdma); 1655 iounmap(sdma->regs); 1656 release_mem_region(iores->start, resource_size(iores)); 1657 /* Kill the tasklet */ 1658 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1659 struct sdma_channel *sdmac = &sdma->channel[i]; 1660 1661 tasklet_kill(&sdmac->tasklet); 1662 } 1663 kfree(sdma); 1664 1665 platform_set_drvdata(pdev, NULL); 1666 dev_info(&pdev->dev, "Removed...\n"); 1667 return 0; 1668 } 1669 1670 static struct platform_driver sdma_driver = { 1671 .driver = { 1672 .name = "imx-sdma", 1673 .of_match_table = sdma_dt_ids, 1674 }, 1675 .id_table = sdma_devtypes, 1676 .remove = sdma_remove, 1677 .probe = sdma_probe, 1678 }; 1679 1680 module_platform_driver(sdma_driver); 1681 1682 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1683 MODULE_DESCRIPTION("i.MX SDMA driver"); 1684 MODULE_LICENSE("GPL"); 1685