1 /* 2 * drivers/dma/imx-sdma.c 3 * 4 * This file contains a driver for the Freescale Smart DMA engine 5 * 6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 7 * 8 * Based on code from Freescale: 9 * 10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 11 * 12 * The code contained herein is licensed under the GNU General Public 13 * License. You may obtain a copy of the GNU General Public License 14 * Version 2 or later at the following locations: 15 * 16 * http://www.opensource.org/licenses/gpl-license.html 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/mm.h> 25 #include <linux/interrupt.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/sched.h> 29 #include <linux/semaphore.h> 30 #include <linux/spinlock.h> 31 #include <linux/device.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/firmware.h> 34 #include <linux/slab.h> 35 #include <linux/platform_device.h> 36 #include <linux/dmaengine.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_dma.h> 40 41 #include <asm/irq.h> 42 #include <linux/platform_data/dma-imx-sdma.h> 43 #include <linux/platform_data/dma-imx.h> 44 45 #include "dmaengine.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * Mode/Count of data node descriptors - IPCv2 128 */ 129 struct sdma_mode_count { 130 u32 count : 16; /* size of the buffer pointed by this BD */ 131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 132 u32 command : 8; /* command mostlky used for channel 0 */ 133 }; 134 135 /* 136 * Buffer descriptor 137 */ 138 struct sdma_buffer_descriptor { 139 struct sdma_mode_count mode; 140 u32 buffer_addr; /* address of the buffer described */ 141 u32 ext_buffer_addr; /* extended buffer address */ 142 } __attribute__ ((packed)); 143 144 /** 145 * struct sdma_channel_control - Channel control Block 146 * 147 * @current_bd_ptr current buffer descriptor processed 148 * @base_bd_ptr first element of buffer descriptor array 149 * @unused padding. The SDMA engine expects an array of 128 byte 150 * control blocks 151 */ 152 struct sdma_channel_control { 153 u32 current_bd_ptr; 154 u32 base_bd_ptr; 155 u32 unused[2]; 156 } __attribute__ ((packed)); 157 158 /** 159 * struct sdma_state_registers - SDMA context for a channel 160 * 161 * @pc: program counter 162 * @t: test bit: status of arithmetic & test instruction 163 * @rpc: return program counter 164 * @sf: source fault while loading data 165 * @spc: loop start program counter 166 * @df: destination fault while storing data 167 * @epc: loop end program counter 168 * @lm: loop mode 169 */ 170 struct sdma_state_registers { 171 u32 pc :14; 172 u32 unused1: 1; 173 u32 t : 1; 174 u32 rpc :14; 175 u32 unused0: 1; 176 u32 sf : 1; 177 u32 spc :14; 178 u32 unused2: 1; 179 u32 df : 1; 180 u32 epc :14; 181 u32 lm : 2; 182 } __attribute__ ((packed)); 183 184 /** 185 * struct sdma_context_data - sdma context specific to a channel 186 * 187 * @channel_state: channel state bits 188 * @gReg: general registers 189 * @mda: burst dma destination address register 190 * @msa: burst dma source address register 191 * @ms: burst dma status register 192 * @md: burst dma data register 193 * @pda: peripheral dma destination address register 194 * @psa: peripheral dma source address register 195 * @ps: peripheral dma status register 196 * @pd: peripheral dma data register 197 * @ca: CRC polynomial register 198 * @cs: CRC accumulator register 199 * @dda: dedicated core destination address register 200 * @dsa: dedicated core source address register 201 * @ds: dedicated core status register 202 * @dd: dedicated core data register 203 */ 204 struct sdma_context_data { 205 struct sdma_state_registers channel_state; 206 u32 gReg[8]; 207 u32 mda; 208 u32 msa; 209 u32 ms; 210 u32 md; 211 u32 pda; 212 u32 psa; 213 u32 ps; 214 u32 pd; 215 u32 ca; 216 u32 cs; 217 u32 dda; 218 u32 dsa; 219 u32 ds; 220 u32 dd; 221 u32 scratch0; 222 u32 scratch1; 223 u32 scratch2; 224 u32 scratch3; 225 u32 scratch4; 226 u32 scratch5; 227 u32 scratch6; 228 u32 scratch7; 229 } __attribute__ ((packed)); 230 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 232 233 struct sdma_engine; 234 235 /** 236 * struct sdma_channel - housekeeping for a SDMA channel 237 * 238 * @sdma pointer to the SDMA engine for this channel 239 * @channel the channel number, matches dmaengine chan_id + 1 240 * @direction transfer type. Needed for setting SDMA script 241 * @peripheral_type Peripheral type. Needed for setting SDMA script 242 * @event_id0 aka dma request line 243 * @event_id1 for channels that use 2 events 244 * @word_size peripheral access size 245 * @buf_tail ID of the buffer that was processed 246 * @num_bd max NUM_BD. number of descriptors currently handling 247 */ 248 struct sdma_channel { 249 struct sdma_engine *sdma; 250 unsigned int channel; 251 enum dma_transfer_direction direction; 252 enum sdma_peripheral_type peripheral_type; 253 unsigned int event_id0; 254 unsigned int event_id1; 255 enum dma_slave_buswidth word_size; 256 unsigned int buf_tail; 257 unsigned int num_bd; 258 struct sdma_buffer_descriptor *bd; 259 dma_addr_t bd_phys; 260 unsigned int pc_from_device, pc_to_device; 261 unsigned long flags; 262 dma_addr_t per_address; 263 unsigned long event_mask[2]; 264 unsigned long watermark_level; 265 u32 shp_addr, per_addr; 266 struct dma_chan chan; 267 spinlock_t lock; 268 struct dma_async_tx_descriptor desc; 269 enum dma_status status; 270 unsigned int chn_count; 271 unsigned int chn_real_count; 272 struct tasklet_struct tasklet; 273 }; 274 275 #define IMX_DMA_SG_LOOP BIT(0) 276 277 #define MAX_DMA_CHANNELS 32 278 #define MXC_SDMA_DEFAULT_PRIORITY 1 279 #define MXC_SDMA_MIN_PRIORITY 1 280 #define MXC_SDMA_MAX_PRIORITY 7 281 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453 283 284 /** 285 * struct sdma_firmware_header - Layout of the firmware image 286 * 287 * @magic "SDMA" 288 * @version_major increased whenever layout of struct sdma_script_start_addrs 289 * changes. 290 * @version_minor firmware minor version (for binary compatible changes) 291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image 292 * @num_script_addrs Number of script addresses in this image 293 * @ram_code_start offset of SDMA ram image in this firmware image 294 * @ram_code_size size of SDMA ram image 295 * @script_addrs Stores the start address of the SDMA scripts 296 * (in SDMA memory space) 297 */ 298 struct sdma_firmware_header { 299 u32 magic; 300 u32 version_major; 301 u32 version_minor; 302 u32 script_addrs_start; 303 u32 num_script_addrs; 304 u32 ram_code_start; 305 u32 ram_code_size; 306 }; 307 308 struct sdma_driver_data { 309 int chnenbl0; 310 int num_events; 311 struct sdma_script_start_addrs *script_addrs; 312 }; 313 314 struct sdma_engine { 315 struct device *dev; 316 struct device_dma_parameters dma_parms; 317 struct sdma_channel channel[MAX_DMA_CHANNELS]; 318 struct sdma_channel_control *channel_control; 319 void __iomem *regs; 320 struct sdma_context_data *context; 321 dma_addr_t context_phys; 322 struct dma_device dma_device; 323 struct clk *clk_ipg; 324 struct clk *clk_ahb; 325 spinlock_t channel_0_lock; 326 u32 script_number; 327 struct sdma_script_start_addrs *script_addrs; 328 const struct sdma_driver_data *drvdata; 329 }; 330 331 static struct sdma_driver_data sdma_imx31 = { 332 .chnenbl0 = SDMA_CHNENBL0_IMX31, 333 .num_events = 32, 334 }; 335 336 static struct sdma_script_start_addrs sdma_script_imx25 = { 337 .ap_2_ap_addr = 729, 338 .uart_2_mcu_addr = 904, 339 .per_2_app_addr = 1255, 340 .mcu_2_app_addr = 834, 341 .uartsh_2_mcu_addr = 1120, 342 .per_2_shp_addr = 1329, 343 .mcu_2_shp_addr = 1048, 344 .ata_2_mcu_addr = 1560, 345 .mcu_2_ata_addr = 1479, 346 .app_2_per_addr = 1189, 347 .app_2_mcu_addr = 770, 348 .shp_2_per_addr = 1407, 349 .shp_2_mcu_addr = 979, 350 }; 351 352 static struct sdma_driver_data sdma_imx25 = { 353 .chnenbl0 = SDMA_CHNENBL0_IMX35, 354 .num_events = 48, 355 .script_addrs = &sdma_script_imx25, 356 }; 357 358 static struct sdma_driver_data sdma_imx35 = { 359 .chnenbl0 = SDMA_CHNENBL0_IMX35, 360 .num_events = 48, 361 }; 362 363 static struct sdma_script_start_addrs sdma_script_imx51 = { 364 .ap_2_ap_addr = 642, 365 .uart_2_mcu_addr = 817, 366 .mcu_2_app_addr = 747, 367 .mcu_2_shp_addr = 961, 368 .ata_2_mcu_addr = 1473, 369 .mcu_2_ata_addr = 1392, 370 .app_2_per_addr = 1033, 371 .app_2_mcu_addr = 683, 372 .shp_2_per_addr = 1251, 373 .shp_2_mcu_addr = 892, 374 }; 375 376 static struct sdma_driver_data sdma_imx51 = { 377 .chnenbl0 = SDMA_CHNENBL0_IMX35, 378 .num_events = 48, 379 .script_addrs = &sdma_script_imx51, 380 }; 381 382 static struct sdma_script_start_addrs sdma_script_imx53 = { 383 .ap_2_ap_addr = 642, 384 .app_2_mcu_addr = 683, 385 .mcu_2_app_addr = 747, 386 .uart_2_mcu_addr = 817, 387 .shp_2_mcu_addr = 891, 388 .mcu_2_shp_addr = 960, 389 .uartsh_2_mcu_addr = 1032, 390 .spdif_2_mcu_addr = 1100, 391 .mcu_2_spdif_addr = 1134, 392 .firi_2_mcu_addr = 1193, 393 .mcu_2_firi_addr = 1290, 394 }; 395 396 static struct sdma_driver_data sdma_imx53 = { 397 .chnenbl0 = SDMA_CHNENBL0_IMX35, 398 .num_events = 48, 399 .script_addrs = &sdma_script_imx53, 400 }; 401 402 static struct sdma_script_start_addrs sdma_script_imx6q = { 403 .ap_2_ap_addr = 642, 404 .uart_2_mcu_addr = 817, 405 .mcu_2_app_addr = 747, 406 .per_2_per_addr = 6331, 407 .uartsh_2_mcu_addr = 1032, 408 .mcu_2_shp_addr = 960, 409 .app_2_mcu_addr = 683, 410 .shp_2_mcu_addr = 891, 411 .spdif_2_mcu_addr = 1100, 412 .mcu_2_spdif_addr = 1134, 413 }; 414 415 static struct sdma_driver_data sdma_imx6q = { 416 .chnenbl0 = SDMA_CHNENBL0_IMX35, 417 .num_events = 48, 418 .script_addrs = &sdma_script_imx6q, 419 }; 420 421 static struct platform_device_id sdma_devtypes[] = { 422 { 423 .name = "imx25-sdma", 424 .driver_data = (unsigned long)&sdma_imx25, 425 }, { 426 .name = "imx31-sdma", 427 .driver_data = (unsigned long)&sdma_imx31, 428 }, { 429 .name = "imx35-sdma", 430 .driver_data = (unsigned long)&sdma_imx35, 431 }, { 432 .name = "imx51-sdma", 433 .driver_data = (unsigned long)&sdma_imx51, 434 }, { 435 .name = "imx53-sdma", 436 .driver_data = (unsigned long)&sdma_imx53, 437 }, { 438 .name = "imx6q-sdma", 439 .driver_data = (unsigned long)&sdma_imx6q, 440 }, { 441 /* sentinel */ 442 } 443 }; 444 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 445 446 static const struct of_device_id sdma_dt_ids[] = { 447 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 448 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 449 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 450 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 451 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 452 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 453 { /* sentinel */ } 454 }; 455 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 456 457 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 458 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 459 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 460 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 461 462 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 463 { 464 u32 chnenbl0 = sdma->drvdata->chnenbl0; 465 return chnenbl0 + event * 4; 466 } 467 468 static int sdma_config_ownership(struct sdma_channel *sdmac, 469 bool event_override, bool mcu_override, bool dsp_override) 470 { 471 struct sdma_engine *sdma = sdmac->sdma; 472 int channel = sdmac->channel; 473 unsigned long evt, mcu, dsp; 474 475 if (event_override && mcu_override && dsp_override) 476 return -EINVAL; 477 478 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 479 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 480 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 481 482 if (dsp_override) 483 __clear_bit(channel, &dsp); 484 else 485 __set_bit(channel, &dsp); 486 487 if (event_override) 488 __clear_bit(channel, &evt); 489 else 490 __set_bit(channel, &evt); 491 492 if (mcu_override) 493 __clear_bit(channel, &mcu); 494 else 495 __set_bit(channel, &mcu); 496 497 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 498 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 499 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 500 501 return 0; 502 } 503 504 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 505 { 506 writel(BIT(channel), sdma->regs + SDMA_H_START); 507 } 508 509 /* 510 * sdma_run_channel0 - run a channel and wait till it's done 511 */ 512 static int sdma_run_channel0(struct sdma_engine *sdma) 513 { 514 int ret; 515 unsigned long timeout = 500; 516 517 sdma_enable_channel(sdma, 0); 518 519 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { 520 if (timeout-- <= 0) 521 break; 522 udelay(1); 523 } 524 525 if (ret) { 526 /* Clear the interrupt status */ 527 writel_relaxed(ret, sdma->regs + SDMA_H_INTR); 528 } else { 529 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 530 } 531 532 return ret ? 0 : -ETIMEDOUT; 533 } 534 535 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 536 u32 address) 537 { 538 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 539 void *buf_virt; 540 dma_addr_t buf_phys; 541 int ret; 542 unsigned long flags; 543 544 buf_virt = dma_alloc_coherent(NULL, 545 size, 546 &buf_phys, GFP_KERNEL); 547 if (!buf_virt) { 548 return -ENOMEM; 549 } 550 551 spin_lock_irqsave(&sdma->channel_0_lock, flags); 552 553 bd0->mode.command = C0_SETPM; 554 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 555 bd0->mode.count = size / 2; 556 bd0->buffer_addr = buf_phys; 557 bd0->ext_buffer_addr = address; 558 559 memcpy(buf_virt, buf, size); 560 561 ret = sdma_run_channel0(sdma); 562 563 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 564 565 dma_free_coherent(NULL, size, buf_virt, buf_phys); 566 567 return ret; 568 } 569 570 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 571 { 572 struct sdma_engine *sdma = sdmac->sdma; 573 int channel = sdmac->channel; 574 unsigned long val; 575 u32 chnenbl = chnenbl_ofs(sdma, event); 576 577 val = readl_relaxed(sdma->regs + chnenbl); 578 __set_bit(channel, &val); 579 writel_relaxed(val, sdma->regs + chnenbl); 580 } 581 582 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 583 { 584 struct sdma_engine *sdma = sdmac->sdma; 585 int channel = sdmac->channel; 586 u32 chnenbl = chnenbl_ofs(sdma, event); 587 unsigned long val; 588 589 val = readl_relaxed(sdma->regs + chnenbl); 590 __clear_bit(channel, &val); 591 writel_relaxed(val, sdma->regs + chnenbl); 592 } 593 594 static void sdma_handle_channel_loop(struct sdma_channel *sdmac) 595 { 596 struct sdma_buffer_descriptor *bd; 597 598 /* 599 * loop mode. Iterate over descriptors, re-setup them and 600 * call callback function. 601 */ 602 while (1) { 603 bd = &sdmac->bd[sdmac->buf_tail]; 604 605 if (bd->mode.status & BD_DONE) 606 break; 607 608 if (bd->mode.status & BD_RROR) 609 sdmac->status = DMA_ERROR; 610 else 611 sdmac->status = DMA_IN_PROGRESS; 612 613 bd->mode.status |= BD_DONE; 614 sdmac->buf_tail++; 615 sdmac->buf_tail %= sdmac->num_bd; 616 617 if (sdmac->desc.callback) 618 sdmac->desc.callback(sdmac->desc.callback_param); 619 } 620 } 621 622 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) 623 { 624 struct sdma_buffer_descriptor *bd; 625 int i, error = 0; 626 627 sdmac->chn_real_count = 0; 628 /* 629 * non loop mode. Iterate over all descriptors, collect 630 * errors and call callback function 631 */ 632 for (i = 0; i < sdmac->num_bd; i++) { 633 bd = &sdmac->bd[i]; 634 635 if (bd->mode.status & (BD_DONE | BD_RROR)) 636 error = -EIO; 637 sdmac->chn_real_count += bd->mode.count; 638 } 639 640 if (error) 641 sdmac->status = DMA_ERROR; 642 else 643 sdmac->status = DMA_COMPLETE; 644 645 dma_cookie_complete(&sdmac->desc); 646 if (sdmac->desc.callback) 647 sdmac->desc.callback(sdmac->desc.callback_param); 648 } 649 650 static void sdma_tasklet(unsigned long data) 651 { 652 struct sdma_channel *sdmac = (struct sdma_channel *) data; 653 654 if (sdmac->flags & IMX_DMA_SG_LOOP) 655 sdma_handle_channel_loop(sdmac); 656 else 657 mxc_sdma_handle_channel_normal(sdmac); 658 } 659 660 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 661 { 662 struct sdma_engine *sdma = dev_id; 663 unsigned long stat; 664 665 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 666 /* not interested in channel 0 interrupts */ 667 stat &= ~1; 668 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 669 670 while (stat) { 671 int channel = fls(stat) - 1; 672 struct sdma_channel *sdmac = &sdma->channel[channel]; 673 674 tasklet_schedule(&sdmac->tasklet); 675 676 __clear_bit(channel, &stat); 677 } 678 679 return IRQ_HANDLED; 680 } 681 682 /* 683 * sets the pc of SDMA script according to the peripheral type 684 */ 685 static void sdma_get_pc(struct sdma_channel *sdmac, 686 enum sdma_peripheral_type peripheral_type) 687 { 688 struct sdma_engine *sdma = sdmac->sdma; 689 int per_2_emi = 0, emi_2_per = 0; 690 /* 691 * These are needed once we start to support transfers between 692 * two peripherals or memory-to-memory transfers 693 */ 694 int per_2_per = 0, emi_2_emi = 0; 695 696 sdmac->pc_from_device = 0; 697 sdmac->pc_to_device = 0; 698 699 switch (peripheral_type) { 700 case IMX_DMATYPE_MEMORY: 701 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 702 break; 703 case IMX_DMATYPE_DSP: 704 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 705 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 706 break; 707 case IMX_DMATYPE_FIRI: 708 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 709 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 710 break; 711 case IMX_DMATYPE_UART: 712 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 713 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 714 break; 715 case IMX_DMATYPE_UART_SP: 716 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 717 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 718 break; 719 case IMX_DMATYPE_ATA: 720 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 721 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 722 break; 723 case IMX_DMATYPE_CSPI: 724 case IMX_DMATYPE_EXT: 725 case IMX_DMATYPE_SSI: 726 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 727 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 728 break; 729 case IMX_DMATYPE_SSI_DUAL: 730 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 731 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 732 break; 733 case IMX_DMATYPE_SSI_SP: 734 case IMX_DMATYPE_MMC: 735 case IMX_DMATYPE_SDHC: 736 case IMX_DMATYPE_CSPI_SP: 737 case IMX_DMATYPE_ESAI: 738 case IMX_DMATYPE_MSHC_SP: 739 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 740 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 741 break; 742 case IMX_DMATYPE_ASRC: 743 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 744 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 745 per_2_per = sdma->script_addrs->per_2_per_addr; 746 break; 747 case IMX_DMATYPE_MSHC: 748 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 749 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 750 break; 751 case IMX_DMATYPE_CCM: 752 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 753 break; 754 case IMX_DMATYPE_SPDIF: 755 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 756 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 757 break; 758 case IMX_DMATYPE_IPU_MEMORY: 759 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 760 break; 761 default: 762 break; 763 } 764 765 sdmac->pc_from_device = per_2_emi; 766 sdmac->pc_to_device = emi_2_per; 767 } 768 769 static int sdma_load_context(struct sdma_channel *sdmac) 770 { 771 struct sdma_engine *sdma = sdmac->sdma; 772 int channel = sdmac->channel; 773 int load_address; 774 struct sdma_context_data *context = sdma->context; 775 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 776 int ret; 777 unsigned long flags; 778 779 if (sdmac->direction == DMA_DEV_TO_MEM) { 780 load_address = sdmac->pc_from_device; 781 } else { 782 load_address = sdmac->pc_to_device; 783 } 784 785 if (load_address < 0) 786 return load_address; 787 788 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 789 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 790 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 791 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 792 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 793 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 794 795 spin_lock_irqsave(&sdma->channel_0_lock, flags); 796 797 memset(context, 0, sizeof(*context)); 798 context->channel_state.pc = load_address; 799 800 /* Send by context the event mask,base address for peripheral 801 * and watermark level 802 */ 803 context->gReg[0] = sdmac->event_mask[1]; 804 context->gReg[1] = sdmac->event_mask[0]; 805 context->gReg[2] = sdmac->per_addr; 806 context->gReg[6] = sdmac->shp_addr; 807 context->gReg[7] = sdmac->watermark_level; 808 809 bd0->mode.command = C0_SETDM; 810 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 811 bd0->mode.count = sizeof(*context) / 4; 812 bd0->buffer_addr = sdma->context_phys; 813 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 814 ret = sdma_run_channel0(sdma); 815 816 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 817 818 return ret; 819 } 820 821 static void sdma_disable_channel(struct sdma_channel *sdmac) 822 { 823 struct sdma_engine *sdma = sdmac->sdma; 824 int channel = sdmac->channel; 825 826 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 827 sdmac->status = DMA_ERROR; 828 } 829 830 static int sdma_config_channel(struct sdma_channel *sdmac) 831 { 832 int ret; 833 834 sdma_disable_channel(sdmac); 835 836 sdmac->event_mask[0] = 0; 837 sdmac->event_mask[1] = 0; 838 sdmac->shp_addr = 0; 839 sdmac->per_addr = 0; 840 841 if (sdmac->event_id0) { 842 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 843 return -EINVAL; 844 sdma_event_enable(sdmac, sdmac->event_id0); 845 } 846 847 switch (sdmac->peripheral_type) { 848 case IMX_DMATYPE_DSP: 849 sdma_config_ownership(sdmac, false, true, true); 850 break; 851 case IMX_DMATYPE_MEMORY: 852 sdma_config_ownership(sdmac, false, true, false); 853 break; 854 default: 855 sdma_config_ownership(sdmac, true, true, false); 856 break; 857 } 858 859 sdma_get_pc(sdmac, sdmac->peripheral_type); 860 861 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 862 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 863 /* Handle multiple event channels differently */ 864 if (sdmac->event_id1) { 865 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); 866 if (sdmac->event_id1 > 31) 867 __set_bit(31, &sdmac->watermark_level); 868 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); 869 if (sdmac->event_id0 > 31) 870 __set_bit(30, &sdmac->watermark_level); 871 } else { 872 __set_bit(sdmac->event_id0, sdmac->event_mask); 873 } 874 /* Watermark Level */ 875 sdmac->watermark_level |= sdmac->watermark_level; 876 /* Address */ 877 sdmac->shp_addr = sdmac->per_address; 878 } else { 879 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 880 } 881 882 ret = sdma_load_context(sdmac); 883 884 return ret; 885 } 886 887 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 888 unsigned int priority) 889 { 890 struct sdma_engine *sdma = sdmac->sdma; 891 int channel = sdmac->channel; 892 893 if (priority < MXC_SDMA_MIN_PRIORITY 894 || priority > MXC_SDMA_MAX_PRIORITY) { 895 return -EINVAL; 896 } 897 898 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 899 900 return 0; 901 } 902 903 static int sdma_request_channel(struct sdma_channel *sdmac) 904 { 905 struct sdma_engine *sdma = sdmac->sdma; 906 int channel = sdmac->channel; 907 int ret = -EBUSY; 908 909 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); 910 if (!sdmac->bd) { 911 ret = -ENOMEM; 912 goto out; 913 } 914 915 memset(sdmac->bd, 0, PAGE_SIZE); 916 917 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; 918 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 919 920 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); 921 return 0; 922 out: 923 924 return ret; 925 } 926 927 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 928 { 929 return container_of(chan, struct sdma_channel, chan); 930 } 931 932 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) 933 { 934 unsigned long flags; 935 struct sdma_channel *sdmac = to_sdma_chan(tx->chan); 936 dma_cookie_t cookie; 937 938 spin_lock_irqsave(&sdmac->lock, flags); 939 940 cookie = dma_cookie_assign(tx); 941 942 spin_unlock_irqrestore(&sdmac->lock, flags); 943 944 return cookie; 945 } 946 947 static int sdma_alloc_chan_resources(struct dma_chan *chan) 948 { 949 struct sdma_channel *sdmac = to_sdma_chan(chan); 950 struct imx_dma_data *data = chan->private; 951 int prio, ret; 952 953 if (!data) 954 return -EINVAL; 955 956 switch (data->priority) { 957 case DMA_PRIO_HIGH: 958 prio = 3; 959 break; 960 case DMA_PRIO_MEDIUM: 961 prio = 2; 962 break; 963 case DMA_PRIO_LOW: 964 default: 965 prio = 1; 966 break; 967 } 968 969 sdmac->peripheral_type = data->peripheral_type; 970 sdmac->event_id0 = data->dma_request; 971 972 clk_enable(sdmac->sdma->clk_ipg); 973 clk_enable(sdmac->sdma->clk_ahb); 974 975 ret = sdma_request_channel(sdmac); 976 if (ret) 977 return ret; 978 979 ret = sdma_set_channel_priority(sdmac, prio); 980 if (ret) 981 return ret; 982 983 dma_async_tx_descriptor_init(&sdmac->desc, chan); 984 sdmac->desc.tx_submit = sdma_tx_submit; 985 /* txd.flags will be overwritten in prep funcs */ 986 sdmac->desc.flags = DMA_CTRL_ACK; 987 988 return 0; 989 } 990 991 static void sdma_free_chan_resources(struct dma_chan *chan) 992 { 993 struct sdma_channel *sdmac = to_sdma_chan(chan); 994 struct sdma_engine *sdma = sdmac->sdma; 995 996 sdma_disable_channel(sdmac); 997 998 if (sdmac->event_id0) 999 sdma_event_disable(sdmac, sdmac->event_id0); 1000 if (sdmac->event_id1) 1001 sdma_event_disable(sdmac, sdmac->event_id1); 1002 1003 sdmac->event_id0 = 0; 1004 sdmac->event_id1 = 0; 1005 1006 sdma_set_channel_priority(sdmac, 0); 1007 1008 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); 1009 1010 clk_disable(sdma->clk_ipg); 1011 clk_disable(sdma->clk_ahb); 1012 } 1013 1014 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1015 struct dma_chan *chan, struct scatterlist *sgl, 1016 unsigned int sg_len, enum dma_transfer_direction direction, 1017 unsigned long flags, void *context) 1018 { 1019 struct sdma_channel *sdmac = to_sdma_chan(chan); 1020 struct sdma_engine *sdma = sdmac->sdma; 1021 int ret, i, count; 1022 int channel = sdmac->channel; 1023 struct scatterlist *sg; 1024 1025 if (sdmac->status == DMA_IN_PROGRESS) 1026 return NULL; 1027 sdmac->status = DMA_IN_PROGRESS; 1028 1029 sdmac->flags = 0; 1030 1031 sdmac->buf_tail = 0; 1032 1033 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1034 sg_len, channel); 1035 1036 sdmac->direction = direction; 1037 ret = sdma_load_context(sdmac); 1038 if (ret) 1039 goto err_out; 1040 1041 if (sg_len > NUM_BD) { 1042 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1043 channel, sg_len, NUM_BD); 1044 ret = -EINVAL; 1045 goto err_out; 1046 } 1047 1048 sdmac->chn_count = 0; 1049 for_each_sg(sgl, sg, sg_len, i) { 1050 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1051 int param; 1052 1053 bd->buffer_addr = sg->dma_address; 1054 1055 count = sg_dma_len(sg); 1056 1057 if (count > 0xffff) { 1058 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1059 channel, count, 0xffff); 1060 ret = -EINVAL; 1061 goto err_out; 1062 } 1063 1064 bd->mode.count = count; 1065 sdmac->chn_count += count; 1066 1067 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { 1068 ret = -EINVAL; 1069 goto err_out; 1070 } 1071 1072 switch (sdmac->word_size) { 1073 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1074 bd->mode.command = 0; 1075 if (count & 3 || sg->dma_address & 3) 1076 return NULL; 1077 break; 1078 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1079 bd->mode.command = 2; 1080 if (count & 1 || sg->dma_address & 1) 1081 return NULL; 1082 break; 1083 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1084 bd->mode.command = 1; 1085 break; 1086 default: 1087 return NULL; 1088 } 1089 1090 param = BD_DONE | BD_EXTD | BD_CONT; 1091 1092 if (i + 1 == sg_len) { 1093 param |= BD_INTR; 1094 param |= BD_LAST; 1095 param &= ~BD_CONT; 1096 } 1097 1098 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1099 i, count, (u64)sg->dma_address, 1100 param & BD_WRAP ? "wrap" : "", 1101 param & BD_INTR ? " intr" : ""); 1102 1103 bd->mode.status = param; 1104 } 1105 1106 sdmac->num_bd = sg_len; 1107 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1108 1109 return &sdmac->desc; 1110 err_out: 1111 sdmac->status = DMA_ERROR; 1112 return NULL; 1113 } 1114 1115 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1116 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1117 size_t period_len, enum dma_transfer_direction direction, 1118 unsigned long flags, void *context) 1119 { 1120 struct sdma_channel *sdmac = to_sdma_chan(chan); 1121 struct sdma_engine *sdma = sdmac->sdma; 1122 int num_periods = buf_len / period_len; 1123 int channel = sdmac->channel; 1124 int ret, i = 0, buf = 0; 1125 1126 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1127 1128 if (sdmac->status == DMA_IN_PROGRESS) 1129 return NULL; 1130 1131 sdmac->status = DMA_IN_PROGRESS; 1132 1133 sdmac->buf_tail = 0; 1134 1135 sdmac->flags |= IMX_DMA_SG_LOOP; 1136 sdmac->direction = direction; 1137 ret = sdma_load_context(sdmac); 1138 if (ret) 1139 goto err_out; 1140 1141 if (num_periods > NUM_BD) { 1142 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1143 channel, num_periods, NUM_BD); 1144 goto err_out; 1145 } 1146 1147 if (period_len > 0xffff) { 1148 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", 1149 channel, period_len, 0xffff); 1150 goto err_out; 1151 } 1152 1153 while (buf < buf_len) { 1154 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1155 int param; 1156 1157 bd->buffer_addr = dma_addr; 1158 1159 bd->mode.count = period_len; 1160 1161 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1162 goto err_out; 1163 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1164 bd->mode.command = 0; 1165 else 1166 bd->mode.command = sdmac->word_size; 1167 1168 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1169 if (i + 1 == num_periods) 1170 param |= BD_WRAP; 1171 1172 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1173 i, period_len, (u64)dma_addr, 1174 param & BD_WRAP ? "wrap" : "", 1175 param & BD_INTR ? " intr" : ""); 1176 1177 bd->mode.status = param; 1178 1179 dma_addr += period_len; 1180 buf += period_len; 1181 1182 i++; 1183 } 1184 1185 sdmac->num_bd = num_periods; 1186 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1187 1188 return &sdmac->desc; 1189 err_out: 1190 sdmac->status = DMA_ERROR; 1191 return NULL; 1192 } 1193 1194 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1195 unsigned long arg) 1196 { 1197 struct sdma_channel *sdmac = to_sdma_chan(chan); 1198 struct dma_slave_config *dmaengine_cfg = (void *)arg; 1199 1200 switch (cmd) { 1201 case DMA_TERMINATE_ALL: 1202 sdma_disable_channel(sdmac); 1203 return 0; 1204 case DMA_SLAVE_CONFIG: 1205 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 1206 sdmac->per_address = dmaengine_cfg->src_addr; 1207 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1208 dmaengine_cfg->src_addr_width; 1209 sdmac->word_size = dmaengine_cfg->src_addr_width; 1210 } else { 1211 sdmac->per_address = dmaengine_cfg->dst_addr; 1212 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1213 dmaengine_cfg->dst_addr_width; 1214 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1215 } 1216 sdmac->direction = dmaengine_cfg->direction; 1217 return sdma_config_channel(sdmac); 1218 default: 1219 return -ENOSYS; 1220 } 1221 1222 return -EINVAL; 1223 } 1224 1225 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1226 dma_cookie_t cookie, 1227 struct dma_tx_state *txstate) 1228 { 1229 struct sdma_channel *sdmac = to_sdma_chan(chan); 1230 1231 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1232 sdmac->chn_count - sdmac->chn_real_count); 1233 1234 return sdmac->status; 1235 } 1236 1237 static void sdma_issue_pending(struct dma_chan *chan) 1238 { 1239 struct sdma_channel *sdmac = to_sdma_chan(chan); 1240 struct sdma_engine *sdma = sdmac->sdma; 1241 1242 if (sdmac->status == DMA_IN_PROGRESS) 1243 sdma_enable_channel(sdma, sdmac->channel); 1244 } 1245 1246 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1247 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1248 1249 static void sdma_add_scripts(struct sdma_engine *sdma, 1250 const struct sdma_script_start_addrs *addr) 1251 { 1252 s32 *addr_arr = (u32 *)addr; 1253 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1254 int i; 1255 1256 /* use the default firmware in ROM if missing external firmware */ 1257 if (!sdma->script_number) 1258 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1259 1260 for (i = 0; i < sdma->script_number; i++) 1261 if (addr_arr[i] > 0) 1262 saddr_arr[i] = addr_arr[i]; 1263 } 1264 1265 static void sdma_load_firmware(const struct firmware *fw, void *context) 1266 { 1267 struct sdma_engine *sdma = context; 1268 const struct sdma_firmware_header *header; 1269 const struct sdma_script_start_addrs *addr; 1270 unsigned short *ram_code; 1271 1272 if (!fw) { 1273 dev_err(sdma->dev, "firmware not found\n"); 1274 return; 1275 } 1276 1277 if (fw->size < sizeof(*header)) 1278 goto err_firmware; 1279 1280 header = (struct sdma_firmware_header *)fw->data; 1281 1282 if (header->magic != SDMA_FIRMWARE_MAGIC) 1283 goto err_firmware; 1284 if (header->ram_code_start + header->ram_code_size > fw->size) 1285 goto err_firmware; 1286 switch (header->version_major) { 1287 case 1: 1288 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1289 break; 1290 case 2: 1291 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1292 break; 1293 default: 1294 dev_err(sdma->dev, "unknown firmware version\n"); 1295 goto err_firmware; 1296 } 1297 1298 addr = (void *)header + header->script_addrs_start; 1299 ram_code = (void *)header + header->ram_code_start; 1300 1301 clk_enable(sdma->clk_ipg); 1302 clk_enable(sdma->clk_ahb); 1303 /* download the RAM image for SDMA */ 1304 sdma_load_script(sdma, ram_code, 1305 header->ram_code_size, 1306 addr->ram_code_start_addr); 1307 clk_disable(sdma->clk_ipg); 1308 clk_disable(sdma->clk_ahb); 1309 1310 sdma_add_scripts(sdma, addr); 1311 1312 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1313 header->version_major, 1314 header->version_minor); 1315 1316 err_firmware: 1317 release_firmware(fw); 1318 } 1319 1320 static int __init sdma_get_firmware(struct sdma_engine *sdma, 1321 const char *fw_name) 1322 { 1323 int ret; 1324 1325 ret = request_firmware_nowait(THIS_MODULE, 1326 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1327 GFP_KERNEL, sdma, sdma_load_firmware); 1328 1329 return ret; 1330 } 1331 1332 static int __init sdma_init(struct sdma_engine *sdma) 1333 { 1334 int i, ret; 1335 dma_addr_t ccb_phys; 1336 1337 clk_enable(sdma->clk_ipg); 1338 clk_enable(sdma->clk_ahb); 1339 1340 /* Be sure SDMA has not started yet */ 1341 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1342 1343 sdma->channel_control = dma_alloc_coherent(NULL, 1344 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1345 sizeof(struct sdma_context_data), 1346 &ccb_phys, GFP_KERNEL); 1347 1348 if (!sdma->channel_control) { 1349 ret = -ENOMEM; 1350 goto err_dma_alloc; 1351 } 1352 1353 sdma->context = (void *)sdma->channel_control + 1354 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1355 sdma->context_phys = ccb_phys + 1356 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1357 1358 /* Zero-out the CCB structures array just allocated */ 1359 memset(sdma->channel_control, 0, 1360 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1361 1362 /* disable all channels */ 1363 for (i = 0; i < sdma->drvdata->num_events; i++) 1364 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1365 1366 /* All channels have priority 0 */ 1367 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1368 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1369 1370 ret = sdma_request_channel(&sdma->channel[0]); 1371 if (ret) 1372 goto err_dma_alloc; 1373 1374 sdma_config_ownership(&sdma->channel[0], false, true, false); 1375 1376 /* Set Command Channel (Channel Zero) */ 1377 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1378 1379 /* Set bits of CONFIG register but with static context switching */ 1380 /* FIXME: Check whether to set ACR bit depending on clock ratios */ 1381 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1382 1383 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1384 1385 /* Set bits of CONFIG register with given context switching mode */ 1386 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 1387 1388 /* Initializes channel's priorities */ 1389 sdma_set_channel_priority(&sdma->channel[0], 7); 1390 1391 clk_disable(sdma->clk_ipg); 1392 clk_disable(sdma->clk_ahb); 1393 1394 return 0; 1395 1396 err_dma_alloc: 1397 clk_disable(sdma->clk_ipg); 1398 clk_disable(sdma->clk_ahb); 1399 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1400 return ret; 1401 } 1402 1403 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1404 { 1405 struct imx_dma_data *data = fn_param; 1406 1407 if (!imx_dma_is_general_purpose(chan)) 1408 return false; 1409 1410 chan->private = data; 1411 1412 return true; 1413 } 1414 1415 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1416 struct of_dma *ofdma) 1417 { 1418 struct sdma_engine *sdma = ofdma->of_dma_data; 1419 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1420 struct imx_dma_data data; 1421 1422 if (dma_spec->args_count != 3) 1423 return NULL; 1424 1425 data.dma_request = dma_spec->args[0]; 1426 data.peripheral_type = dma_spec->args[1]; 1427 data.priority = dma_spec->args[2]; 1428 1429 return dma_request_channel(mask, sdma_filter_fn, &data); 1430 } 1431 1432 static int __init sdma_probe(struct platform_device *pdev) 1433 { 1434 const struct of_device_id *of_id = 1435 of_match_device(sdma_dt_ids, &pdev->dev); 1436 struct device_node *np = pdev->dev.of_node; 1437 const char *fw_name; 1438 int ret; 1439 int irq; 1440 struct resource *iores; 1441 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1442 int i; 1443 struct sdma_engine *sdma; 1444 s32 *saddr_arr; 1445 const struct sdma_driver_data *drvdata = NULL; 1446 1447 if (of_id) 1448 drvdata = of_id->data; 1449 else if (pdev->id_entry) 1450 drvdata = (void *)pdev->id_entry->driver_data; 1451 1452 if (!drvdata) { 1453 dev_err(&pdev->dev, "unable to find driver data\n"); 1454 return -EINVAL; 1455 } 1456 1457 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1458 if (ret) 1459 return ret; 1460 1461 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); 1462 if (!sdma) 1463 return -ENOMEM; 1464 1465 spin_lock_init(&sdma->channel_0_lock); 1466 1467 sdma->dev = &pdev->dev; 1468 sdma->drvdata = drvdata; 1469 1470 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1471 irq = platform_get_irq(pdev, 0); 1472 if (!iores || irq < 0) { 1473 ret = -EINVAL; 1474 goto err_irq; 1475 } 1476 1477 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { 1478 ret = -EBUSY; 1479 goto err_request_region; 1480 } 1481 1482 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1483 if (IS_ERR(sdma->clk_ipg)) { 1484 ret = PTR_ERR(sdma->clk_ipg); 1485 goto err_clk; 1486 } 1487 1488 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1489 if (IS_ERR(sdma->clk_ahb)) { 1490 ret = PTR_ERR(sdma->clk_ahb); 1491 goto err_clk; 1492 } 1493 1494 clk_prepare(sdma->clk_ipg); 1495 clk_prepare(sdma->clk_ahb); 1496 1497 sdma->regs = ioremap(iores->start, resource_size(iores)); 1498 if (!sdma->regs) { 1499 ret = -ENOMEM; 1500 goto err_ioremap; 1501 } 1502 1503 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); 1504 if (ret) 1505 goto err_request_irq; 1506 1507 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 1508 if (!sdma->script_addrs) { 1509 ret = -ENOMEM; 1510 goto err_alloc; 1511 } 1512 1513 /* initially no scripts available */ 1514 saddr_arr = (s32 *)sdma->script_addrs; 1515 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 1516 saddr_arr[i] = -EINVAL; 1517 1518 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1519 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1520 1521 INIT_LIST_HEAD(&sdma->dma_device.channels); 1522 /* Initialize channel parameters */ 1523 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1524 struct sdma_channel *sdmac = &sdma->channel[i]; 1525 1526 sdmac->sdma = sdma; 1527 spin_lock_init(&sdmac->lock); 1528 1529 sdmac->chan.device = &sdma->dma_device; 1530 dma_cookie_init(&sdmac->chan); 1531 sdmac->channel = i; 1532 1533 tasklet_init(&sdmac->tasklet, sdma_tasklet, 1534 (unsigned long) sdmac); 1535 /* 1536 * Add the channel to the DMAC list. Do not add channel 0 though 1537 * because we need it internally in the SDMA driver. This also means 1538 * that channel 0 in dmaengine counting matches sdma channel 1. 1539 */ 1540 if (i) 1541 list_add_tail(&sdmac->chan.device_node, 1542 &sdma->dma_device.channels); 1543 } 1544 1545 ret = sdma_init(sdma); 1546 if (ret) 1547 goto err_init; 1548 1549 if (sdma->drvdata->script_addrs) 1550 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 1551 if (pdata && pdata->script_addrs) 1552 sdma_add_scripts(sdma, pdata->script_addrs); 1553 1554 if (pdata) { 1555 ret = sdma_get_firmware(sdma, pdata->fw_name); 1556 if (ret) 1557 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 1558 } else { 1559 /* 1560 * Because that device tree does not encode ROM script address, 1561 * the RAM script in firmware is mandatory for device tree 1562 * probe, otherwise it fails. 1563 */ 1564 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 1565 &fw_name); 1566 if (ret) 1567 dev_warn(&pdev->dev, "failed to get firmware name\n"); 1568 else { 1569 ret = sdma_get_firmware(sdma, fw_name); 1570 if (ret) 1571 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 1572 } 1573 } 1574 1575 sdma->dma_device.dev = &pdev->dev; 1576 1577 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 1578 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 1579 sdma->dma_device.device_tx_status = sdma_tx_status; 1580 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 1581 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1582 sdma->dma_device.device_control = sdma_control; 1583 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1584 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1585 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1586 1587 ret = dma_async_device_register(&sdma->dma_device); 1588 if (ret) { 1589 dev_err(&pdev->dev, "unable to register\n"); 1590 goto err_init; 1591 } 1592 1593 if (np) { 1594 ret = of_dma_controller_register(np, sdma_xlate, sdma); 1595 if (ret) { 1596 dev_err(&pdev->dev, "failed to register controller\n"); 1597 goto err_register; 1598 } 1599 } 1600 1601 dev_info(sdma->dev, "initialized\n"); 1602 1603 return 0; 1604 1605 err_register: 1606 dma_async_device_unregister(&sdma->dma_device); 1607 err_init: 1608 kfree(sdma->script_addrs); 1609 err_alloc: 1610 free_irq(irq, sdma); 1611 err_request_irq: 1612 iounmap(sdma->regs); 1613 err_ioremap: 1614 err_clk: 1615 release_mem_region(iores->start, resource_size(iores)); 1616 err_request_region: 1617 err_irq: 1618 kfree(sdma); 1619 return ret; 1620 } 1621 1622 static int sdma_remove(struct platform_device *pdev) 1623 { 1624 return -EBUSY; 1625 } 1626 1627 static struct platform_driver sdma_driver = { 1628 .driver = { 1629 .name = "imx-sdma", 1630 .of_match_table = sdma_dt_ids, 1631 }, 1632 .id_table = sdma_devtypes, 1633 .remove = sdma_remove, 1634 }; 1635 1636 static int __init sdma_module_init(void) 1637 { 1638 return platform_driver_probe(&sdma_driver, sdma_probe); 1639 } 1640 module_init(sdma_module_init); 1641 1642 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1643 MODULE_DESCRIPTION("i.MX SDMA driver"); 1644 MODULE_LICENSE("GPL"); 1645