1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // drivers/dma/imx-sdma.c 4 // 5 // This file contains a driver for the Freescale Smart DMA engine 6 // 7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 // 9 // Based on code from Freescale: 10 // 11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 12 13 #include <linux/init.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/types.h> 17 #include <linux/bitops.h> 18 #include <linux/mm.h> 19 #include <linux/interrupt.h> 20 #include <linux/clk.h> 21 #include <linux/delay.h> 22 #include <linux/sched.h> 23 #include <linux/semaphore.h> 24 #include <linux/spinlock.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firmware.h> 28 #include <linux/slab.h> 29 #include <linux/platform_device.h> 30 #include <linux/dmaengine.h> 31 #include <linux/of.h> 32 #include <linux/of_address.h> 33 #include <linux/of_device.h> 34 #include <linux/of_dma.h> 35 #include <linux/workqueue.h> 36 37 #include <asm/irq.h> 38 #include <linux/platform_data/dma-imx-sdma.h> 39 #include <linux/platform_data/dma-imx.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 43 44 #include "dmaengine.h" 45 #include "virt-dma.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * p_2_p watermark_level description 128 * Bits Name Description 129 * 0-7 Lower WML Lower watermark level 130 * 8 PS 1: Pad Swallowing 131 * 0: No Pad Swallowing 132 * 9 PA 1: Pad Adding 133 * 0: No Pad Adding 134 * 10 SPDIF If this bit is set both source 135 * and destination are on SPBA 136 * 11 Source Bit(SP) 1: Source on SPBA 137 * 0: Source on AIPS 138 * 12 Destination Bit(DP) 1: Destination on SPBA 139 * 0: Destination on AIPS 140 * 13-15 --------- MUST BE 0 141 * 16-23 Higher WML HWML 142 * 24-27 N Total number of samples after 143 * which Pad adding/Swallowing 144 * must be done. It must be odd. 145 * 28 Lower WML Event(LWE) SDMA events reg to check for 146 * LWML event mask 147 * 0: LWE in EVENTS register 148 * 1: LWE in EVENTS2 register 149 * 29 Higher WML Event(HWE) SDMA events reg to check for 150 * HWML event mask 151 * 0: HWE in EVENTS register 152 * 1: HWE in EVENTS2 register 153 * 30 --------- MUST BE 0 154 * 31 CONT 1: Amount of samples to be 155 * transferred is unknown and 156 * script will keep on 157 * transferring samples as long as 158 * both events are detected and 159 * script must be manually stopped 160 * by the application 161 * 0: The amount of samples to be 162 * transferred is equal to the 163 * count field of mode word 164 */ 165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF 166 #define SDMA_WATERMARK_LEVEL_PS BIT(8) 167 #define SDMA_WATERMARK_LEVEL_PA BIT(9) 168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) 169 #define SDMA_WATERMARK_LEVEL_SP BIT(11) 170 #define SDMA_WATERMARK_LEVEL_DP BIT(12) 171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) 172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28) 173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29) 174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31) 175 176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 179 180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ 181 BIT(DMA_MEM_TO_DEV) | \ 182 BIT(DMA_DEV_TO_DEV)) 183 184 /* 185 * Mode/Count of data node descriptors - IPCv2 186 */ 187 struct sdma_mode_count { 188 #define SDMA_BD_MAX_CNT 0xffff 189 u32 count : 16; /* size of the buffer pointed by this BD */ 190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 191 u32 command : 8; /* command mostly used for channel 0 */ 192 }; 193 194 /* 195 * Buffer descriptor 196 */ 197 struct sdma_buffer_descriptor { 198 struct sdma_mode_count mode; 199 u32 buffer_addr; /* address of the buffer described */ 200 u32 ext_buffer_addr; /* extended buffer address */ 201 } __attribute__ ((packed)); 202 203 /** 204 * struct sdma_channel_control - Channel control Block 205 * 206 * @current_bd_ptr: current buffer descriptor processed 207 * @base_bd_ptr: first element of buffer descriptor array 208 * @unused: padding. The SDMA engine expects an array of 128 byte 209 * control blocks 210 */ 211 struct sdma_channel_control { 212 u32 current_bd_ptr; 213 u32 base_bd_ptr; 214 u32 unused[2]; 215 } __attribute__ ((packed)); 216 217 /** 218 * struct sdma_state_registers - SDMA context for a channel 219 * 220 * @pc: program counter 221 * @unused1: unused 222 * @t: test bit: status of arithmetic & test instruction 223 * @rpc: return program counter 224 * @unused0: unused 225 * @sf: source fault while loading data 226 * @spc: loop start program counter 227 * @unused2: unused 228 * @df: destination fault while storing data 229 * @epc: loop end program counter 230 * @lm: loop mode 231 */ 232 struct sdma_state_registers { 233 u32 pc :14; 234 u32 unused1: 1; 235 u32 t : 1; 236 u32 rpc :14; 237 u32 unused0: 1; 238 u32 sf : 1; 239 u32 spc :14; 240 u32 unused2: 1; 241 u32 df : 1; 242 u32 epc :14; 243 u32 lm : 2; 244 } __attribute__ ((packed)); 245 246 /** 247 * struct sdma_context_data - sdma context specific to a channel 248 * 249 * @channel_state: channel state bits 250 * @gReg: general registers 251 * @mda: burst dma destination address register 252 * @msa: burst dma source address register 253 * @ms: burst dma status register 254 * @md: burst dma data register 255 * @pda: peripheral dma destination address register 256 * @psa: peripheral dma source address register 257 * @ps: peripheral dma status register 258 * @pd: peripheral dma data register 259 * @ca: CRC polynomial register 260 * @cs: CRC accumulator register 261 * @dda: dedicated core destination address register 262 * @dsa: dedicated core source address register 263 * @ds: dedicated core status register 264 * @dd: dedicated core data register 265 * @scratch0: 1st word of dedicated ram for context switch 266 * @scratch1: 2nd word of dedicated ram for context switch 267 * @scratch2: 3rd word of dedicated ram for context switch 268 * @scratch3: 4th word of dedicated ram for context switch 269 * @scratch4: 5th word of dedicated ram for context switch 270 * @scratch5: 6th word of dedicated ram for context switch 271 * @scratch6: 7th word of dedicated ram for context switch 272 * @scratch7: 8th word of dedicated ram for context switch 273 */ 274 struct sdma_context_data { 275 struct sdma_state_registers channel_state; 276 u32 gReg[8]; 277 u32 mda; 278 u32 msa; 279 u32 ms; 280 u32 md; 281 u32 pda; 282 u32 psa; 283 u32 ps; 284 u32 pd; 285 u32 ca; 286 u32 cs; 287 u32 dda; 288 u32 dsa; 289 u32 ds; 290 u32 dd; 291 u32 scratch0; 292 u32 scratch1; 293 u32 scratch2; 294 u32 scratch3; 295 u32 scratch4; 296 u32 scratch5; 297 u32 scratch6; 298 u32 scratch7; 299 } __attribute__ ((packed)); 300 301 302 struct sdma_engine; 303 304 /** 305 * struct sdma_desc - descriptor structor for one transfer 306 * @vd: descriptor for virt dma 307 * @num_bd: number of descriptors currently handling 308 * @bd_phys: physical address of bd 309 * @buf_tail: ID of the buffer that was processed 310 * @buf_ptail: ID of the previous buffer that was processed 311 * @period_len: period length, used in cyclic. 312 * @chn_real_count: the real count updated from bd->mode.count 313 * @chn_count: the transfer count set 314 * @sdmac: sdma_channel pointer 315 * @bd: pointer of allocate bd 316 */ 317 struct sdma_desc { 318 struct virt_dma_desc vd; 319 unsigned int num_bd; 320 dma_addr_t bd_phys; 321 unsigned int buf_tail; 322 unsigned int buf_ptail; 323 unsigned int period_len; 324 unsigned int chn_real_count; 325 unsigned int chn_count; 326 struct sdma_channel *sdmac; 327 struct sdma_buffer_descriptor *bd; 328 }; 329 330 /** 331 * struct sdma_channel - housekeeping for a SDMA channel 332 * 333 * @vc: virt_dma base structure 334 * @desc: sdma description including vd and other special member 335 * @sdma: pointer to the SDMA engine for this channel 336 * @channel: the channel number, matches dmaengine chan_id + 1 337 * @direction: transfer type. Needed for setting SDMA script 338 * @slave_config: Slave configuration 339 * @peripheral_type: Peripheral type. Needed for setting SDMA script 340 * @event_id0: aka dma request line 341 * @event_id1: for channels that use 2 events 342 * @word_size: peripheral access size 343 * @pc_from_device: script address for those device_2_memory 344 * @pc_to_device: script address for those memory_2_device 345 * @device_to_device: script address for those device_2_device 346 * @pc_to_pc: script address for those memory_2_memory 347 * @flags: loop mode or not 348 * @per_address: peripheral source or destination address in common case 349 * destination address in p_2_p case 350 * @per_address2: peripheral source address in p_2_p case 351 * @event_mask: event mask used in p_2_p script 352 * @watermark_level: value for gReg[7], some script will extend it from 353 * basic watermark such as p_2_p 354 * @shp_addr: value for gReg[6] 355 * @per_addr: value for gReg[2] 356 * @status: status of dma channel 357 * @context_loaded: ensure context is only loaded once 358 * @data: specific sdma interface structure 359 * @bd_pool: dma_pool for bd 360 * @terminate_worker: used to call back into terminate work function 361 */ 362 struct sdma_channel { 363 struct virt_dma_chan vc; 364 struct sdma_desc *desc; 365 struct sdma_engine *sdma; 366 unsigned int channel; 367 enum dma_transfer_direction direction; 368 struct dma_slave_config slave_config; 369 enum sdma_peripheral_type peripheral_type; 370 unsigned int event_id0; 371 unsigned int event_id1; 372 enum dma_slave_buswidth word_size; 373 unsigned int pc_from_device, pc_to_device; 374 unsigned int device_to_device; 375 unsigned int pc_to_pc; 376 unsigned long flags; 377 dma_addr_t per_address, per_address2; 378 unsigned long event_mask[2]; 379 unsigned long watermark_level; 380 u32 shp_addr, per_addr; 381 enum dma_status status; 382 bool context_loaded; 383 struct imx_dma_data data; 384 struct work_struct terminate_worker; 385 }; 386 387 #define IMX_DMA_SG_LOOP BIT(0) 388 389 #define MAX_DMA_CHANNELS 32 390 #define MXC_SDMA_DEFAULT_PRIORITY 1 391 #define MXC_SDMA_MIN_PRIORITY 1 392 #define MXC_SDMA_MAX_PRIORITY 7 393 394 #define SDMA_FIRMWARE_MAGIC 0x414d4453 395 396 /** 397 * struct sdma_firmware_header - Layout of the firmware image 398 * 399 * @magic: "SDMA" 400 * @version_major: increased whenever layout of struct 401 * sdma_script_start_addrs changes. 402 * @version_minor: firmware minor version (for binary compatible changes) 403 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image 404 * @num_script_addrs: Number of script addresses in this image 405 * @ram_code_start: offset of SDMA ram image in this firmware image 406 * @ram_code_size: size of SDMA ram image 407 * @script_addrs: Stores the start address of the SDMA scripts 408 * (in SDMA memory space) 409 */ 410 struct sdma_firmware_header { 411 u32 magic; 412 u32 version_major; 413 u32 version_minor; 414 u32 script_addrs_start; 415 u32 num_script_addrs; 416 u32 ram_code_start; 417 u32 ram_code_size; 418 }; 419 420 struct sdma_driver_data { 421 int chnenbl0; 422 int num_events; 423 struct sdma_script_start_addrs *script_addrs; 424 bool check_ratio; 425 }; 426 427 struct sdma_engine { 428 struct device *dev; 429 struct sdma_channel channel[MAX_DMA_CHANNELS]; 430 struct sdma_channel_control *channel_control; 431 void __iomem *regs; 432 struct sdma_context_data *context; 433 dma_addr_t context_phys; 434 struct dma_device dma_device; 435 struct clk *clk_ipg; 436 struct clk *clk_ahb; 437 spinlock_t channel_0_lock; 438 u32 script_number; 439 struct sdma_script_start_addrs *script_addrs; 440 const struct sdma_driver_data *drvdata; 441 u32 spba_start_addr; 442 u32 spba_end_addr; 443 unsigned int irq; 444 dma_addr_t bd0_phys; 445 struct sdma_buffer_descriptor *bd0; 446 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ 447 bool clk_ratio; 448 }; 449 450 static int sdma_config_write(struct dma_chan *chan, 451 struct dma_slave_config *dmaengine_cfg, 452 enum dma_transfer_direction direction); 453 454 static struct sdma_driver_data sdma_imx31 = { 455 .chnenbl0 = SDMA_CHNENBL0_IMX31, 456 .num_events = 32, 457 }; 458 459 static struct sdma_script_start_addrs sdma_script_imx25 = { 460 .ap_2_ap_addr = 729, 461 .uart_2_mcu_addr = 904, 462 .per_2_app_addr = 1255, 463 .mcu_2_app_addr = 834, 464 .uartsh_2_mcu_addr = 1120, 465 .per_2_shp_addr = 1329, 466 .mcu_2_shp_addr = 1048, 467 .ata_2_mcu_addr = 1560, 468 .mcu_2_ata_addr = 1479, 469 .app_2_per_addr = 1189, 470 .app_2_mcu_addr = 770, 471 .shp_2_per_addr = 1407, 472 .shp_2_mcu_addr = 979, 473 }; 474 475 static struct sdma_driver_data sdma_imx25 = { 476 .chnenbl0 = SDMA_CHNENBL0_IMX35, 477 .num_events = 48, 478 .script_addrs = &sdma_script_imx25, 479 }; 480 481 static struct sdma_driver_data sdma_imx35 = { 482 .chnenbl0 = SDMA_CHNENBL0_IMX35, 483 .num_events = 48, 484 }; 485 486 static struct sdma_script_start_addrs sdma_script_imx51 = { 487 .ap_2_ap_addr = 642, 488 .uart_2_mcu_addr = 817, 489 .mcu_2_app_addr = 747, 490 .mcu_2_shp_addr = 961, 491 .ata_2_mcu_addr = 1473, 492 .mcu_2_ata_addr = 1392, 493 .app_2_per_addr = 1033, 494 .app_2_mcu_addr = 683, 495 .shp_2_per_addr = 1251, 496 .shp_2_mcu_addr = 892, 497 }; 498 499 static struct sdma_driver_data sdma_imx51 = { 500 .chnenbl0 = SDMA_CHNENBL0_IMX35, 501 .num_events = 48, 502 .script_addrs = &sdma_script_imx51, 503 }; 504 505 static struct sdma_script_start_addrs sdma_script_imx53 = { 506 .ap_2_ap_addr = 642, 507 .app_2_mcu_addr = 683, 508 .mcu_2_app_addr = 747, 509 .uart_2_mcu_addr = 817, 510 .shp_2_mcu_addr = 891, 511 .mcu_2_shp_addr = 960, 512 .uartsh_2_mcu_addr = 1032, 513 .spdif_2_mcu_addr = 1100, 514 .mcu_2_spdif_addr = 1134, 515 .firi_2_mcu_addr = 1193, 516 .mcu_2_firi_addr = 1290, 517 }; 518 519 static struct sdma_driver_data sdma_imx53 = { 520 .chnenbl0 = SDMA_CHNENBL0_IMX35, 521 .num_events = 48, 522 .script_addrs = &sdma_script_imx53, 523 }; 524 525 static struct sdma_script_start_addrs sdma_script_imx6q = { 526 .ap_2_ap_addr = 642, 527 .uart_2_mcu_addr = 817, 528 .mcu_2_app_addr = 747, 529 .per_2_per_addr = 6331, 530 .uartsh_2_mcu_addr = 1032, 531 .mcu_2_shp_addr = 960, 532 .app_2_mcu_addr = 683, 533 .shp_2_mcu_addr = 891, 534 .spdif_2_mcu_addr = 1100, 535 .mcu_2_spdif_addr = 1134, 536 }; 537 538 static struct sdma_driver_data sdma_imx6q = { 539 .chnenbl0 = SDMA_CHNENBL0_IMX35, 540 .num_events = 48, 541 .script_addrs = &sdma_script_imx6q, 542 }; 543 544 static struct sdma_script_start_addrs sdma_script_imx7d = { 545 .ap_2_ap_addr = 644, 546 .uart_2_mcu_addr = 819, 547 .mcu_2_app_addr = 749, 548 .uartsh_2_mcu_addr = 1034, 549 .mcu_2_shp_addr = 962, 550 .app_2_mcu_addr = 685, 551 .shp_2_mcu_addr = 893, 552 .spdif_2_mcu_addr = 1102, 553 .mcu_2_spdif_addr = 1136, 554 }; 555 556 static struct sdma_driver_data sdma_imx7d = { 557 .chnenbl0 = SDMA_CHNENBL0_IMX35, 558 .num_events = 48, 559 .script_addrs = &sdma_script_imx7d, 560 }; 561 562 static struct sdma_driver_data sdma_imx8mq = { 563 .chnenbl0 = SDMA_CHNENBL0_IMX35, 564 .num_events = 48, 565 .script_addrs = &sdma_script_imx7d, 566 .check_ratio = 1, 567 }; 568 569 static const struct of_device_id sdma_dt_ids[] = { 570 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 571 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 572 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 573 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 574 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 575 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 576 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, 577 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, 578 { /* sentinel */ } 579 }; 580 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 581 582 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 583 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 584 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 585 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 586 587 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 588 { 589 u32 chnenbl0 = sdma->drvdata->chnenbl0; 590 return chnenbl0 + event * 4; 591 } 592 593 static int sdma_config_ownership(struct sdma_channel *sdmac, 594 bool event_override, bool mcu_override, bool dsp_override) 595 { 596 struct sdma_engine *sdma = sdmac->sdma; 597 int channel = sdmac->channel; 598 unsigned long evt, mcu, dsp; 599 600 if (event_override && mcu_override && dsp_override) 601 return -EINVAL; 602 603 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 604 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 605 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 606 607 if (dsp_override) 608 __clear_bit(channel, &dsp); 609 else 610 __set_bit(channel, &dsp); 611 612 if (event_override) 613 __clear_bit(channel, &evt); 614 else 615 __set_bit(channel, &evt); 616 617 if (mcu_override) 618 __clear_bit(channel, &mcu); 619 else 620 __set_bit(channel, &mcu); 621 622 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 623 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 624 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 625 626 return 0; 627 } 628 629 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 630 { 631 writel(BIT(channel), sdma->regs + SDMA_H_START); 632 } 633 634 /* 635 * sdma_run_channel0 - run a channel and wait till it's done 636 */ 637 static int sdma_run_channel0(struct sdma_engine *sdma) 638 { 639 int ret; 640 u32 reg; 641 642 sdma_enable_channel(sdma, 0); 643 644 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, 645 reg, !(reg & 1), 1, 500); 646 if (ret) 647 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 648 649 /* Set bits of CONFIG register with dynamic context switching */ 650 reg = readl(sdma->regs + SDMA_H_CONFIG); 651 if ((reg & SDMA_H_CONFIG_CSM) == 0) { 652 reg |= SDMA_H_CONFIG_CSM; 653 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); 654 } 655 656 return ret; 657 } 658 659 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 660 u32 address) 661 { 662 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 663 void *buf_virt; 664 dma_addr_t buf_phys; 665 int ret; 666 unsigned long flags; 667 668 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); 669 if (!buf_virt) { 670 return -ENOMEM; 671 } 672 673 spin_lock_irqsave(&sdma->channel_0_lock, flags); 674 675 bd0->mode.command = C0_SETPM; 676 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; 677 bd0->mode.count = size / 2; 678 bd0->buffer_addr = buf_phys; 679 bd0->ext_buffer_addr = address; 680 681 memcpy(buf_virt, buf, size); 682 683 ret = sdma_run_channel0(sdma); 684 685 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 686 687 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); 688 689 return ret; 690 } 691 692 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 693 { 694 struct sdma_engine *sdma = sdmac->sdma; 695 int channel = sdmac->channel; 696 unsigned long val; 697 u32 chnenbl = chnenbl_ofs(sdma, event); 698 699 val = readl_relaxed(sdma->regs + chnenbl); 700 __set_bit(channel, &val); 701 writel_relaxed(val, sdma->regs + chnenbl); 702 } 703 704 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 705 { 706 struct sdma_engine *sdma = sdmac->sdma; 707 int channel = sdmac->channel; 708 u32 chnenbl = chnenbl_ofs(sdma, event); 709 unsigned long val; 710 711 val = readl_relaxed(sdma->regs + chnenbl); 712 __clear_bit(channel, &val); 713 writel_relaxed(val, sdma->regs + chnenbl); 714 } 715 716 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t) 717 { 718 return container_of(t, struct sdma_desc, vd.tx); 719 } 720 721 static void sdma_start_desc(struct sdma_channel *sdmac) 722 { 723 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); 724 struct sdma_desc *desc; 725 struct sdma_engine *sdma = sdmac->sdma; 726 int channel = sdmac->channel; 727 728 if (!vd) { 729 sdmac->desc = NULL; 730 return; 731 } 732 sdmac->desc = desc = to_sdma_desc(&vd->tx); 733 734 list_del(&vd->node); 735 736 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; 737 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; 738 sdma_enable_channel(sdma, sdmac->channel); 739 } 740 741 static void sdma_update_channel_loop(struct sdma_channel *sdmac) 742 { 743 struct sdma_buffer_descriptor *bd; 744 int error = 0; 745 enum dma_status old_status = sdmac->status; 746 747 /* 748 * loop mode. Iterate over descriptors, re-setup them and 749 * call callback function. 750 */ 751 while (sdmac->desc) { 752 struct sdma_desc *desc = sdmac->desc; 753 754 bd = &desc->bd[desc->buf_tail]; 755 756 if (bd->mode.status & BD_DONE) 757 break; 758 759 if (bd->mode.status & BD_RROR) { 760 bd->mode.status &= ~BD_RROR; 761 sdmac->status = DMA_ERROR; 762 error = -EIO; 763 } 764 765 /* 766 * We use bd->mode.count to calculate the residue, since contains 767 * the number of bytes present in the current buffer descriptor. 768 */ 769 770 desc->chn_real_count = bd->mode.count; 771 bd->mode.status |= BD_DONE; 772 bd->mode.count = desc->period_len; 773 desc->buf_ptail = desc->buf_tail; 774 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; 775 776 /* 777 * The callback is called from the interrupt context in order 778 * to reduce latency and to avoid the risk of altering the 779 * SDMA transaction status by the time the client tasklet is 780 * executed. 781 */ 782 spin_unlock(&sdmac->vc.lock); 783 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); 784 spin_lock(&sdmac->vc.lock); 785 786 if (error) 787 sdmac->status = old_status; 788 } 789 } 790 791 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data) 792 { 793 struct sdma_channel *sdmac = (struct sdma_channel *) data; 794 struct sdma_buffer_descriptor *bd; 795 int i, error = 0; 796 797 sdmac->desc->chn_real_count = 0; 798 /* 799 * non loop mode. Iterate over all descriptors, collect 800 * errors and call callback function 801 */ 802 for (i = 0; i < sdmac->desc->num_bd; i++) { 803 bd = &sdmac->desc->bd[i]; 804 805 if (bd->mode.status & (BD_DONE | BD_RROR)) 806 error = -EIO; 807 sdmac->desc->chn_real_count += bd->mode.count; 808 } 809 810 if (error) 811 sdmac->status = DMA_ERROR; 812 else 813 sdmac->status = DMA_COMPLETE; 814 } 815 816 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 817 { 818 struct sdma_engine *sdma = dev_id; 819 unsigned long stat; 820 821 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 822 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 823 /* channel 0 is special and not handled here, see run_channel0() */ 824 stat &= ~1; 825 826 while (stat) { 827 int channel = fls(stat) - 1; 828 struct sdma_channel *sdmac = &sdma->channel[channel]; 829 struct sdma_desc *desc; 830 831 spin_lock(&sdmac->vc.lock); 832 desc = sdmac->desc; 833 if (desc) { 834 if (sdmac->flags & IMX_DMA_SG_LOOP) { 835 sdma_update_channel_loop(sdmac); 836 } else { 837 mxc_sdma_handle_channel_normal(sdmac); 838 vchan_cookie_complete(&desc->vd); 839 sdma_start_desc(sdmac); 840 } 841 } 842 843 spin_unlock(&sdmac->vc.lock); 844 __clear_bit(channel, &stat); 845 } 846 847 return IRQ_HANDLED; 848 } 849 850 /* 851 * sets the pc of SDMA script according to the peripheral type 852 */ 853 static void sdma_get_pc(struct sdma_channel *sdmac, 854 enum sdma_peripheral_type peripheral_type) 855 { 856 struct sdma_engine *sdma = sdmac->sdma; 857 int per_2_emi = 0, emi_2_per = 0; 858 /* 859 * These are needed once we start to support transfers between 860 * two peripherals or memory-to-memory transfers 861 */ 862 int per_2_per = 0, emi_2_emi = 0; 863 864 sdmac->pc_from_device = 0; 865 sdmac->pc_to_device = 0; 866 sdmac->device_to_device = 0; 867 sdmac->pc_to_pc = 0; 868 869 switch (peripheral_type) { 870 case IMX_DMATYPE_MEMORY: 871 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 872 break; 873 case IMX_DMATYPE_DSP: 874 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 875 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 876 break; 877 case IMX_DMATYPE_FIRI: 878 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 879 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 880 break; 881 case IMX_DMATYPE_UART: 882 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 883 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 884 break; 885 case IMX_DMATYPE_UART_SP: 886 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 887 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 888 break; 889 case IMX_DMATYPE_ATA: 890 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 891 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 892 break; 893 case IMX_DMATYPE_CSPI: 894 case IMX_DMATYPE_EXT: 895 case IMX_DMATYPE_SSI: 896 case IMX_DMATYPE_SAI: 897 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 898 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 899 break; 900 case IMX_DMATYPE_SSI_DUAL: 901 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 902 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 903 break; 904 case IMX_DMATYPE_SSI_SP: 905 case IMX_DMATYPE_MMC: 906 case IMX_DMATYPE_SDHC: 907 case IMX_DMATYPE_CSPI_SP: 908 case IMX_DMATYPE_ESAI: 909 case IMX_DMATYPE_MSHC_SP: 910 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 911 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 912 break; 913 case IMX_DMATYPE_ASRC: 914 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 915 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 916 per_2_per = sdma->script_addrs->per_2_per_addr; 917 break; 918 case IMX_DMATYPE_ASRC_SP: 919 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 920 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 921 per_2_per = sdma->script_addrs->per_2_per_addr; 922 break; 923 case IMX_DMATYPE_MSHC: 924 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 925 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 926 break; 927 case IMX_DMATYPE_CCM: 928 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 929 break; 930 case IMX_DMATYPE_SPDIF: 931 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 932 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 933 break; 934 case IMX_DMATYPE_IPU_MEMORY: 935 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 936 break; 937 default: 938 break; 939 } 940 941 sdmac->pc_from_device = per_2_emi; 942 sdmac->pc_to_device = emi_2_per; 943 sdmac->device_to_device = per_2_per; 944 sdmac->pc_to_pc = emi_2_emi; 945 } 946 947 static int sdma_load_context(struct sdma_channel *sdmac) 948 { 949 struct sdma_engine *sdma = sdmac->sdma; 950 int channel = sdmac->channel; 951 int load_address; 952 struct sdma_context_data *context = sdma->context; 953 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 954 int ret; 955 unsigned long flags; 956 957 if (sdmac->context_loaded) 958 return 0; 959 960 if (sdmac->direction == DMA_DEV_TO_MEM) 961 load_address = sdmac->pc_from_device; 962 else if (sdmac->direction == DMA_DEV_TO_DEV) 963 load_address = sdmac->device_to_device; 964 else if (sdmac->direction == DMA_MEM_TO_MEM) 965 load_address = sdmac->pc_to_pc; 966 else 967 load_address = sdmac->pc_to_device; 968 969 if (load_address < 0) 970 return load_address; 971 972 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 973 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 974 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 975 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 976 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 977 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 978 979 spin_lock_irqsave(&sdma->channel_0_lock, flags); 980 981 memset(context, 0, sizeof(*context)); 982 context->channel_state.pc = load_address; 983 984 /* Send by context the event mask,base address for peripheral 985 * and watermark level 986 */ 987 context->gReg[0] = sdmac->event_mask[1]; 988 context->gReg[1] = sdmac->event_mask[0]; 989 context->gReg[2] = sdmac->per_addr; 990 context->gReg[6] = sdmac->shp_addr; 991 context->gReg[7] = sdmac->watermark_level; 992 993 bd0->mode.command = C0_SETDM; 994 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; 995 bd0->mode.count = sizeof(*context) / 4; 996 bd0->buffer_addr = sdma->context_phys; 997 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 998 ret = sdma_run_channel0(sdma); 999 1000 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 1001 1002 sdmac->context_loaded = true; 1003 1004 return ret; 1005 } 1006 1007 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 1008 { 1009 return container_of(chan, struct sdma_channel, vc.chan); 1010 } 1011 1012 static int sdma_disable_channel(struct dma_chan *chan) 1013 { 1014 struct sdma_channel *sdmac = to_sdma_chan(chan); 1015 struct sdma_engine *sdma = sdmac->sdma; 1016 int channel = sdmac->channel; 1017 1018 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 1019 sdmac->status = DMA_ERROR; 1020 1021 return 0; 1022 } 1023 static void sdma_channel_terminate_work(struct work_struct *work) 1024 { 1025 struct sdma_channel *sdmac = container_of(work, struct sdma_channel, 1026 terminate_worker); 1027 unsigned long flags; 1028 LIST_HEAD(head); 1029 1030 /* 1031 * According to NXP R&D team a delay of one BD SDMA cost time 1032 * (maximum is 1ms) should be added after disable of the channel 1033 * bit, to ensure SDMA core has really been stopped after SDMA 1034 * clients call .device_terminate_all. 1035 */ 1036 usleep_range(1000, 2000); 1037 1038 spin_lock_irqsave(&sdmac->vc.lock, flags); 1039 vchan_get_all_descriptors(&sdmac->vc, &head); 1040 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1041 vchan_dma_desc_free_list(&sdmac->vc, &head); 1042 sdmac->context_loaded = false; 1043 } 1044 1045 static int sdma_terminate_all(struct dma_chan *chan) 1046 { 1047 struct sdma_channel *sdmac = to_sdma_chan(chan); 1048 unsigned long flags; 1049 1050 spin_lock_irqsave(&sdmac->vc.lock, flags); 1051 1052 sdma_disable_channel(chan); 1053 1054 if (sdmac->desc) { 1055 vchan_terminate_vdesc(&sdmac->desc->vd); 1056 sdmac->desc = NULL; 1057 schedule_work(&sdmac->terminate_worker); 1058 } 1059 1060 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1061 1062 return 0; 1063 } 1064 1065 static void sdma_channel_synchronize(struct dma_chan *chan) 1066 { 1067 struct sdma_channel *sdmac = to_sdma_chan(chan); 1068 1069 vchan_synchronize(&sdmac->vc); 1070 1071 flush_work(&sdmac->terminate_worker); 1072 } 1073 1074 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) 1075 { 1076 struct sdma_engine *sdma = sdmac->sdma; 1077 1078 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; 1079 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; 1080 1081 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); 1082 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); 1083 1084 if (sdmac->event_id0 > 31) 1085 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; 1086 1087 if (sdmac->event_id1 > 31) 1088 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; 1089 1090 /* 1091 * If LWML(src_maxburst) > HWML(dst_maxburst), we need 1092 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap 1093 * r0(event_mask[1]) and r1(event_mask[0]). 1094 */ 1095 if (lwml > hwml) { 1096 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | 1097 SDMA_WATERMARK_LEVEL_HWML); 1098 sdmac->watermark_level |= hwml; 1099 sdmac->watermark_level |= lwml << 16; 1100 swap(sdmac->event_mask[0], sdmac->event_mask[1]); 1101 } 1102 1103 if (sdmac->per_address2 >= sdma->spba_start_addr && 1104 sdmac->per_address2 <= sdma->spba_end_addr) 1105 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; 1106 1107 if (sdmac->per_address >= sdma->spba_start_addr && 1108 sdmac->per_address <= sdma->spba_end_addr) 1109 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; 1110 1111 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; 1112 } 1113 1114 static int sdma_config_channel(struct dma_chan *chan) 1115 { 1116 struct sdma_channel *sdmac = to_sdma_chan(chan); 1117 int ret; 1118 1119 sdma_disable_channel(chan); 1120 1121 sdmac->event_mask[0] = 0; 1122 sdmac->event_mask[1] = 0; 1123 sdmac->shp_addr = 0; 1124 sdmac->per_addr = 0; 1125 1126 switch (sdmac->peripheral_type) { 1127 case IMX_DMATYPE_DSP: 1128 sdma_config_ownership(sdmac, false, true, true); 1129 break; 1130 case IMX_DMATYPE_MEMORY: 1131 sdma_config_ownership(sdmac, false, true, false); 1132 break; 1133 default: 1134 sdma_config_ownership(sdmac, true, true, false); 1135 break; 1136 } 1137 1138 sdma_get_pc(sdmac, sdmac->peripheral_type); 1139 1140 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 1141 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 1142 /* Handle multiple event channels differently */ 1143 if (sdmac->event_id1) { 1144 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || 1145 sdmac->peripheral_type == IMX_DMATYPE_ASRC) 1146 sdma_set_watermarklevel_for_p2p(sdmac); 1147 } else 1148 __set_bit(sdmac->event_id0, sdmac->event_mask); 1149 1150 /* Address */ 1151 sdmac->shp_addr = sdmac->per_address; 1152 sdmac->per_addr = sdmac->per_address2; 1153 } else { 1154 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 1155 } 1156 1157 ret = sdma_load_context(sdmac); 1158 1159 return ret; 1160 } 1161 1162 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 1163 unsigned int priority) 1164 { 1165 struct sdma_engine *sdma = sdmac->sdma; 1166 int channel = sdmac->channel; 1167 1168 if (priority < MXC_SDMA_MIN_PRIORITY 1169 || priority > MXC_SDMA_MAX_PRIORITY) { 1170 return -EINVAL; 1171 } 1172 1173 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 1174 1175 return 0; 1176 } 1177 1178 static int sdma_request_channel0(struct sdma_engine *sdma) 1179 { 1180 int ret = -EBUSY; 1181 1182 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, 1183 GFP_NOWAIT); 1184 if (!sdma->bd0) { 1185 ret = -ENOMEM; 1186 goto out; 1187 } 1188 1189 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; 1190 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; 1191 1192 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); 1193 return 0; 1194 out: 1195 1196 return ret; 1197 } 1198 1199 1200 static int sdma_alloc_bd(struct sdma_desc *desc) 1201 { 1202 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1203 int ret = 0; 1204 1205 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, 1206 &desc->bd_phys, GFP_NOWAIT); 1207 if (!desc->bd) { 1208 ret = -ENOMEM; 1209 goto out; 1210 } 1211 out: 1212 return ret; 1213 } 1214 1215 static void sdma_free_bd(struct sdma_desc *desc) 1216 { 1217 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1218 1219 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, 1220 desc->bd_phys); 1221 } 1222 1223 static void sdma_desc_free(struct virt_dma_desc *vd) 1224 { 1225 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd); 1226 1227 sdma_free_bd(desc); 1228 kfree(desc); 1229 } 1230 1231 static int sdma_alloc_chan_resources(struct dma_chan *chan) 1232 { 1233 struct sdma_channel *sdmac = to_sdma_chan(chan); 1234 struct imx_dma_data *data = chan->private; 1235 struct imx_dma_data mem_data; 1236 int prio, ret; 1237 1238 /* 1239 * MEMCPY may never setup chan->private by filter function such as 1240 * dmatest, thus create 'struct imx_dma_data mem_data' for this case. 1241 * Please note in any other slave case, you have to setup chan->private 1242 * with 'struct imx_dma_data' in your own filter function if you want to 1243 * request dma channel by dma_request_channel() rather than 1244 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear 1245 * to warn you to correct your filter function. 1246 */ 1247 if (!data) { 1248 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); 1249 mem_data.priority = 2; 1250 mem_data.peripheral_type = IMX_DMATYPE_MEMORY; 1251 mem_data.dma_request = 0; 1252 mem_data.dma_request2 = 0; 1253 data = &mem_data; 1254 1255 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); 1256 } 1257 1258 switch (data->priority) { 1259 case DMA_PRIO_HIGH: 1260 prio = 3; 1261 break; 1262 case DMA_PRIO_MEDIUM: 1263 prio = 2; 1264 break; 1265 case DMA_PRIO_LOW: 1266 default: 1267 prio = 1; 1268 break; 1269 } 1270 1271 sdmac->peripheral_type = data->peripheral_type; 1272 sdmac->event_id0 = data->dma_request; 1273 sdmac->event_id1 = data->dma_request2; 1274 1275 ret = clk_enable(sdmac->sdma->clk_ipg); 1276 if (ret) 1277 return ret; 1278 ret = clk_enable(sdmac->sdma->clk_ahb); 1279 if (ret) 1280 goto disable_clk_ipg; 1281 1282 ret = sdma_set_channel_priority(sdmac, prio); 1283 if (ret) 1284 goto disable_clk_ahb; 1285 1286 return 0; 1287 1288 disable_clk_ahb: 1289 clk_disable(sdmac->sdma->clk_ahb); 1290 disable_clk_ipg: 1291 clk_disable(sdmac->sdma->clk_ipg); 1292 return ret; 1293 } 1294 1295 static void sdma_free_chan_resources(struct dma_chan *chan) 1296 { 1297 struct sdma_channel *sdmac = to_sdma_chan(chan); 1298 struct sdma_engine *sdma = sdmac->sdma; 1299 1300 sdma_terminate_all(chan); 1301 1302 sdma_channel_synchronize(chan); 1303 1304 sdma_event_disable(sdmac, sdmac->event_id0); 1305 if (sdmac->event_id1) 1306 sdma_event_disable(sdmac, sdmac->event_id1); 1307 1308 sdmac->event_id0 = 0; 1309 sdmac->event_id1 = 0; 1310 sdmac->context_loaded = false; 1311 1312 sdma_set_channel_priority(sdmac, 0); 1313 1314 clk_disable(sdma->clk_ipg); 1315 clk_disable(sdma->clk_ahb); 1316 } 1317 1318 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, 1319 enum dma_transfer_direction direction, u32 bds) 1320 { 1321 struct sdma_desc *desc; 1322 1323 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); 1324 if (!desc) 1325 goto err_out; 1326 1327 sdmac->status = DMA_IN_PROGRESS; 1328 sdmac->direction = direction; 1329 sdmac->flags = 0; 1330 1331 desc->chn_count = 0; 1332 desc->chn_real_count = 0; 1333 desc->buf_tail = 0; 1334 desc->buf_ptail = 0; 1335 desc->sdmac = sdmac; 1336 desc->num_bd = bds; 1337 1338 if (sdma_alloc_bd(desc)) 1339 goto err_desc_out; 1340 1341 /* No slave_config called in MEMCPY case, so do here */ 1342 if (direction == DMA_MEM_TO_MEM) 1343 sdma_config_ownership(sdmac, false, true, false); 1344 1345 if (sdma_load_context(sdmac)) 1346 goto err_desc_out; 1347 1348 return desc; 1349 1350 err_desc_out: 1351 kfree(desc); 1352 err_out: 1353 return NULL; 1354 } 1355 1356 static struct dma_async_tx_descriptor *sdma_prep_memcpy( 1357 struct dma_chan *chan, dma_addr_t dma_dst, 1358 dma_addr_t dma_src, size_t len, unsigned long flags) 1359 { 1360 struct sdma_channel *sdmac = to_sdma_chan(chan); 1361 struct sdma_engine *sdma = sdmac->sdma; 1362 int channel = sdmac->channel; 1363 size_t count; 1364 int i = 0, param; 1365 struct sdma_buffer_descriptor *bd; 1366 struct sdma_desc *desc; 1367 1368 if (!chan || !len) 1369 return NULL; 1370 1371 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", 1372 &dma_src, &dma_dst, len, channel); 1373 1374 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, 1375 len / SDMA_BD_MAX_CNT + 1); 1376 if (!desc) 1377 return NULL; 1378 1379 do { 1380 count = min_t(size_t, len, SDMA_BD_MAX_CNT); 1381 bd = &desc->bd[i]; 1382 bd->buffer_addr = dma_src; 1383 bd->ext_buffer_addr = dma_dst; 1384 bd->mode.count = count; 1385 desc->chn_count += count; 1386 bd->mode.command = 0; 1387 1388 dma_src += count; 1389 dma_dst += count; 1390 len -= count; 1391 i++; 1392 1393 param = BD_DONE | BD_EXTD | BD_CONT; 1394 /* last bd */ 1395 if (!len) { 1396 param |= BD_INTR; 1397 param |= BD_LAST; 1398 param &= ~BD_CONT; 1399 } 1400 1401 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", 1402 i, count, bd->buffer_addr, 1403 param & BD_WRAP ? "wrap" : "", 1404 param & BD_INTR ? " intr" : ""); 1405 1406 bd->mode.status = param; 1407 } while (len); 1408 1409 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1410 } 1411 1412 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1413 struct dma_chan *chan, struct scatterlist *sgl, 1414 unsigned int sg_len, enum dma_transfer_direction direction, 1415 unsigned long flags, void *context) 1416 { 1417 struct sdma_channel *sdmac = to_sdma_chan(chan); 1418 struct sdma_engine *sdma = sdmac->sdma; 1419 int i, count; 1420 int channel = sdmac->channel; 1421 struct scatterlist *sg; 1422 struct sdma_desc *desc; 1423 1424 sdma_config_write(chan, &sdmac->slave_config, direction); 1425 1426 desc = sdma_transfer_init(sdmac, direction, sg_len); 1427 if (!desc) 1428 goto err_out; 1429 1430 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1431 sg_len, channel); 1432 1433 for_each_sg(sgl, sg, sg_len, i) { 1434 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1435 int param; 1436 1437 bd->buffer_addr = sg->dma_address; 1438 1439 count = sg_dma_len(sg); 1440 1441 if (count > SDMA_BD_MAX_CNT) { 1442 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1443 channel, count, SDMA_BD_MAX_CNT); 1444 goto err_bd_out; 1445 } 1446 1447 bd->mode.count = count; 1448 desc->chn_count += count; 1449 1450 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1451 goto err_bd_out; 1452 1453 switch (sdmac->word_size) { 1454 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1455 bd->mode.command = 0; 1456 if (count & 3 || sg->dma_address & 3) 1457 goto err_bd_out; 1458 break; 1459 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1460 bd->mode.command = 2; 1461 if (count & 1 || sg->dma_address & 1) 1462 goto err_bd_out; 1463 break; 1464 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1465 bd->mode.command = 1; 1466 break; 1467 default: 1468 goto err_bd_out; 1469 } 1470 1471 param = BD_DONE | BD_EXTD | BD_CONT; 1472 1473 if (i + 1 == sg_len) { 1474 param |= BD_INTR; 1475 param |= BD_LAST; 1476 param &= ~BD_CONT; 1477 } 1478 1479 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1480 i, count, (u64)sg->dma_address, 1481 param & BD_WRAP ? "wrap" : "", 1482 param & BD_INTR ? " intr" : ""); 1483 1484 bd->mode.status = param; 1485 } 1486 1487 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1488 err_bd_out: 1489 sdma_free_bd(desc); 1490 kfree(desc); 1491 err_out: 1492 sdmac->status = DMA_ERROR; 1493 return NULL; 1494 } 1495 1496 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1497 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1498 size_t period_len, enum dma_transfer_direction direction, 1499 unsigned long flags) 1500 { 1501 struct sdma_channel *sdmac = to_sdma_chan(chan); 1502 struct sdma_engine *sdma = sdmac->sdma; 1503 int num_periods = buf_len / period_len; 1504 int channel = sdmac->channel; 1505 int i = 0, buf = 0; 1506 struct sdma_desc *desc; 1507 1508 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1509 1510 sdma_config_write(chan, &sdmac->slave_config, direction); 1511 1512 desc = sdma_transfer_init(sdmac, direction, num_periods); 1513 if (!desc) 1514 goto err_out; 1515 1516 desc->period_len = period_len; 1517 1518 sdmac->flags |= IMX_DMA_SG_LOOP; 1519 1520 if (period_len > SDMA_BD_MAX_CNT) { 1521 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", 1522 channel, period_len, SDMA_BD_MAX_CNT); 1523 goto err_bd_out; 1524 } 1525 1526 while (buf < buf_len) { 1527 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1528 int param; 1529 1530 bd->buffer_addr = dma_addr; 1531 1532 bd->mode.count = period_len; 1533 1534 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1535 goto err_bd_out; 1536 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1537 bd->mode.command = 0; 1538 else 1539 bd->mode.command = sdmac->word_size; 1540 1541 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1542 if (i + 1 == num_periods) 1543 param |= BD_WRAP; 1544 1545 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", 1546 i, period_len, (u64)dma_addr, 1547 param & BD_WRAP ? "wrap" : "", 1548 param & BD_INTR ? " intr" : ""); 1549 1550 bd->mode.status = param; 1551 1552 dma_addr += period_len; 1553 buf += period_len; 1554 1555 i++; 1556 } 1557 1558 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1559 err_bd_out: 1560 sdma_free_bd(desc); 1561 kfree(desc); 1562 err_out: 1563 sdmac->status = DMA_ERROR; 1564 return NULL; 1565 } 1566 1567 static int sdma_config_write(struct dma_chan *chan, 1568 struct dma_slave_config *dmaengine_cfg, 1569 enum dma_transfer_direction direction) 1570 { 1571 struct sdma_channel *sdmac = to_sdma_chan(chan); 1572 1573 if (direction == DMA_DEV_TO_MEM) { 1574 sdmac->per_address = dmaengine_cfg->src_addr; 1575 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1576 dmaengine_cfg->src_addr_width; 1577 sdmac->word_size = dmaengine_cfg->src_addr_width; 1578 } else if (direction == DMA_DEV_TO_DEV) { 1579 sdmac->per_address2 = dmaengine_cfg->src_addr; 1580 sdmac->per_address = dmaengine_cfg->dst_addr; 1581 sdmac->watermark_level = dmaengine_cfg->src_maxburst & 1582 SDMA_WATERMARK_LEVEL_LWML; 1583 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & 1584 SDMA_WATERMARK_LEVEL_HWML; 1585 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1586 } else { 1587 sdmac->per_address = dmaengine_cfg->dst_addr; 1588 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1589 dmaengine_cfg->dst_addr_width; 1590 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1591 } 1592 sdmac->direction = direction; 1593 return sdma_config_channel(chan); 1594 } 1595 1596 static int sdma_config(struct dma_chan *chan, 1597 struct dma_slave_config *dmaengine_cfg) 1598 { 1599 struct sdma_channel *sdmac = to_sdma_chan(chan); 1600 1601 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); 1602 1603 /* Set ENBLn earlier to make sure dma request triggered after that */ 1604 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 1605 return -EINVAL; 1606 sdma_event_enable(sdmac, sdmac->event_id0); 1607 1608 if (sdmac->event_id1) { 1609 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) 1610 return -EINVAL; 1611 sdma_event_enable(sdmac, sdmac->event_id1); 1612 } 1613 1614 return 0; 1615 } 1616 1617 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1618 dma_cookie_t cookie, 1619 struct dma_tx_state *txstate) 1620 { 1621 struct sdma_channel *sdmac = to_sdma_chan(chan); 1622 struct sdma_desc *desc = NULL; 1623 u32 residue; 1624 struct virt_dma_desc *vd; 1625 enum dma_status ret; 1626 unsigned long flags; 1627 1628 ret = dma_cookie_status(chan, cookie, txstate); 1629 if (ret == DMA_COMPLETE || !txstate) 1630 return ret; 1631 1632 spin_lock_irqsave(&sdmac->vc.lock, flags); 1633 1634 vd = vchan_find_desc(&sdmac->vc, cookie); 1635 if (vd) 1636 desc = to_sdma_desc(&vd->tx); 1637 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) 1638 desc = sdmac->desc; 1639 1640 if (desc) { 1641 if (sdmac->flags & IMX_DMA_SG_LOOP) 1642 residue = (desc->num_bd - desc->buf_ptail) * 1643 desc->period_len - desc->chn_real_count; 1644 else 1645 residue = desc->chn_count - desc->chn_real_count; 1646 } else { 1647 residue = 0; 1648 } 1649 1650 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1651 1652 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1653 residue); 1654 1655 return sdmac->status; 1656 } 1657 1658 static void sdma_issue_pending(struct dma_chan *chan) 1659 { 1660 struct sdma_channel *sdmac = to_sdma_chan(chan); 1661 unsigned long flags; 1662 1663 spin_lock_irqsave(&sdmac->vc.lock, flags); 1664 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) 1665 sdma_start_desc(sdmac); 1666 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1667 } 1668 1669 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1670 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1671 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 1672 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 1673 1674 static void sdma_add_scripts(struct sdma_engine *sdma, 1675 const struct sdma_script_start_addrs *addr) 1676 { 1677 s32 *addr_arr = (u32 *)addr; 1678 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1679 int i; 1680 1681 /* use the default firmware in ROM if missing external firmware */ 1682 if (!sdma->script_number) 1683 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1684 1685 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) 1686 / sizeof(s32)) { 1687 dev_err(sdma->dev, 1688 "SDMA script number %d not match with firmware.\n", 1689 sdma->script_number); 1690 return; 1691 } 1692 1693 for (i = 0; i < sdma->script_number; i++) 1694 if (addr_arr[i] > 0) 1695 saddr_arr[i] = addr_arr[i]; 1696 } 1697 1698 static void sdma_load_firmware(const struct firmware *fw, void *context) 1699 { 1700 struct sdma_engine *sdma = context; 1701 const struct sdma_firmware_header *header; 1702 const struct sdma_script_start_addrs *addr; 1703 unsigned short *ram_code; 1704 1705 if (!fw) { 1706 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); 1707 /* In this case we just use the ROM firmware. */ 1708 return; 1709 } 1710 1711 if (fw->size < sizeof(*header)) 1712 goto err_firmware; 1713 1714 header = (struct sdma_firmware_header *)fw->data; 1715 1716 if (header->magic != SDMA_FIRMWARE_MAGIC) 1717 goto err_firmware; 1718 if (header->ram_code_start + header->ram_code_size > fw->size) 1719 goto err_firmware; 1720 switch (header->version_major) { 1721 case 1: 1722 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1723 break; 1724 case 2: 1725 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1726 break; 1727 case 3: 1728 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; 1729 break; 1730 case 4: 1731 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; 1732 break; 1733 default: 1734 dev_err(sdma->dev, "unknown firmware version\n"); 1735 goto err_firmware; 1736 } 1737 1738 addr = (void *)header + header->script_addrs_start; 1739 ram_code = (void *)header + header->ram_code_start; 1740 1741 clk_enable(sdma->clk_ipg); 1742 clk_enable(sdma->clk_ahb); 1743 /* download the RAM image for SDMA */ 1744 sdma_load_script(sdma, ram_code, 1745 header->ram_code_size, 1746 addr->ram_code_start_addr); 1747 clk_disable(sdma->clk_ipg); 1748 clk_disable(sdma->clk_ahb); 1749 1750 sdma_add_scripts(sdma, addr); 1751 1752 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1753 header->version_major, 1754 header->version_minor); 1755 1756 err_firmware: 1757 release_firmware(fw); 1758 } 1759 1760 #define EVENT_REMAP_CELLS 3 1761 1762 static int sdma_event_remap(struct sdma_engine *sdma) 1763 { 1764 struct device_node *np = sdma->dev->of_node; 1765 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); 1766 struct property *event_remap; 1767 struct regmap *gpr; 1768 char propname[] = "fsl,sdma-event-remap"; 1769 u32 reg, val, shift, num_map, i; 1770 int ret = 0; 1771 1772 if (IS_ERR(np) || IS_ERR(gpr_np)) 1773 goto out; 1774 1775 event_remap = of_find_property(np, propname, NULL); 1776 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; 1777 if (!num_map) { 1778 dev_dbg(sdma->dev, "no event needs to be remapped\n"); 1779 goto out; 1780 } else if (num_map % EVENT_REMAP_CELLS) { 1781 dev_err(sdma->dev, "the property %s must modulo %d\n", 1782 propname, EVENT_REMAP_CELLS); 1783 ret = -EINVAL; 1784 goto out; 1785 } 1786 1787 gpr = syscon_node_to_regmap(gpr_np); 1788 if (IS_ERR(gpr)) { 1789 dev_err(sdma->dev, "failed to get gpr regmap\n"); 1790 ret = PTR_ERR(gpr); 1791 goto out; 1792 } 1793 1794 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { 1795 ret = of_property_read_u32_index(np, propname, i, ®); 1796 if (ret) { 1797 dev_err(sdma->dev, "failed to read property %s index %d\n", 1798 propname, i); 1799 goto out; 1800 } 1801 1802 ret = of_property_read_u32_index(np, propname, i + 1, &shift); 1803 if (ret) { 1804 dev_err(sdma->dev, "failed to read property %s index %d\n", 1805 propname, i + 1); 1806 goto out; 1807 } 1808 1809 ret = of_property_read_u32_index(np, propname, i + 2, &val); 1810 if (ret) { 1811 dev_err(sdma->dev, "failed to read property %s index %d\n", 1812 propname, i + 2); 1813 goto out; 1814 } 1815 1816 regmap_update_bits(gpr, reg, BIT(shift), val << shift); 1817 } 1818 1819 out: 1820 if (!IS_ERR(gpr_np)) 1821 of_node_put(gpr_np); 1822 1823 return ret; 1824 } 1825 1826 static int sdma_get_firmware(struct sdma_engine *sdma, 1827 const char *fw_name) 1828 { 1829 int ret; 1830 1831 ret = request_firmware_nowait(THIS_MODULE, 1832 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1833 GFP_KERNEL, sdma, sdma_load_firmware); 1834 1835 return ret; 1836 } 1837 1838 static int sdma_init(struct sdma_engine *sdma) 1839 { 1840 int i, ret; 1841 dma_addr_t ccb_phys; 1842 1843 ret = clk_enable(sdma->clk_ipg); 1844 if (ret) 1845 return ret; 1846 ret = clk_enable(sdma->clk_ahb); 1847 if (ret) 1848 goto disable_clk_ipg; 1849 1850 if (sdma->drvdata->check_ratio && 1851 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) 1852 sdma->clk_ratio = 1; 1853 1854 /* Be sure SDMA has not started yet */ 1855 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1856 1857 sdma->channel_control = dma_alloc_coherent(sdma->dev, 1858 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1859 sizeof(struct sdma_context_data), 1860 &ccb_phys, GFP_KERNEL); 1861 1862 if (!sdma->channel_control) { 1863 ret = -ENOMEM; 1864 goto err_dma_alloc; 1865 } 1866 1867 sdma->context = (void *)sdma->channel_control + 1868 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1869 sdma->context_phys = ccb_phys + 1870 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1871 1872 /* disable all channels */ 1873 for (i = 0; i < sdma->drvdata->num_events; i++) 1874 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1875 1876 /* All channels have priority 0 */ 1877 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1878 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1879 1880 ret = sdma_request_channel0(sdma); 1881 if (ret) 1882 goto err_dma_alloc; 1883 1884 sdma_config_ownership(&sdma->channel[0], false, true, false); 1885 1886 /* Set Command Channel (Channel Zero) */ 1887 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1888 1889 /* Set bits of CONFIG register but with static context switching */ 1890 if (sdma->clk_ratio) 1891 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); 1892 else 1893 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1894 1895 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1896 1897 /* Initializes channel's priorities */ 1898 sdma_set_channel_priority(&sdma->channel[0], 7); 1899 1900 clk_disable(sdma->clk_ipg); 1901 clk_disable(sdma->clk_ahb); 1902 1903 return 0; 1904 1905 err_dma_alloc: 1906 clk_disable(sdma->clk_ahb); 1907 disable_clk_ipg: 1908 clk_disable(sdma->clk_ipg); 1909 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1910 return ret; 1911 } 1912 1913 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1914 { 1915 struct sdma_channel *sdmac = to_sdma_chan(chan); 1916 struct imx_dma_data *data = fn_param; 1917 1918 if (!imx_dma_is_general_purpose(chan)) 1919 return false; 1920 1921 sdmac->data = *data; 1922 chan->private = &sdmac->data; 1923 1924 return true; 1925 } 1926 1927 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1928 struct of_dma *ofdma) 1929 { 1930 struct sdma_engine *sdma = ofdma->of_dma_data; 1931 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1932 struct imx_dma_data data; 1933 1934 if (dma_spec->args_count != 3) 1935 return NULL; 1936 1937 data.dma_request = dma_spec->args[0]; 1938 data.peripheral_type = dma_spec->args[1]; 1939 data.priority = dma_spec->args[2]; 1940 /* 1941 * init dma_request2 to zero, which is not used by the dts. 1942 * For P2P, dma_request2 is init from dma_request_channel(), 1943 * chan->private will point to the imx_dma_data, and in 1944 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will 1945 * be set to sdmac->event_id1. 1946 */ 1947 data.dma_request2 = 0; 1948 1949 return __dma_request_channel(&mask, sdma_filter_fn, &data, 1950 ofdma->of_node); 1951 } 1952 1953 static int sdma_probe(struct platform_device *pdev) 1954 { 1955 const struct of_device_id *of_id = 1956 of_match_device(sdma_dt_ids, &pdev->dev); 1957 struct device_node *np = pdev->dev.of_node; 1958 struct device_node *spba_bus; 1959 const char *fw_name; 1960 int ret; 1961 int irq; 1962 struct resource *iores; 1963 struct resource spba_res; 1964 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1965 int i; 1966 struct sdma_engine *sdma; 1967 s32 *saddr_arr; 1968 const struct sdma_driver_data *drvdata = NULL; 1969 1970 drvdata = of_id->data; 1971 if (!drvdata) { 1972 dev_err(&pdev->dev, "unable to find driver data\n"); 1973 return -EINVAL; 1974 } 1975 1976 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1977 if (ret) 1978 return ret; 1979 1980 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); 1981 if (!sdma) 1982 return -ENOMEM; 1983 1984 spin_lock_init(&sdma->channel_0_lock); 1985 1986 sdma->dev = &pdev->dev; 1987 sdma->drvdata = drvdata; 1988 1989 irq = platform_get_irq(pdev, 0); 1990 if (irq < 0) 1991 return irq; 1992 1993 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1994 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); 1995 if (IS_ERR(sdma->regs)) 1996 return PTR_ERR(sdma->regs); 1997 1998 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1999 if (IS_ERR(sdma->clk_ipg)) 2000 return PTR_ERR(sdma->clk_ipg); 2001 2002 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2003 if (IS_ERR(sdma->clk_ahb)) 2004 return PTR_ERR(sdma->clk_ahb); 2005 2006 ret = clk_prepare(sdma->clk_ipg); 2007 if (ret) 2008 return ret; 2009 2010 ret = clk_prepare(sdma->clk_ahb); 2011 if (ret) 2012 goto err_clk; 2013 2014 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", 2015 sdma); 2016 if (ret) 2017 goto err_irq; 2018 2019 sdma->irq = irq; 2020 2021 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 2022 if (!sdma->script_addrs) { 2023 ret = -ENOMEM; 2024 goto err_irq; 2025 } 2026 2027 /* initially no scripts available */ 2028 saddr_arr = (s32 *)sdma->script_addrs; 2029 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) 2030 saddr_arr[i] = -EINVAL; 2031 2032 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 2033 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 2034 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); 2035 2036 INIT_LIST_HEAD(&sdma->dma_device.channels); 2037 /* Initialize channel parameters */ 2038 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2039 struct sdma_channel *sdmac = &sdma->channel[i]; 2040 2041 sdmac->sdma = sdma; 2042 2043 sdmac->channel = i; 2044 sdmac->vc.desc_free = sdma_desc_free; 2045 INIT_WORK(&sdmac->terminate_worker, 2046 sdma_channel_terminate_work); 2047 /* 2048 * Add the channel to the DMAC list. Do not add channel 0 though 2049 * because we need it internally in the SDMA driver. This also means 2050 * that channel 0 in dmaengine counting matches sdma channel 1. 2051 */ 2052 if (i) 2053 vchan_init(&sdmac->vc, &sdma->dma_device); 2054 } 2055 2056 ret = sdma_init(sdma); 2057 if (ret) 2058 goto err_init; 2059 2060 ret = sdma_event_remap(sdma); 2061 if (ret) 2062 goto err_init; 2063 2064 if (sdma->drvdata->script_addrs) 2065 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 2066 if (pdata && pdata->script_addrs) 2067 sdma_add_scripts(sdma, pdata->script_addrs); 2068 2069 sdma->dma_device.dev = &pdev->dev; 2070 2071 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 2072 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 2073 sdma->dma_device.device_tx_status = sdma_tx_status; 2074 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 2075 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 2076 sdma->dma_device.device_config = sdma_config; 2077 sdma->dma_device.device_terminate_all = sdma_terminate_all; 2078 sdma->dma_device.device_synchronize = sdma_channel_synchronize; 2079 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; 2080 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; 2081 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; 2082 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2083 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; 2084 sdma->dma_device.device_issue_pending = sdma_issue_pending; 2085 sdma->dma_device.copy_align = 2; 2086 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); 2087 2088 platform_set_drvdata(pdev, sdma); 2089 2090 ret = dma_async_device_register(&sdma->dma_device); 2091 if (ret) { 2092 dev_err(&pdev->dev, "unable to register\n"); 2093 goto err_init; 2094 } 2095 2096 if (np) { 2097 ret = of_dma_controller_register(np, sdma_xlate, sdma); 2098 if (ret) { 2099 dev_err(&pdev->dev, "failed to register controller\n"); 2100 goto err_register; 2101 } 2102 2103 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); 2104 ret = of_address_to_resource(spba_bus, 0, &spba_res); 2105 if (!ret) { 2106 sdma->spba_start_addr = spba_res.start; 2107 sdma->spba_end_addr = spba_res.end; 2108 } 2109 of_node_put(spba_bus); 2110 } 2111 2112 /* 2113 * Kick off firmware loading as the very last step: 2114 * attempt to load firmware only if we're not on the error path, because 2115 * the firmware callback requires a fully functional and allocated sdma 2116 * instance. 2117 */ 2118 if (pdata) { 2119 ret = sdma_get_firmware(sdma, pdata->fw_name); 2120 if (ret) 2121 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 2122 } else { 2123 /* 2124 * Because that device tree does not encode ROM script address, 2125 * the RAM script in firmware is mandatory for device tree 2126 * probe, otherwise it fails. 2127 */ 2128 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 2129 &fw_name); 2130 if (ret) { 2131 dev_warn(&pdev->dev, "failed to get firmware name\n"); 2132 } else { 2133 ret = sdma_get_firmware(sdma, fw_name); 2134 if (ret) 2135 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 2136 } 2137 } 2138 2139 return 0; 2140 2141 err_register: 2142 dma_async_device_unregister(&sdma->dma_device); 2143 err_init: 2144 kfree(sdma->script_addrs); 2145 err_irq: 2146 clk_unprepare(sdma->clk_ahb); 2147 err_clk: 2148 clk_unprepare(sdma->clk_ipg); 2149 return ret; 2150 } 2151 2152 static int sdma_remove(struct platform_device *pdev) 2153 { 2154 struct sdma_engine *sdma = platform_get_drvdata(pdev); 2155 int i; 2156 2157 devm_free_irq(&pdev->dev, sdma->irq, sdma); 2158 dma_async_device_unregister(&sdma->dma_device); 2159 kfree(sdma->script_addrs); 2160 clk_unprepare(sdma->clk_ahb); 2161 clk_unprepare(sdma->clk_ipg); 2162 /* Kill the tasklet */ 2163 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2164 struct sdma_channel *sdmac = &sdma->channel[i]; 2165 2166 tasklet_kill(&sdmac->vc.task); 2167 sdma_free_chan_resources(&sdmac->vc.chan); 2168 } 2169 2170 platform_set_drvdata(pdev, NULL); 2171 return 0; 2172 } 2173 2174 static struct platform_driver sdma_driver = { 2175 .driver = { 2176 .name = "imx-sdma", 2177 .of_match_table = sdma_dt_ids, 2178 }, 2179 .remove = sdma_remove, 2180 .probe = sdma_probe, 2181 }; 2182 2183 module_platform_driver(sdma_driver); 2184 2185 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 2186 MODULE_DESCRIPTION("i.MX SDMA driver"); 2187 #if IS_ENABLED(CONFIG_SOC_IMX6Q) 2188 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin"); 2189 #endif 2190 #if IS_ENABLED(CONFIG_SOC_IMX7D) 2191 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin"); 2192 #endif 2193 MODULE_LICENSE("GPL"); 2194