1 /* 2 * drivers/dma/imx-sdma.c 3 * 4 * This file contains a driver for the Freescale Smart DMA engine 5 * 6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 7 * 8 * Based on code from Freescale: 9 * 10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 11 * 12 * The code contained herein is licensed under the GNU General Public 13 * License. You may obtain a copy of the GNU General Public License 14 * Version 2 or later at the following locations: 15 * 16 * http://www.opensource.org/licenses/gpl-license.html 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/init.h> 21 #include <linux/iopoll.h> 22 #include <linux/module.h> 23 #include <linux/types.h> 24 #include <linux/bitops.h> 25 #include <linux/mm.h> 26 #include <linux/interrupt.h> 27 #include <linux/clk.h> 28 #include <linux/delay.h> 29 #include <linux/sched.h> 30 #include <linux/semaphore.h> 31 #include <linux/spinlock.h> 32 #include <linux/device.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/firmware.h> 35 #include <linux/slab.h> 36 #include <linux/platform_device.h> 37 #include <linux/dmaengine.h> 38 #include <linux/of.h> 39 #include <linux/of_address.h> 40 #include <linux/of_device.h> 41 #include <linux/of_dma.h> 42 43 #include <asm/irq.h> 44 #include <linux/platform_data/dma-imx-sdma.h> 45 #include <linux/platform_data/dma-imx.h> 46 #include <linux/regmap.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 49 50 #include "dmaengine.h" 51 52 /* SDMA registers */ 53 #define SDMA_H_C0PTR 0x000 54 #define SDMA_H_INTR 0x004 55 #define SDMA_H_STATSTOP 0x008 56 #define SDMA_H_START 0x00c 57 #define SDMA_H_EVTOVR 0x010 58 #define SDMA_H_DSPOVR 0x014 59 #define SDMA_H_HOSTOVR 0x018 60 #define SDMA_H_EVTPEND 0x01c 61 #define SDMA_H_DSPENBL 0x020 62 #define SDMA_H_RESET 0x024 63 #define SDMA_H_EVTERR 0x028 64 #define SDMA_H_INTRMSK 0x02c 65 #define SDMA_H_PSW 0x030 66 #define SDMA_H_EVTERRDBG 0x034 67 #define SDMA_H_CONFIG 0x038 68 #define SDMA_ONCE_ENB 0x040 69 #define SDMA_ONCE_DATA 0x044 70 #define SDMA_ONCE_INSTR 0x048 71 #define SDMA_ONCE_STAT 0x04c 72 #define SDMA_ONCE_CMD 0x050 73 #define SDMA_EVT_MIRROR 0x054 74 #define SDMA_ILLINSTADDR 0x058 75 #define SDMA_CHN0ADDR 0x05c 76 #define SDMA_ONCE_RTB 0x060 77 #define SDMA_XTRIG_CONF1 0x070 78 #define SDMA_XTRIG_CONF2 0x074 79 #define SDMA_CHNENBL0_IMX35 0x200 80 #define SDMA_CHNENBL0_IMX31 0x080 81 #define SDMA_CHNPRI_0 0x100 82 83 /* 84 * Buffer descriptor status values. 85 */ 86 #define BD_DONE 0x01 87 #define BD_WRAP 0x02 88 #define BD_CONT 0x04 89 #define BD_INTR 0x08 90 #define BD_RROR 0x10 91 #define BD_LAST 0x20 92 #define BD_EXTD 0x80 93 94 /* 95 * Data Node descriptor status values. 96 */ 97 #define DND_END_OF_FRAME 0x80 98 #define DND_END_OF_XFER 0x40 99 #define DND_DONE 0x20 100 #define DND_UNUSED 0x01 101 102 /* 103 * IPCV2 descriptor status values. 104 */ 105 #define BD_IPCV2_END_OF_FRAME 0x40 106 107 #define IPCV2_MAX_NODES 50 108 /* 109 * Error bit set in the CCB status field by the SDMA, 110 * in setbd routine, in case of a transfer error 111 */ 112 #define DATA_ERROR 0x10000000 113 114 /* 115 * Buffer descriptor commands. 116 */ 117 #define C0_ADDR 0x01 118 #define C0_LOAD 0x02 119 #define C0_DUMP 0x03 120 #define C0_SETCTX 0x07 121 #define C0_GETCTX 0x03 122 #define C0_SETDM 0x01 123 #define C0_SETPM 0x04 124 #define C0_GETDM 0x02 125 #define C0_GETPM 0x08 126 /* 127 * Change endianness indicator in the BD command field 128 */ 129 #define CHANGE_ENDIANNESS 0x80 130 131 /* 132 * p_2_p watermark_level description 133 * Bits Name Description 134 * 0-7 Lower WML Lower watermark level 135 * 8 PS 1: Pad Swallowing 136 * 0: No Pad Swallowing 137 * 9 PA 1: Pad Adding 138 * 0: No Pad Adding 139 * 10 SPDIF If this bit is set both source 140 * and destination are on SPBA 141 * 11 Source Bit(SP) 1: Source on SPBA 142 * 0: Source on AIPS 143 * 12 Destination Bit(DP) 1: Destination on SPBA 144 * 0: Destination on AIPS 145 * 13-15 --------- MUST BE 0 146 * 16-23 Higher WML HWML 147 * 24-27 N Total number of samples after 148 * which Pad adding/Swallowing 149 * must be done. It must be odd. 150 * 28 Lower WML Event(LWE) SDMA events reg to check for 151 * LWML event mask 152 * 0: LWE in EVENTS register 153 * 1: LWE in EVENTS2 register 154 * 29 Higher WML Event(HWE) SDMA events reg to check for 155 * HWML event mask 156 * 0: HWE in EVENTS register 157 * 1: HWE in EVENTS2 register 158 * 30 --------- MUST BE 0 159 * 31 CONT 1: Amount of samples to be 160 * transferred is unknown and 161 * script will keep on 162 * transferring samples as long as 163 * both events are detected and 164 * script must be manually stopped 165 * by the application 166 * 0: The amount of samples to be 167 * transferred is equal to the 168 * count field of mode word 169 */ 170 #define SDMA_WATERMARK_LEVEL_LWML 0xFF 171 #define SDMA_WATERMARK_LEVEL_PS BIT(8) 172 #define SDMA_WATERMARK_LEVEL_PA BIT(9) 173 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) 174 #define SDMA_WATERMARK_LEVEL_SP BIT(11) 175 #define SDMA_WATERMARK_LEVEL_DP BIT(12) 176 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) 177 #define SDMA_WATERMARK_LEVEL_LWE BIT(28) 178 #define SDMA_WATERMARK_LEVEL_HWE BIT(29) 179 #define SDMA_WATERMARK_LEVEL_CONT BIT(31) 180 181 /* 182 * Mode/Count of data node descriptors - IPCv2 183 */ 184 struct sdma_mode_count { 185 u32 count : 16; /* size of the buffer pointed by this BD */ 186 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 187 u32 command : 8; /* command mostlky used for channel 0 */ 188 }; 189 190 /* 191 * Buffer descriptor 192 */ 193 struct sdma_buffer_descriptor { 194 struct sdma_mode_count mode; 195 u32 buffer_addr; /* address of the buffer described */ 196 u32 ext_buffer_addr; /* extended buffer address */ 197 } __attribute__ ((packed)); 198 199 /** 200 * struct sdma_channel_control - Channel control Block 201 * 202 * @current_bd_ptr current buffer descriptor processed 203 * @base_bd_ptr first element of buffer descriptor array 204 * @unused padding. The SDMA engine expects an array of 128 byte 205 * control blocks 206 */ 207 struct sdma_channel_control { 208 u32 current_bd_ptr; 209 u32 base_bd_ptr; 210 u32 unused[2]; 211 } __attribute__ ((packed)); 212 213 /** 214 * struct sdma_state_registers - SDMA context for a channel 215 * 216 * @pc: program counter 217 * @t: test bit: status of arithmetic & test instruction 218 * @rpc: return program counter 219 * @sf: source fault while loading data 220 * @spc: loop start program counter 221 * @df: destination fault while storing data 222 * @epc: loop end program counter 223 * @lm: loop mode 224 */ 225 struct sdma_state_registers { 226 u32 pc :14; 227 u32 unused1: 1; 228 u32 t : 1; 229 u32 rpc :14; 230 u32 unused0: 1; 231 u32 sf : 1; 232 u32 spc :14; 233 u32 unused2: 1; 234 u32 df : 1; 235 u32 epc :14; 236 u32 lm : 2; 237 } __attribute__ ((packed)); 238 239 /** 240 * struct sdma_context_data - sdma context specific to a channel 241 * 242 * @channel_state: channel state bits 243 * @gReg: general registers 244 * @mda: burst dma destination address register 245 * @msa: burst dma source address register 246 * @ms: burst dma status register 247 * @md: burst dma data register 248 * @pda: peripheral dma destination address register 249 * @psa: peripheral dma source address register 250 * @ps: peripheral dma status register 251 * @pd: peripheral dma data register 252 * @ca: CRC polynomial register 253 * @cs: CRC accumulator register 254 * @dda: dedicated core destination address register 255 * @dsa: dedicated core source address register 256 * @ds: dedicated core status register 257 * @dd: dedicated core data register 258 */ 259 struct sdma_context_data { 260 struct sdma_state_registers channel_state; 261 u32 gReg[8]; 262 u32 mda; 263 u32 msa; 264 u32 ms; 265 u32 md; 266 u32 pda; 267 u32 psa; 268 u32 ps; 269 u32 pd; 270 u32 ca; 271 u32 cs; 272 u32 dda; 273 u32 dsa; 274 u32 ds; 275 u32 dd; 276 u32 scratch0; 277 u32 scratch1; 278 u32 scratch2; 279 u32 scratch3; 280 u32 scratch4; 281 u32 scratch5; 282 u32 scratch6; 283 u32 scratch7; 284 } __attribute__ ((packed)); 285 286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 287 288 struct sdma_engine; 289 290 /** 291 * struct sdma_channel - housekeeping for a SDMA channel 292 * 293 * @sdma pointer to the SDMA engine for this channel 294 * @channel the channel number, matches dmaengine chan_id + 1 295 * @direction transfer type. Needed for setting SDMA script 296 * @peripheral_type Peripheral type. Needed for setting SDMA script 297 * @event_id0 aka dma request line 298 * @event_id1 for channels that use 2 events 299 * @word_size peripheral access size 300 * @buf_tail ID of the buffer that was processed 301 * @num_bd max NUM_BD. number of descriptors currently handling 302 */ 303 struct sdma_channel { 304 struct sdma_engine *sdma; 305 unsigned int channel; 306 enum dma_transfer_direction direction; 307 enum sdma_peripheral_type peripheral_type; 308 unsigned int event_id0; 309 unsigned int event_id1; 310 enum dma_slave_buswidth word_size; 311 unsigned int buf_tail; 312 unsigned int num_bd; 313 unsigned int period_len; 314 struct sdma_buffer_descriptor *bd; 315 dma_addr_t bd_phys; 316 unsigned int pc_from_device, pc_to_device; 317 unsigned int device_to_device; 318 unsigned long flags; 319 dma_addr_t per_address, per_address2; 320 unsigned long event_mask[2]; 321 unsigned long watermark_level; 322 u32 shp_addr, per_addr; 323 struct dma_chan chan; 324 spinlock_t lock; 325 struct dma_async_tx_descriptor desc; 326 enum dma_status status; 327 unsigned int chn_count; 328 unsigned int chn_real_count; 329 struct tasklet_struct tasklet; 330 struct imx_dma_data data; 331 }; 332 333 #define IMX_DMA_SG_LOOP BIT(0) 334 335 #define MAX_DMA_CHANNELS 32 336 #define MXC_SDMA_DEFAULT_PRIORITY 1 337 #define MXC_SDMA_MIN_PRIORITY 1 338 #define MXC_SDMA_MAX_PRIORITY 7 339 340 #define SDMA_FIRMWARE_MAGIC 0x414d4453 341 342 /** 343 * struct sdma_firmware_header - Layout of the firmware image 344 * 345 * @magic "SDMA" 346 * @version_major increased whenever layout of struct sdma_script_start_addrs 347 * changes. 348 * @version_minor firmware minor version (for binary compatible changes) 349 * @script_addrs_start offset of struct sdma_script_start_addrs in this image 350 * @num_script_addrs Number of script addresses in this image 351 * @ram_code_start offset of SDMA ram image in this firmware image 352 * @ram_code_size size of SDMA ram image 353 * @script_addrs Stores the start address of the SDMA scripts 354 * (in SDMA memory space) 355 */ 356 struct sdma_firmware_header { 357 u32 magic; 358 u32 version_major; 359 u32 version_minor; 360 u32 script_addrs_start; 361 u32 num_script_addrs; 362 u32 ram_code_start; 363 u32 ram_code_size; 364 }; 365 366 struct sdma_driver_data { 367 int chnenbl0; 368 int num_events; 369 struct sdma_script_start_addrs *script_addrs; 370 }; 371 372 struct sdma_engine { 373 struct device *dev; 374 struct device_dma_parameters dma_parms; 375 struct sdma_channel channel[MAX_DMA_CHANNELS]; 376 struct sdma_channel_control *channel_control; 377 void __iomem *regs; 378 struct sdma_context_data *context; 379 dma_addr_t context_phys; 380 struct dma_device dma_device; 381 struct clk *clk_ipg; 382 struct clk *clk_ahb; 383 spinlock_t channel_0_lock; 384 u32 script_number; 385 struct sdma_script_start_addrs *script_addrs; 386 const struct sdma_driver_data *drvdata; 387 u32 spba_start_addr; 388 u32 spba_end_addr; 389 unsigned int irq; 390 }; 391 392 static struct sdma_driver_data sdma_imx31 = { 393 .chnenbl0 = SDMA_CHNENBL0_IMX31, 394 .num_events = 32, 395 }; 396 397 static struct sdma_script_start_addrs sdma_script_imx25 = { 398 .ap_2_ap_addr = 729, 399 .uart_2_mcu_addr = 904, 400 .per_2_app_addr = 1255, 401 .mcu_2_app_addr = 834, 402 .uartsh_2_mcu_addr = 1120, 403 .per_2_shp_addr = 1329, 404 .mcu_2_shp_addr = 1048, 405 .ata_2_mcu_addr = 1560, 406 .mcu_2_ata_addr = 1479, 407 .app_2_per_addr = 1189, 408 .app_2_mcu_addr = 770, 409 .shp_2_per_addr = 1407, 410 .shp_2_mcu_addr = 979, 411 }; 412 413 static struct sdma_driver_data sdma_imx25 = { 414 .chnenbl0 = SDMA_CHNENBL0_IMX35, 415 .num_events = 48, 416 .script_addrs = &sdma_script_imx25, 417 }; 418 419 static struct sdma_driver_data sdma_imx35 = { 420 .chnenbl0 = SDMA_CHNENBL0_IMX35, 421 .num_events = 48, 422 }; 423 424 static struct sdma_script_start_addrs sdma_script_imx51 = { 425 .ap_2_ap_addr = 642, 426 .uart_2_mcu_addr = 817, 427 .mcu_2_app_addr = 747, 428 .mcu_2_shp_addr = 961, 429 .ata_2_mcu_addr = 1473, 430 .mcu_2_ata_addr = 1392, 431 .app_2_per_addr = 1033, 432 .app_2_mcu_addr = 683, 433 .shp_2_per_addr = 1251, 434 .shp_2_mcu_addr = 892, 435 }; 436 437 static struct sdma_driver_data sdma_imx51 = { 438 .chnenbl0 = SDMA_CHNENBL0_IMX35, 439 .num_events = 48, 440 .script_addrs = &sdma_script_imx51, 441 }; 442 443 static struct sdma_script_start_addrs sdma_script_imx53 = { 444 .ap_2_ap_addr = 642, 445 .app_2_mcu_addr = 683, 446 .mcu_2_app_addr = 747, 447 .uart_2_mcu_addr = 817, 448 .shp_2_mcu_addr = 891, 449 .mcu_2_shp_addr = 960, 450 .uartsh_2_mcu_addr = 1032, 451 .spdif_2_mcu_addr = 1100, 452 .mcu_2_spdif_addr = 1134, 453 .firi_2_mcu_addr = 1193, 454 .mcu_2_firi_addr = 1290, 455 }; 456 457 static struct sdma_driver_data sdma_imx53 = { 458 .chnenbl0 = SDMA_CHNENBL0_IMX35, 459 .num_events = 48, 460 .script_addrs = &sdma_script_imx53, 461 }; 462 463 static struct sdma_script_start_addrs sdma_script_imx6q = { 464 .ap_2_ap_addr = 642, 465 .uart_2_mcu_addr = 817, 466 .mcu_2_app_addr = 747, 467 .per_2_per_addr = 6331, 468 .uartsh_2_mcu_addr = 1032, 469 .mcu_2_shp_addr = 960, 470 .app_2_mcu_addr = 683, 471 .shp_2_mcu_addr = 891, 472 .spdif_2_mcu_addr = 1100, 473 .mcu_2_spdif_addr = 1134, 474 }; 475 476 static struct sdma_driver_data sdma_imx6q = { 477 .chnenbl0 = SDMA_CHNENBL0_IMX35, 478 .num_events = 48, 479 .script_addrs = &sdma_script_imx6q, 480 }; 481 482 static const struct platform_device_id sdma_devtypes[] = { 483 { 484 .name = "imx25-sdma", 485 .driver_data = (unsigned long)&sdma_imx25, 486 }, { 487 .name = "imx31-sdma", 488 .driver_data = (unsigned long)&sdma_imx31, 489 }, { 490 .name = "imx35-sdma", 491 .driver_data = (unsigned long)&sdma_imx35, 492 }, { 493 .name = "imx51-sdma", 494 .driver_data = (unsigned long)&sdma_imx51, 495 }, { 496 .name = "imx53-sdma", 497 .driver_data = (unsigned long)&sdma_imx53, 498 }, { 499 .name = "imx6q-sdma", 500 .driver_data = (unsigned long)&sdma_imx6q, 501 }, { 502 /* sentinel */ 503 } 504 }; 505 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 506 507 static const struct of_device_id sdma_dt_ids[] = { 508 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 509 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 510 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 511 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 512 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 513 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 514 { /* sentinel */ } 515 }; 516 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 517 518 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 519 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 520 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 521 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 522 523 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 524 { 525 u32 chnenbl0 = sdma->drvdata->chnenbl0; 526 return chnenbl0 + event * 4; 527 } 528 529 static int sdma_config_ownership(struct sdma_channel *sdmac, 530 bool event_override, bool mcu_override, bool dsp_override) 531 { 532 struct sdma_engine *sdma = sdmac->sdma; 533 int channel = sdmac->channel; 534 unsigned long evt, mcu, dsp; 535 536 if (event_override && mcu_override && dsp_override) 537 return -EINVAL; 538 539 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 540 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 541 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 542 543 if (dsp_override) 544 __clear_bit(channel, &dsp); 545 else 546 __set_bit(channel, &dsp); 547 548 if (event_override) 549 __clear_bit(channel, &evt); 550 else 551 __set_bit(channel, &evt); 552 553 if (mcu_override) 554 __clear_bit(channel, &mcu); 555 else 556 __set_bit(channel, &mcu); 557 558 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 559 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 560 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 561 562 return 0; 563 } 564 565 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 566 { 567 writel(BIT(channel), sdma->regs + SDMA_H_START); 568 } 569 570 /* 571 * sdma_run_channel0 - run a channel and wait till it's done 572 */ 573 static int sdma_run_channel0(struct sdma_engine *sdma) 574 { 575 int ret; 576 u32 reg; 577 578 sdma_enable_channel(sdma, 0); 579 580 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, 581 reg, !(reg & 1), 1, 500); 582 if (ret) 583 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 584 585 /* Set bits of CONFIG register with dynamic context switching */ 586 if (readl(sdma->regs + SDMA_H_CONFIG) == 0) 587 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 588 589 return ret; 590 } 591 592 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 593 u32 address) 594 { 595 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 596 void *buf_virt; 597 dma_addr_t buf_phys; 598 int ret; 599 unsigned long flags; 600 601 buf_virt = dma_alloc_coherent(NULL, 602 size, 603 &buf_phys, GFP_KERNEL); 604 if (!buf_virt) { 605 return -ENOMEM; 606 } 607 608 spin_lock_irqsave(&sdma->channel_0_lock, flags); 609 610 bd0->mode.command = C0_SETPM; 611 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 612 bd0->mode.count = size / 2; 613 bd0->buffer_addr = buf_phys; 614 bd0->ext_buffer_addr = address; 615 616 memcpy(buf_virt, buf, size); 617 618 ret = sdma_run_channel0(sdma); 619 620 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 621 622 dma_free_coherent(NULL, size, buf_virt, buf_phys); 623 624 return ret; 625 } 626 627 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 628 { 629 struct sdma_engine *sdma = sdmac->sdma; 630 int channel = sdmac->channel; 631 unsigned long val; 632 u32 chnenbl = chnenbl_ofs(sdma, event); 633 634 val = readl_relaxed(sdma->regs + chnenbl); 635 __set_bit(channel, &val); 636 writel_relaxed(val, sdma->regs + chnenbl); 637 } 638 639 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 640 { 641 struct sdma_engine *sdma = sdmac->sdma; 642 int channel = sdmac->channel; 643 u32 chnenbl = chnenbl_ofs(sdma, event); 644 unsigned long val; 645 646 val = readl_relaxed(sdma->regs + chnenbl); 647 __clear_bit(channel, &val); 648 writel_relaxed(val, sdma->regs + chnenbl); 649 } 650 651 static void sdma_handle_channel_loop(struct sdma_channel *sdmac) 652 { 653 if (sdmac->desc.callback) 654 sdmac->desc.callback(sdmac->desc.callback_param); 655 } 656 657 static void sdma_update_channel_loop(struct sdma_channel *sdmac) 658 { 659 struct sdma_buffer_descriptor *bd; 660 661 /* 662 * loop mode. Iterate over descriptors, re-setup them and 663 * call callback function. 664 */ 665 while (1) { 666 bd = &sdmac->bd[sdmac->buf_tail]; 667 668 if (bd->mode.status & BD_DONE) 669 break; 670 671 if (bd->mode.status & BD_RROR) 672 sdmac->status = DMA_ERROR; 673 674 bd->mode.status |= BD_DONE; 675 sdmac->buf_tail++; 676 sdmac->buf_tail %= sdmac->num_bd; 677 } 678 } 679 680 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) 681 { 682 struct sdma_buffer_descriptor *bd; 683 int i, error = 0; 684 685 sdmac->chn_real_count = 0; 686 /* 687 * non loop mode. Iterate over all descriptors, collect 688 * errors and call callback function 689 */ 690 for (i = 0; i < sdmac->num_bd; i++) { 691 bd = &sdmac->bd[i]; 692 693 if (bd->mode.status & (BD_DONE | BD_RROR)) 694 error = -EIO; 695 sdmac->chn_real_count += bd->mode.count; 696 } 697 698 if (error) 699 sdmac->status = DMA_ERROR; 700 else 701 sdmac->status = DMA_COMPLETE; 702 703 dma_cookie_complete(&sdmac->desc); 704 if (sdmac->desc.callback) 705 sdmac->desc.callback(sdmac->desc.callback_param); 706 } 707 708 static void sdma_tasklet(unsigned long data) 709 { 710 struct sdma_channel *sdmac = (struct sdma_channel *) data; 711 712 if (sdmac->flags & IMX_DMA_SG_LOOP) 713 sdma_handle_channel_loop(sdmac); 714 else 715 mxc_sdma_handle_channel_normal(sdmac); 716 } 717 718 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 719 { 720 struct sdma_engine *sdma = dev_id; 721 unsigned long stat; 722 723 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 724 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 725 /* channel 0 is special and not handled here, see run_channel0() */ 726 stat &= ~1; 727 728 while (stat) { 729 int channel = fls(stat) - 1; 730 struct sdma_channel *sdmac = &sdma->channel[channel]; 731 732 if (sdmac->flags & IMX_DMA_SG_LOOP) 733 sdma_update_channel_loop(sdmac); 734 735 tasklet_schedule(&sdmac->tasklet); 736 737 __clear_bit(channel, &stat); 738 } 739 740 return IRQ_HANDLED; 741 } 742 743 /* 744 * sets the pc of SDMA script according to the peripheral type 745 */ 746 static void sdma_get_pc(struct sdma_channel *sdmac, 747 enum sdma_peripheral_type peripheral_type) 748 { 749 struct sdma_engine *sdma = sdmac->sdma; 750 int per_2_emi = 0, emi_2_per = 0; 751 /* 752 * These are needed once we start to support transfers between 753 * two peripherals or memory-to-memory transfers 754 */ 755 int per_2_per = 0; 756 757 sdmac->pc_from_device = 0; 758 sdmac->pc_to_device = 0; 759 sdmac->device_to_device = 0; 760 761 switch (peripheral_type) { 762 case IMX_DMATYPE_MEMORY: 763 break; 764 case IMX_DMATYPE_DSP: 765 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 766 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 767 break; 768 case IMX_DMATYPE_FIRI: 769 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 770 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 771 break; 772 case IMX_DMATYPE_UART: 773 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 774 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 775 break; 776 case IMX_DMATYPE_UART_SP: 777 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 778 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 779 break; 780 case IMX_DMATYPE_ATA: 781 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 782 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 783 break; 784 case IMX_DMATYPE_CSPI: 785 case IMX_DMATYPE_EXT: 786 case IMX_DMATYPE_SSI: 787 case IMX_DMATYPE_SAI: 788 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 789 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 790 break; 791 case IMX_DMATYPE_SSI_DUAL: 792 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 793 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 794 break; 795 case IMX_DMATYPE_SSI_SP: 796 case IMX_DMATYPE_MMC: 797 case IMX_DMATYPE_SDHC: 798 case IMX_DMATYPE_CSPI_SP: 799 case IMX_DMATYPE_ESAI: 800 case IMX_DMATYPE_MSHC_SP: 801 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 802 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 803 break; 804 case IMX_DMATYPE_ASRC: 805 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 806 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 807 per_2_per = sdma->script_addrs->per_2_per_addr; 808 break; 809 case IMX_DMATYPE_ASRC_SP: 810 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 811 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 812 per_2_per = sdma->script_addrs->per_2_per_addr; 813 break; 814 case IMX_DMATYPE_MSHC: 815 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 816 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 817 break; 818 case IMX_DMATYPE_CCM: 819 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 820 break; 821 case IMX_DMATYPE_SPDIF: 822 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 823 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 824 break; 825 case IMX_DMATYPE_IPU_MEMORY: 826 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 827 break; 828 default: 829 break; 830 } 831 832 sdmac->pc_from_device = per_2_emi; 833 sdmac->pc_to_device = emi_2_per; 834 sdmac->device_to_device = per_2_per; 835 } 836 837 static int sdma_load_context(struct sdma_channel *sdmac) 838 { 839 struct sdma_engine *sdma = sdmac->sdma; 840 int channel = sdmac->channel; 841 int load_address; 842 struct sdma_context_data *context = sdma->context; 843 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 844 int ret; 845 unsigned long flags; 846 847 if (sdmac->direction == DMA_DEV_TO_MEM) 848 load_address = sdmac->pc_from_device; 849 else if (sdmac->direction == DMA_DEV_TO_DEV) 850 load_address = sdmac->device_to_device; 851 else 852 load_address = sdmac->pc_to_device; 853 854 if (load_address < 0) 855 return load_address; 856 857 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 858 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 859 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 860 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 861 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 862 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 863 864 spin_lock_irqsave(&sdma->channel_0_lock, flags); 865 866 memset(context, 0, sizeof(*context)); 867 context->channel_state.pc = load_address; 868 869 /* Send by context the event mask,base address for peripheral 870 * and watermark level 871 */ 872 context->gReg[0] = sdmac->event_mask[1]; 873 context->gReg[1] = sdmac->event_mask[0]; 874 context->gReg[2] = sdmac->per_addr; 875 context->gReg[6] = sdmac->shp_addr; 876 context->gReg[7] = sdmac->watermark_level; 877 878 bd0->mode.command = C0_SETDM; 879 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 880 bd0->mode.count = sizeof(*context) / 4; 881 bd0->buffer_addr = sdma->context_phys; 882 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 883 ret = sdma_run_channel0(sdma); 884 885 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 886 887 return ret; 888 } 889 890 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 891 { 892 return container_of(chan, struct sdma_channel, chan); 893 } 894 895 static int sdma_disable_channel(struct dma_chan *chan) 896 { 897 struct sdma_channel *sdmac = to_sdma_chan(chan); 898 struct sdma_engine *sdma = sdmac->sdma; 899 int channel = sdmac->channel; 900 901 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 902 sdmac->status = DMA_ERROR; 903 904 return 0; 905 } 906 907 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) 908 { 909 struct sdma_engine *sdma = sdmac->sdma; 910 911 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; 912 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; 913 914 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); 915 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); 916 917 if (sdmac->event_id0 > 31) 918 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; 919 920 if (sdmac->event_id1 > 31) 921 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; 922 923 /* 924 * If LWML(src_maxburst) > HWML(dst_maxburst), we need 925 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap 926 * r0(event_mask[1]) and r1(event_mask[0]). 927 */ 928 if (lwml > hwml) { 929 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | 930 SDMA_WATERMARK_LEVEL_HWML); 931 sdmac->watermark_level |= hwml; 932 sdmac->watermark_level |= lwml << 16; 933 swap(sdmac->event_mask[0], sdmac->event_mask[1]); 934 } 935 936 if (sdmac->per_address2 >= sdma->spba_start_addr && 937 sdmac->per_address2 <= sdma->spba_end_addr) 938 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; 939 940 if (sdmac->per_address >= sdma->spba_start_addr && 941 sdmac->per_address <= sdma->spba_end_addr) 942 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; 943 944 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; 945 } 946 947 static int sdma_config_channel(struct dma_chan *chan) 948 { 949 struct sdma_channel *sdmac = to_sdma_chan(chan); 950 int ret; 951 952 sdma_disable_channel(chan); 953 954 sdmac->event_mask[0] = 0; 955 sdmac->event_mask[1] = 0; 956 sdmac->shp_addr = 0; 957 sdmac->per_addr = 0; 958 959 if (sdmac->event_id0) { 960 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 961 return -EINVAL; 962 sdma_event_enable(sdmac, sdmac->event_id0); 963 } 964 965 if (sdmac->event_id1) { 966 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) 967 return -EINVAL; 968 sdma_event_enable(sdmac, sdmac->event_id1); 969 } 970 971 switch (sdmac->peripheral_type) { 972 case IMX_DMATYPE_DSP: 973 sdma_config_ownership(sdmac, false, true, true); 974 break; 975 case IMX_DMATYPE_MEMORY: 976 sdma_config_ownership(sdmac, false, true, false); 977 break; 978 default: 979 sdma_config_ownership(sdmac, true, true, false); 980 break; 981 } 982 983 sdma_get_pc(sdmac, sdmac->peripheral_type); 984 985 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 986 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 987 /* Handle multiple event channels differently */ 988 if (sdmac->event_id1) { 989 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || 990 sdmac->peripheral_type == IMX_DMATYPE_ASRC) 991 sdma_set_watermarklevel_for_p2p(sdmac); 992 } else 993 __set_bit(sdmac->event_id0, sdmac->event_mask); 994 995 /* Address */ 996 sdmac->shp_addr = sdmac->per_address; 997 sdmac->per_addr = sdmac->per_address2; 998 } else { 999 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 1000 } 1001 1002 ret = sdma_load_context(sdmac); 1003 1004 return ret; 1005 } 1006 1007 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 1008 unsigned int priority) 1009 { 1010 struct sdma_engine *sdma = sdmac->sdma; 1011 int channel = sdmac->channel; 1012 1013 if (priority < MXC_SDMA_MIN_PRIORITY 1014 || priority > MXC_SDMA_MAX_PRIORITY) { 1015 return -EINVAL; 1016 } 1017 1018 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 1019 1020 return 0; 1021 } 1022 1023 static int sdma_request_channel(struct sdma_channel *sdmac) 1024 { 1025 struct sdma_engine *sdma = sdmac->sdma; 1026 int channel = sdmac->channel; 1027 int ret = -EBUSY; 1028 1029 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, 1030 GFP_KERNEL); 1031 if (!sdmac->bd) { 1032 ret = -ENOMEM; 1033 goto out; 1034 } 1035 1036 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; 1037 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1038 1039 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); 1040 return 0; 1041 out: 1042 1043 return ret; 1044 } 1045 1046 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) 1047 { 1048 unsigned long flags; 1049 struct sdma_channel *sdmac = to_sdma_chan(tx->chan); 1050 dma_cookie_t cookie; 1051 1052 spin_lock_irqsave(&sdmac->lock, flags); 1053 1054 cookie = dma_cookie_assign(tx); 1055 1056 spin_unlock_irqrestore(&sdmac->lock, flags); 1057 1058 return cookie; 1059 } 1060 1061 static int sdma_alloc_chan_resources(struct dma_chan *chan) 1062 { 1063 struct sdma_channel *sdmac = to_sdma_chan(chan); 1064 struct imx_dma_data *data = chan->private; 1065 int prio, ret; 1066 1067 if (!data) 1068 return -EINVAL; 1069 1070 switch (data->priority) { 1071 case DMA_PRIO_HIGH: 1072 prio = 3; 1073 break; 1074 case DMA_PRIO_MEDIUM: 1075 prio = 2; 1076 break; 1077 case DMA_PRIO_LOW: 1078 default: 1079 prio = 1; 1080 break; 1081 } 1082 1083 sdmac->peripheral_type = data->peripheral_type; 1084 sdmac->event_id0 = data->dma_request; 1085 sdmac->event_id1 = data->dma_request2; 1086 1087 ret = clk_enable(sdmac->sdma->clk_ipg); 1088 if (ret) 1089 return ret; 1090 ret = clk_enable(sdmac->sdma->clk_ahb); 1091 if (ret) 1092 goto disable_clk_ipg; 1093 1094 ret = sdma_request_channel(sdmac); 1095 if (ret) 1096 goto disable_clk_ahb; 1097 1098 ret = sdma_set_channel_priority(sdmac, prio); 1099 if (ret) 1100 goto disable_clk_ahb; 1101 1102 dma_async_tx_descriptor_init(&sdmac->desc, chan); 1103 sdmac->desc.tx_submit = sdma_tx_submit; 1104 /* txd.flags will be overwritten in prep funcs */ 1105 sdmac->desc.flags = DMA_CTRL_ACK; 1106 1107 return 0; 1108 1109 disable_clk_ahb: 1110 clk_disable(sdmac->sdma->clk_ahb); 1111 disable_clk_ipg: 1112 clk_disable(sdmac->sdma->clk_ipg); 1113 return ret; 1114 } 1115 1116 static void sdma_free_chan_resources(struct dma_chan *chan) 1117 { 1118 struct sdma_channel *sdmac = to_sdma_chan(chan); 1119 struct sdma_engine *sdma = sdmac->sdma; 1120 1121 sdma_disable_channel(chan); 1122 1123 if (sdmac->event_id0) 1124 sdma_event_disable(sdmac, sdmac->event_id0); 1125 if (sdmac->event_id1) 1126 sdma_event_disable(sdmac, sdmac->event_id1); 1127 1128 sdmac->event_id0 = 0; 1129 sdmac->event_id1 = 0; 1130 1131 sdma_set_channel_priority(sdmac, 0); 1132 1133 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); 1134 1135 clk_disable(sdma->clk_ipg); 1136 clk_disable(sdma->clk_ahb); 1137 } 1138 1139 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1140 struct dma_chan *chan, struct scatterlist *sgl, 1141 unsigned int sg_len, enum dma_transfer_direction direction, 1142 unsigned long flags, void *context) 1143 { 1144 struct sdma_channel *sdmac = to_sdma_chan(chan); 1145 struct sdma_engine *sdma = sdmac->sdma; 1146 int ret, i, count; 1147 int channel = sdmac->channel; 1148 struct scatterlist *sg; 1149 1150 if (sdmac->status == DMA_IN_PROGRESS) 1151 return NULL; 1152 sdmac->status = DMA_IN_PROGRESS; 1153 1154 sdmac->flags = 0; 1155 1156 sdmac->buf_tail = 0; 1157 1158 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1159 sg_len, channel); 1160 1161 sdmac->direction = direction; 1162 ret = sdma_load_context(sdmac); 1163 if (ret) 1164 goto err_out; 1165 1166 if (sg_len > NUM_BD) { 1167 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1168 channel, sg_len, NUM_BD); 1169 ret = -EINVAL; 1170 goto err_out; 1171 } 1172 1173 sdmac->chn_count = 0; 1174 for_each_sg(sgl, sg, sg_len, i) { 1175 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1176 int param; 1177 1178 bd->buffer_addr = sg->dma_address; 1179 1180 count = sg_dma_len(sg); 1181 1182 if (count > 0xffff) { 1183 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1184 channel, count, 0xffff); 1185 ret = -EINVAL; 1186 goto err_out; 1187 } 1188 1189 bd->mode.count = count; 1190 sdmac->chn_count += count; 1191 1192 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { 1193 ret = -EINVAL; 1194 goto err_out; 1195 } 1196 1197 switch (sdmac->word_size) { 1198 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1199 bd->mode.command = 0; 1200 if (count & 3 || sg->dma_address & 3) 1201 return NULL; 1202 break; 1203 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1204 bd->mode.command = 2; 1205 if (count & 1 || sg->dma_address & 1) 1206 return NULL; 1207 break; 1208 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1209 bd->mode.command = 1; 1210 break; 1211 default: 1212 return NULL; 1213 } 1214 1215 param = BD_DONE | BD_EXTD | BD_CONT; 1216 1217 if (i + 1 == sg_len) { 1218 param |= BD_INTR; 1219 param |= BD_LAST; 1220 param &= ~BD_CONT; 1221 } 1222 1223 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1224 i, count, (u64)sg->dma_address, 1225 param & BD_WRAP ? "wrap" : "", 1226 param & BD_INTR ? " intr" : ""); 1227 1228 bd->mode.status = param; 1229 } 1230 1231 sdmac->num_bd = sg_len; 1232 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1233 1234 return &sdmac->desc; 1235 err_out: 1236 sdmac->status = DMA_ERROR; 1237 return NULL; 1238 } 1239 1240 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1241 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1242 size_t period_len, enum dma_transfer_direction direction, 1243 unsigned long flags) 1244 { 1245 struct sdma_channel *sdmac = to_sdma_chan(chan); 1246 struct sdma_engine *sdma = sdmac->sdma; 1247 int num_periods = buf_len / period_len; 1248 int channel = sdmac->channel; 1249 int ret, i = 0, buf = 0; 1250 1251 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1252 1253 if (sdmac->status == DMA_IN_PROGRESS) 1254 return NULL; 1255 1256 sdmac->status = DMA_IN_PROGRESS; 1257 1258 sdmac->buf_tail = 0; 1259 sdmac->period_len = period_len; 1260 1261 sdmac->flags |= IMX_DMA_SG_LOOP; 1262 sdmac->direction = direction; 1263 ret = sdma_load_context(sdmac); 1264 if (ret) 1265 goto err_out; 1266 1267 if (num_periods > NUM_BD) { 1268 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1269 channel, num_periods, NUM_BD); 1270 goto err_out; 1271 } 1272 1273 if (period_len > 0xffff) { 1274 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", 1275 channel, period_len, 0xffff); 1276 goto err_out; 1277 } 1278 1279 while (buf < buf_len) { 1280 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1281 int param; 1282 1283 bd->buffer_addr = dma_addr; 1284 1285 bd->mode.count = period_len; 1286 1287 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1288 goto err_out; 1289 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1290 bd->mode.command = 0; 1291 else 1292 bd->mode.command = sdmac->word_size; 1293 1294 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1295 if (i + 1 == num_periods) 1296 param |= BD_WRAP; 1297 1298 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1299 i, period_len, (u64)dma_addr, 1300 param & BD_WRAP ? "wrap" : "", 1301 param & BD_INTR ? " intr" : ""); 1302 1303 bd->mode.status = param; 1304 1305 dma_addr += period_len; 1306 buf += period_len; 1307 1308 i++; 1309 } 1310 1311 sdmac->num_bd = num_periods; 1312 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1313 1314 return &sdmac->desc; 1315 err_out: 1316 sdmac->status = DMA_ERROR; 1317 return NULL; 1318 } 1319 1320 static int sdma_config(struct dma_chan *chan, 1321 struct dma_slave_config *dmaengine_cfg) 1322 { 1323 struct sdma_channel *sdmac = to_sdma_chan(chan); 1324 1325 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 1326 sdmac->per_address = dmaengine_cfg->src_addr; 1327 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1328 dmaengine_cfg->src_addr_width; 1329 sdmac->word_size = dmaengine_cfg->src_addr_width; 1330 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) { 1331 sdmac->per_address2 = dmaengine_cfg->src_addr; 1332 sdmac->per_address = dmaengine_cfg->dst_addr; 1333 sdmac->watermark_level = dmaengine_cfg->src_maxburst & 1334 SDMA_WATERMARK_LEVEL_LWML; 1335 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & 1336 SDMA_WATERMARK_LEVEL_HWML; 1337 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1338 } else { 1339 sdmac->per_address = dmaengine_cfg->dst_addr; 1340 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1341 dmaengine_cfg->dst_addr_width; 1342 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1343 } 1344 sdmac->direction = dmaengine_cfg->direction; 1345 return sdma_config_channel(chan); 1346 } 1347 1348 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1349 dma_cookie_t cookie, 1350 struct dma_tx_state *txstate) 1351 { 1352 struct sdma_channel *sdmac = to_sdma_chan(chan); 1353 u32 residue; 1354 1355 if (sdmac->flags & IMX_DMA_SG_LOOP) 1356 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len; 1357 else 1358 residue = sdmac->chn_count - sdmac->chn_real_count; 1359 1360 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1361 residue); 1362 1363 return sdmac->status; 1364 } 1365 1366 static void sdma_issue_pending(struct dma_chan *chan) 1367 { 1368 struct sdma_channel *sdmac = to_sdma_chan(chan); 1369 struct sdma_engine *sdma = sdmac->sdma; 1370 1371 if (sdmac->status == DMA_IN_PROGRESS) 1372 sdma_enable_channel(sdma, sdmac->channel); 1373 } 1374 1375 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1376 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1377 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 1378 1379 static void sdma_add_scripts(struct sdma_engine *sdma, 1380 const struct sdma_script_start_addrs *addr) 1381 { 1382 s32 *addr_arr = (u32 *)addr; 1383 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1384 int i; 1385 1386 /* use the default firmware in ROM if missing external firmware */ 1387 if (!sdma->script_number) 1388 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1389 1390 for (i = 0; i < sdma->script_number; i++) 1391 if (addr_arr[i] > 0) 1392 saddr_arr[i] = addr_arr[i]; 1393 } 1394 1395 static void sdma_load_firmware(const struct firmware *fw, void *context) 1396 { 1397 struct sdma_engine *sdma = context; 1398 const struct sdma_firmware_header *header; 1399 const struct sdma_script_start_addrs *addr; 1400 unsigned short *ram_code; 1401 1402 if (!fw) { 1403 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); 1404 /* In this case we just use the ROM firmware. */ 1405 return; 1406 } 1407 1408 if (fw->size < sizeof(*header)) 1409 goto err_firmware; 1410 1411 header = (struct sdma_firmware_header *)fw->data; 1412 1413 if (header->magic != SDMA_FIRMWARE_MAGIC) 1414 goto err_firmware; 1415 if (header->ram_code_start + header->ram_code_size > fw->size) 1416 goto err_firmware; 1417 switch (header->version_major) { 1418 case 1: 1419 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1420 break; 1421 case 2: 1422 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1423 break; 1424 case 3: 1425 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; 1426 break; 1427 default: 1428 dev_err(sdma->dev, "unknown firmware version\n"); 1429 goto err_firmware; 1430 } 1431 1432 addr = (void *)header + header->script_addrs_start; 1433 ram_code = (void *)header + header->ram_code_start; 1434 1435 clk_enable(sdma->clk_ipg); 1436 clk_enable(sdma->clk_ahb); 1437 /* download the RAM image for SDMA */ 1438 sdma_load_script(sdma, ram_code, 1439 header->ram_code_size, 1440 addr->ram_code_start_addr); 1441 clk_disable(sdma->clk_ipg); 1442 clk_disable(sdma->clk_ahb); 1443 1444 sdma_add_scripts(sdma, addr); 1445 1446 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1447 header->version_major, 1448 header->version_minor); 1449 1450 err_firmware: 1451 release_firmware(fw); 1452 } 1453 1454 #define EVENT_REMAP_CELLS 3 1455 1456 static int sdma_event_remap(struct sdma_engine *sdma) 1457 { 1458 struct device_node *np = sdma->dev->of_node; 1459 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); 1460 struct property *event_remap; 1461 struct regmap *gpr; 1462 char propname[] = "fsl,sdma-event-remap"; 1463 u32 reg, val, shift, num_map, i; 1464 int ret = 0; 1465 1466 if (IS_ERR(np) || IS_ERR(gpr_np)) 1467 goto out; 1468 1469 event_remap = of_find_property(np, propname, NULL); 1470 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; 1471 if (!num_map) { 1472 dev_dbg(sdma->dev, "no event needs to be remapped\n"); 1473 goto out; 1474 } else if (num_map % EVENT_REMAP_CELLS) { 1475 dev_err(sdma->dev, "the property %s must modulo %d\n", 1476 propname, EVENT_REMAP_CELLS); 1477 ret = -EINVAL; 1478 goto out; 1479 } 1480 1481 gpr = syscon_node_to_regmap(gpr_np); 1482 if (IS_ERR(gpr)) { 1483 dev_err(sdma->dev, "failed to get gpr regmap\n"); 1484 ret = PTR_ERR(gpr); 1485 goto out; 1486 } 1487 1488 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { 1489 ret = of_property_read_u32_index(np, propname, i, ®); 1490 if (ret) { 1491 dev_err(sdma->dev, "failed to read property %s index %d\n", 1492 propname, i); 1493 goto out; 1494 } 1495 1496 ret = of_property_read_u32_index(np, propname, i + 1, &shift); 1497 if (ret) { 1498 dev_err(sdma->dev, "failed to read property %s index %d\n", 1499 propname, i + 1); 1500 goto out; 1501 } 1502 1503 ret = of_property_read_u32_index(np, propname, i + 2, &val); 1504 if (ret) { 1505 dev_err(sdma->dev, "failed to read property %s index %d\n", 1506 propname, i + 2); 1507 goto out; 1508 } 1509 1510 regmap_update_bits(gpr, reg, BIT(shift), val << shift); 1511 } 1512 1513 out: 1514 if (!IS_ERR(gpr_np)) 1515 of_node_put(gpr_np); 1516 1517 return ret; 1518 } 1519 1520 static int sdma_get_firmware(struct sdma_engine *sdma, 1521 const char *fw_name) 1522 { 1523 int ret; 1524 1525 ret = request_firmware_nowait(THIS_MODULE, 1526 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1527 GFP_KERNEL, sdma, sdma_load_firmware); 1528 1529 return ret; 1530 } 1531 1532 static int sdma_init(struct sdma_engine *sdma) 1533 { 1534 int i, ret; 1535 dma_addr_t ccb_phys; 1536 1537 ret = clk_enable(sdma->clk_ipg); 1538 if (ret) 1539 return ret; 1540 ret = clk_enable(sdma->clk_ahb); 1541 if (ret) 1542 goto disable_clk_ipg; 1543 1544 /* Be sure SDMA has not started yet */ 1545 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1546 1547 sdma->channel_control = dma_alloc_coherent(NULL, 1548 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1549 sizeof(struct sdma_context_data), 1550 &ccb_phys, GFP_KERNEL); 1551 1552 if (!sdma->channel_control) { 1553 ret = -ENOMEM; 1554 goto err_dma_alloc; 1555 } 1556 1557 sdma->context = (void *)sdma->channel_control + 1558 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1559 sdma->context_phys = ccb_phys + 1560 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1561 1562 /* Zero-out the CCB structures array just allocated */ 1563 memset(sdma->channel_control, 0, 1564 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1565 1566 /* disable all channels */ 1567 for (i = 0; i < sdma->drvdata->num_events; i++) 1568 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1569 1570 /* All channels have priority 0 */ 1571 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1572 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1573 1574 ret = sdma_request_channel(&sdma->channel[0]); 1575 if (ret) 1576 goto err_dma_alloc; 1577 1578 sdma_config_ownership(&sdma->channel[0], false, true, false); 1579 1580 /* Set Command Channel (Channel Zero) */ 1581 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1582 1583 /* Set bits of CONFIG register but with static context switching */ 1584 /* FIXME: Check whether to set ACR bit depending on clock ratios */ 1585 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1586 1587 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1588 1589 /* Initializes channel's priorities */ 1590 sdma_set_channel_priority(&sdma->channel[0], 7); 1591 1592 clk_disable(sdma->clk_ipg); 1593 clk_disable(sdma->clk_ahb); 1594 1595 return 0; 1596 1597 err_dma_alloc: 1598 clk_disable(sdma->clk_ahb); 1599 disable_clk_ipg: 1600 clk_disable(sdma->clk_ipg); 1601 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1602 return ret; 1603 } 1604 1605 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1606 { 1607 struct sdma_channel *sdmac = to_sdma_chan(chan); 1608 struct imx_dma_data *data = fn_param; 1609 1610 if (!imx_dma_is_general_purpose(chan)) 1611 return false; 1612 1613 sdmac->data = *data; 1614 chan->private = &sdmac->data; 1615 1616 return true; 1617 } 1618 1619 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1620 struct of_dma *ofdma) 1621 { 1622 struct sdma_engine *sdma = ofdma->of_dma_data; 1623 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1624 struct imx_dma_data data; 1625 1626 if (dma_spec->args_count != 3) 1627 return NULL; 1628 1629 data.dma_request = dma_spec->args[0]; 1630 data.peripheral_type = dma_spec->args[1]; 1631 data.priority = dma_spec->args[2]; 1632 /* 1633 * init dma_request2 to zero, which is not used by the dts. 1634 * For P2P, dma_request2 is init from dma_request_channel(), 1635 * chan->private will point to the imx_dma_data, and in 1636 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will 1637 * be set to sdmac->event_id1. 1638 */ 1639 data.dma_request2 = 0; 1640 1641 return dma_request_channel(mask, sdma_filter_fn, &data); 1642 } 1643 1644 static int sdma_probe(struct platform_device *pdev) 1645 { 1646 const struct of_device_id *of_id = 1647 of_match_device(sdma_dt_ids, &pdev->dev); 1648 struct device_node *np = pdev->dev.of_node; 1649 struct device_node *spba_bus; 1650 const char *fw_name; 1651 int ret; 1652 int irq; 1653 struct resource *iores; 1654 struct resource spba_res; 1655 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1656 int i; 1657 struct sdma_engine *sdma; 1658 s32 *saddr_arr; 1659 const struct sdma_driver_data *drvdata = NULL; 1660 1661 if (of_id) 1662 drvdata = of_id->data; 1663 else if (pdev->id_entry) 1664 drvdata = (void *)pdev->id_entry->driver_data; 1665 1666 if (!drvdata) { 1667 dev_err(&pdev->dev, "unable to find driver data\n"); 1668 return -EINVAL; 1669 } 1670 1671 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1672 if (ret) 1673 return ret; 1674 1675 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); 1676 if (!sdma) 1677 return -ENOMEM; 1678 1679 spin_lock_init(&sdma->channel_0_lock); 1680 1681 sdma->dev = &pdev->dev; 1682 sdma->drvdata = drvdata; 1683 1684 irq = platform_get_irq(pdev, 0); 1685 if (irq < 0) 1686 return irq; 1687 1688 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1689 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); 1690 if (IS_ERR(sdma->regs)) 1691 return PTR_ERR(sdma->regs); 1692 1693 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1694 if (IS_ERR(sdma->clk_ipg)) 1695 return PTR_ERR(sdma->clk_ipg); 1696 1697 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1698 if (IS_ERR(sdma->clk_ahb)) 1699 return PTR_ERR(sdma->clk_ahb); 1700 1701 clk_prepare(sdma->clk_ipg); 1702 clk_prepare(sdma->clk_ahb); 1703 1704 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", 1705 sdma); 1706 if (ret) 1707 return ret; 1708 1709 sdma->irq = irq; 1710 1711 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 1712 if (!sdma->script_addrs) 1713 return -ENOMEM; 1714 1715 /* initially no scripts available */ 1716 saddr_arr = (s32 *)sdma->script_addrs; 1717 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 1718 saddr_arr[i] = -EINVAL; 1719 1720 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1721 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1722 1723 INIT_LIST_HEAD(&sdma->dma_device.channels); 1724 /* Initialize channel parameters */ 1725 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1726 struct sdma_channel *sdmac = &sdma->channel[i]; 1727 1728 sdmac->sdma = sdma; 1729 spin_lock_init(&sdmac->lock); 1730 1731 sdmac->chan.device = &sdma->dma_device; 1732 dma_cookie_init(&sdmac->chan); 1733 sdmac->channel = i; 1734 1735 tasklet_init(&sdmac->tasklet, sdma_tasklet, 1736 (unsigned long) sdmac); 1737 /* 1738 * Add the channel to the DMAC list. Do not add channel 0 though 1739 * because we need it internally in the SDMA driver. This also means 1740 * that channel 0 in dmaengine counting matches sdma channel 1. 1741 */ 1742 if (i) 1743 list_add_tail(&sdmac->chan.device_node, 1744 &sdma->dma_device.channels); 1745 } 1746 1747 ret = sdma_init(sdma); 1748 if (ret) 1749 goto err_init; 1750 1751 ret = sdma_event_remap(sdma); 1752 if (ret) 1753 goto err_init; 1754 1755 if (sdma->drvdata->script_addrs) 1756 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 1757 if (pdata && pdata->script_addrs) 1758 sdma_add_scripts(sdma, pdata->script_addrs); 1759 1760 if (pdata) { 1761 ret = sdma_get_firmware(sdma, pdata->fw_name); 1762 if (ret) 1763 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 1764 } else { 1765 /* 1766 * Because that device tree does not encode ROM script address, 1767 * the RAM script in firmware is mandatory for device tree 1768 * probe, otherwise it fails. 1769 */ 1770 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 1771 &fw_name); 1772 if (ret) 1773 dev_warn(&pdev->dev, "failed to get firmware name\n"); 1774 else { 1775 ret = sdma_get_firmware(sdma, fw_name); 1776 if (ret) 1777 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 1778 } 1779 } 1780 1781 sdma->dma_device.dev = &pdev->dev; 1782 1783 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 1784 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 1785 sdma->dma_device.device_tx_status = sdma_tx_status; 1786 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 1787 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1788 sdma->dma_device.device_config = sdma_config; 1789 sdma->dma_device.device_terminate_all = sdma_disable_channel; 1790 sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1791 sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1792 sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1793 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1794 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1795 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1796 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1797 1798 platform_set_drvdata(pdev, sdma); 1799 1800 ret = dma_async_device_register(&sdma->dma_device); 1801 if (ret) { 1802 dev_err(&pdev->dev, "unable to register\n"); 1803 goto err_init; 1804 } 1805 1806 if (np) { 1807 ret = of_dma_controller_register(np, sdma_xlate, sdma); 1808 if (ret) { 1809 dev_err(&pdev->dev, "failed to register controller\n"); 1810 goto err_register; 1811 } 1812 1813 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); 1814 ret = of_address_to_resource(spba_bus, 0, &spba_res); 1815 if (!ret) { 1816 sdma->spba_start_addr = spba_res.start; 1817 sdma->spba_end_addr = spba_res.end; 1818 } 1819 of_node_put(spba_bus); 1820 } 1821 1822 return 0; 1823 1824 err_register: 1825 dma_async_device_unregister(&sdma->dma_device); 1826 err_init: 1827 kfree(sdma->script_addrs); 1828 return ret; 1829 } 1830 1831 static int sdma_remove(struct platform_device *pdev) 1832 { 1833 struct sdma_engine *sdma = platform_get_drvdata(pdev); 1834 int i; 1835 1836 devm_free_irq(&pdev->dev, sdma->irq, sdma); 1837 dma_async_device_unregister(&sdma->dma_device); 1838 kfree(sdma->script_addrs); 1839 /* Kill the tasklet */ 1840 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1841 struct sdma_channel *sdmac = &sdma->channel[i]; 1842 1843 tasklet_kill(&sdmac->tasklet); 1844 } 1845 1846 platform_set_drvdata(pdev, NULL); 1847 return 0; 1848 } 1849 1850 static struct platform_driver sdma_driver = { 1851 .driver = { 1852 .name = "imx-sdma", 1853 .of_match_table = sdma_dt_ids, 1854 }, 1855 .id_table = sdma_devtypes, 1856 .remove = sdma_remove, 1857 .probe = sdma_probe, 1858 }; 1859 1860 module_platform_driver(sdma_driver); 1861 1862 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1863 MODULE_DESCRIPTION("i.MX SDMA driver"); 1864 MODULE_LICENSE("GPL"); 1865