1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // drivers/dma/imx-sdma.c 4 // 5 // This file contains a driver for the Freescale Smart DMA engine 6 // 7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 // 9 // Based on code from Freescale: 10 // 11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 12 13 #include <linux/init.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/types.h> 17 #include <linux/bitops.h> 18 #include <linux/mm.h> 19 #include <linux/interrupt.h> 20 #include <linux/clk.h> 21 #include <linux/delay.h> 22 #include <linux/sched.h> 23 #include <linux/semaphore.h> 24 #include <linux/spinlock.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firmware.h> 28 #include <linux/slab.h> 29 #include <linux/platform_device.h> 30 #include <linux/dmaengine.h> 31 #include <linux/of.h> 32 #include <linux/of_address.h> 33 #include <linux/of_device.h> 34 #include <linux/of_dma.h> 35 #include <linux/workqueue.h> 36 37 #include <asm/irq.h> 38 #include <linux/platform_data/dma-imx-sdma.h> 39 #include <linux/platform_data/dma-imx.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 43 44 #include "dmaengine.h" 45 #include "virt-dma.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * p_2_p watermark_level description 128 * Bits Name Description 129 * 0-7 Lower WML Lower watermark level 130 * 8 PS 1: Pad Swallowing 131 * 0: No Pad Swallowing 132 * 9 PA 1: Pad Adding 133 * 0: No Pad Adding 134 * 10 SPDIF If this bit is set both source 135 * and destination are on SPBA 136 * 11 Source Bit(SP) 1: Source on SPBA 137 * 0: Source on AIPS 138 * 12 Destination Bit(DP) 1: Destination on SPBA 139 * 0: Destination on AIPS 140 * 13-15 --------- MUST BE 0 141 * 16-23 Higher WML HWML 142 * 24-27 N Total number of samples after 143 * which Pad adding/Swallowing 144 * must be done. It must be odd. 145 * 28 Lower WML Event(LWE) SDMA events reg to check for 146 * LWML event mask 147 * 0: LWE in EVENTS register 148 * 1: LWE in EVENTS2 register 149 * 29 Higher WML Event(HWE) SDMA events reg to check for 150 * HWML event mask 151 * 0: HWE in EVENTS register 152 * 1: HWE in EVENTS2 register 153 * 30 --------- MUST BE 0 154 * 31 CONT 1: Amount of samples to be 155 * transferred is unknown and 156 * script will keep on 157 * transferring samples as long as 158 * both events are detected and 159 * script must be manually stopped 160 * by the application 161 * 0: The amount of samples to be 162 * transferred is equal to the 163 * count field of mode word 164 */ 165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF 166 #define SDMA_WATERMARK_LEVEL_PS BIT(8) 167 #define SDMA_WATERMARK_LEVEL_PA BIT(9) 168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) 169 #define SDMA_WATERMARK_LEVEL_SP BIT(11) 170 #define SDMA_WATERMARK_LEVEL_DP BIT(12) 171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) 172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28) 173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29) 174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31) 175 176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 179 180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ 181 BIT(DMA_MEM_TO_DEV) | \ 182 BIT(DMA_DEV_TO_DEV)) 183 184 /* 185 * Mode/Count of data node descriptors - IPCv2 186 */ 187 struct sdma_mode_count { 188 #define SDMA_BD_MAX_CNT 0xffff 189 u32 count : 16; /* size of the buffer pointed by this BD */ 190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 191 u32 command : 8; /* command mostly used for channel 0 */ 192 }; 193 194 /* 195 * Buffer descriptor 196 */ 197 struct sdma_buffer_descriptor { 198 struct sdma_mode_count mode; 199 u32 buffer_addr; /* address of the buffer described */ 200 u32 ext_buffer_addr; /* extended buffer address */ 201 } __attribute__ ((packed)); 202 203 /** 204 * struct sdma_channel_control - Channel control Block 205 * 206 * @current_bd_ptr: current buffer descriptor processed 207 * @base_bd_ptr: first element of buffer descriptor array 208 * @unused: padding. The SDMA engine expects an array of 128 byte 209 * control blocks 210 */ 211 struct sdma_channel_control { 212 u32 current_bd_ptr; 213 u32 base_bd_ptr; 214 u32 unused[2]; 215 } __attribute__ ((packed)); 216 217 /** 218 * struct sdma_state_registers - SDMA context for a channel 219 * 220 * @pc: program counter 221 * @unused1: unused 222 * @t: test bit: status of arithmetic & test instruction 223 * @rpc: return program counter 224 * @unused0: unused 225 * @sf: source fault while loading data 226 * @spc: loop start program counter 227 * @unused2: unused 228 * @df: destination fault while storing data 229 * @epc: loop end program counter 230 * @lm: loop mode 231 */ 232 struct sdma_state_registers { 233 u32 pc :14; 234 u32 unused1: 1; 235 u32 t : 1; 236 u32 rpc :14; 237 u32 unused0: 1; 238 u32 sf : 1; 239 u32 spc :14; 240 u32 unused2: 1; 241 u32 df : 1; 242 u32 epc :14; 243 u32 lm : 2; 244 } __attribute__ ((packed)); 245 246 /** 247 * struct sdma_context_data - sdma context specific to a channel 248 * 249 * @channel_state: channel state bits 250 * @gReg: general registers 251 * @mda: burst dma destination address register 252 * @msa: burst dma source address register 253 * @ms: burst dma status register 254 * @md: burst dma data register 255 * @pda: peripheral dma destination address register 256 * @psa: peripheral dma source address register 257 * @ps: peripheral dma status register 258 * @pd: peripheral dma data register 259 * @ca: CRC polynomial register 260 * @cs: CRC accumulator register 261 * @dda: dedicated core destination address register 262 * @dsa: dedicated core source address register 263 * @ds: dedicated core status register 264 * @dd: dedicated core data register 265 * @scratch0: 1st word of dedicated ram for context switch 266 * @scratch1: 2nd word of dedicated ram for context switch 267 * @scratch2: 3rd word of dedicated ram for context switch 268 * @scratch3: 4th word of dedicated ram for context switch 269 * @scratch4: 5th word of dedicated ram for context switch 270 * @scratch5: 6th word of dedicated ram for context switch 271 * @scratch6: 7th word of dedicated ram for context switch 272 * @scratch7: 8th word of dedicated ram for context switch 273 */ 274 struct sdma_context_data { 275 struct sdma_state_registers channel_state; 276 u32 gReg[8]; 277 u32 mda; 278 u32 msa; 279 u32 ms; 280 u32 md; 281 u32 pda; 282 u32 psa; 283 u32 ps; 284 u32 pd; 285 u32 ca; 286 u32 cs; 287 u32 dda; 288 u32 dsa; 289 u32 ds; 290 u32 dd; 291 u32 scratch0; 292 u32 scratch1; 293 u32 scratch2; 294 u32 scratch3; 295 u32 scratch4; 296 u32 scratch5; 297 u32 scratch6; 298 u32 scratch7; 299 } __attribute__ ((packed)); 300 301 302 struct sdma_engine; 303 304 /** 305 * struct sdma_desc - descriptor structor for one transfer 306 * @vd: descriptor for virt dma 307 * @num_bd: number of descriptors currently handling 308 * @bd_phys: physical address of bd 309 * @buf_tail: ID of the buffer that was processed 310 * @buf_ptail: ID of the previous buffer that was processed 311 * @period_len: period length, used in cyclic. 312 * @chn_real_count: the real count updated from bd->mode.count 313 * @chn_count: the transfer count set 314 * @sdmac: sdma_channel pointer 315 * @bd: pointer of allocate bd 316 */ 317 struct sdma_desc { 318 struct virt_dma_desc vd; 319 unsigned int num_bd; 320 dma_addr_t bd_phys; 321 unsigned int buf_tail; 322 unsigned int buf_ptail; 323 unsigned int period_len; 324 unsigned int chn_real_count; 325 unsigned int chn_count; 326 struct sdma_channel *sdmac; 327 struct sdma_buffer_descriptor *bd; 328 }; 329 330 /** 331 * struct sdma_channel - housekeeping for a SDMA channel 332 * 333 * @vc: virt_dma base structure 334 * @desc: sdma description including vd and other special member 335 * @sdma: pointer to the SDMA engine for this channel 336 * @channel: the channel number, matches dmaengine chan_id + 1 337 * @direction: transfer type. Needed for setting SDMA script 338 * @slave_config Slave configuration 339 * @peripheral_type: Peripheral type. Needed for setting SDMA script 340 * @event_id0: aka dma request line 341 * @event_id1: for channels that use 2 events 342 * @word_size: peripheral access size 343 * @pc_from_device: script address for those device_2_memory 344 * @pc_to_device: script address for those memory_2_device 345 * @device_to_device: script address for those device_2_device 346 * @pc_to_pc: script address for those memory_2_memory 347 * @flags: loop mode or not 348 * @per_address: peripheral source or destination address in common case 349 * destination address in p_2_p case 350 * @per_address2: peripheral source address in p_2_p case 351 * @event_mask: event mask used in p_2_p script 352 * @watermark_level: value for gReg[7], some script will extend it from 353 * basic watermark such as p_2_p 354 * @shp_addr: value for gReg[6] 355 * @per_addr: value for gReg[2] 356 * @status: status of dma channel 357 * @data: specific sdma interface structure 358 * @bd_pool: dma_pool for bd 359 */ 360 struct sdma_channel { 361 struct virt_dma_chan vc; 362 struct sdma_desc *desc; 363 struct sdma_engine *sdma; 364 unsigned int channel; 365 enum dma_transfer_direction direction; 366 struct dma_slave_config slave_config; 367 enum sdma_peripheral_type peripheral_type; 368 unsigned int event_id0; 369 unsigned int event_id1; 370 enum dma_slave_buswidth word_size; 371 unsigned int pc_from_device, pc_to_device; 372 unsigned int device_to_device; 373 unsigned int pc_to_pc; 374 unsigned long flags; 375 dma_addr_t per_address, per_address2; 376 unsigned long event_mask[2]; 377 unsigned long watermark_level; 378 u32 shp_addr, per_addr; 379 enum dma_status status; 380 bool context_loaded; 381 struct imx_dma_data data; 382 struct work_struct terminate_worker; 383 }; 384 385 #define IMX_DMA_SG_LOOP BIT(0) 386 387 #define MAX_DMA_CHANNELS 32 388 #define MXC_SDMA_DEFAULT_PRIORITY 1 389 #define MXC_SDMA_MIN_PRIORITY 1 390 #define MXC_SDMA_MAX_PRIORITY 7 391 392 #define SDMA_FIRMWARE_MAGIC 0x414d4453 393 394 /** 395 * struct sdma_firmware_header - Layout of the firmware image 396 * 397 * @magic: "SDMA" 398 * @version_major: increased whenever layout of struct 399 * sdma_script_start_addrs changes. 400 * @version_minor: firmware minor version (for binary compatible changes) 401 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image 402 * @num_script_addrs: Number of script addresses in this image 403 * @ram_code_start: offset of SDMA ram image in this firmware image 404 * @ram_code_size: size of SDMA ram image 405 * @script_addrs: Stores the start address of the SDMA scripts 406 * (in SDMA memory space) 407 */ 408 struct sdma_firmware_header { 409 u32 magic; 410 u32 version_major; 411 u32 version_minor; 412 u32 script_addrs_start; 413 u32 num_script_addrs; 414 u32 ram_code_start; 415 u32 ram_code_size; 416 }; 417 418 struct sdma_driver_data { 419 int chnenbl0; 420 int num_events; 421 struct sdma_script_start_addrs *script_addrs; 422 }; 423 424 struct sdma_engine { 425 struct device *dev; 426 struct device_dma_parameters dma_parms; 427 struct sdma_channel channel[MAX_DMA_CHANNELS]; 428 struct sdma_channel_control *channel_control; 429 void __iomem *regs; 430 struct sdma_context_data *context; 431 dma_addr_t context_phys; 432 struct dma_device dma_device; 433 struct clk *clk_ipg; 434 struct clk *clk_ahb; 435 spinlock_t channel_0_lock; 436 u32 script_number; 437 struct sdma_script_start_addrs *script_addrs; 438 const struct sdma_driver_data *drvdata; 439 u32 spba_start_addr; 440 u32 spba_end_addr; 441 unsigned int irq; 442 dma_addr_t bd0_phys; 443 struct sdma_buffer_descriptor *bd0; 444 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ 445 bool clk_ratio; 446 }; 447 448 static int sdma_config_write(struct dma_chan *chan, 449 struct dma_slave_config *dmaengine_cfg, 450 enum dma_transfer_direction direction); 451 452 static struct sdma_driver_data sdma_imx31 = { 453 .chnenbl0 = SDMA_CHNENBL0_IMX31, 454 .num_events = 32, 455 }; 456 457 static struct sdma_script_start_addrs sdma_script_imx25 = { 458 .ap_2_ap_addr = 729, 459 .uart_2_mcu_addr = 904, 460 .per_2_app_addr = 1255, 461 .mcu_2_app_addr = 834, 462 .uartsh_2_mcu_addr = 1120, 463 .per_2_shp_addr = 1329, 464 .mcu_2_shp_addr = 1048, 465 .ata_2_mcu_addr = 1560, 466 .mcu_2_ata_addr = 1479, 467 .app_2_per_addr = 1189, 468 .app_2_mcu_addr = 770, 469 .shp_2_per_addr = 1407, 470 .shp_2_mcu_addr = 979, 471 }; 472 473 static struct sdma_driver_data sdma_imx25 = { 474 .chnenbl0 = SDMA_CHNENBL0_IMX35, 475 .num_events = 48, 476 .script_addrs = &sdma_script_imx25, 477 }; 478 479 static struct sdma_driver_data sdma_imx35 = { 480 .chnenbl0 = SDMA_CHNENBL0_IMX35, 481 .num_events = 48, 482 }; 483 484 static struct sdma_script_start_addrs sdma_script_imx51 = { 485 .ap_2_ap_addr = 642, 486 .uart_2_mcu_addr = 817, 487 .mcu_2_app_addr = 747, 488 .mcu_2_shp_addr = 961, 489 .ata_2_mcu_addr = 1473, 490 .mcu_2_ata_addr = 1392, 491 .app_2_per_addr = 1033, 492 .app_2_mcu_addr = 683, 493 .shp_2_per_addr = 1251, 494 .shp_2_mcu_addr = 892, 495 }; 496 497 static struct sdma_driver_data sdma_imx51 = { 498 .chnenbl0 = SDMA_CHNENBL0_IMX35, 499 .num_events = 48, 500 .script_addrs = &sdma_script_imx51, 501 }; 502 503 static struct sdma_script_start_addrs sdma_script_imx53 = { 504 .ap_2_ap_addr = 642, 505 .app_2_mcu_addr = 683, 506 .mcu_2_app_addr = 747, 507 .uart_2_mcu_addr = 817, 508 .shp_2_mcu_addr = 891, 509 .mcu_2_shp_addr = 960, 510 .uartsh_2_mcu_addr = 1032, 511 .spdif_2_mcu_addr = 1100, 512 .mcu_2_spdif_addr = 1134, 513 .firi_2_mcu_addr = 1193, 514 .mcu_2_firi_addr = 1290, 515 }; 516 517 static struct sdma_driver_data sdma_imx53 = { 518 .chnenbl0 = SDMA_CHNENBL0_IMX35, 519 .num_events = 48, 520 .script_addrs = &sdma_script_imx53, 521 }; 522 523 static struct sdma_script_start_addrs sdma_script_imx6q = { 524 .ap_2_ap_addr = 642, 525 .uart_2_mcu_addr = 817, 526 .mcu_2_app_addr = 747, 527 .per_2_per_addr = 6331, 528 .uartsh_2_mcu_addr = 1032, 529 .mcu_2_shp_addr = 960, 530 .app_2_mcu_addr = 683, 531 .shp_2_mcu_addr = 891, 532 .spdif_2_mcu_addr = 1100, 533 .mcu_2_spdif_addr = 1134, 534 }; 535 536 static struct sdma_driver_data sdma_imx6q = { 537 .chnenbl0 = SDMA_CHNENBL0_IMX35, 538 .num_events = 48, 539 .script_addrs = &sdma_script_imx6q, 540 }; 541 542 static struct sdma_script_start_addrs sdma_script_imx7d = { 543 .ap_2_ap_addr = 644, 544 .uart_2_mcu_addr = 819, 545 .mcu_2_app_addr = 749, 546 .uartsh_2_mcu_addr = 1034, 547 .mcu_2_shp_addr = 962, 548 .app_2_mcu_addr = 685, 549 .shp_2_mcu_addr = 893, 550 .spdif_2_mcu_addr = 1102, 551 .mcu_2_spdif_addr = 1136, 552 }; 553 554 static struct sdma_driver_data sdma_imx7d = { 555 .chnenbl0 = SDMA_CHNENBL0_IMX35, 556 .num_events = 48, 557 .script_addrs = &sdma_script_imx7d, 558 }; 559 560 static const struct platform_device_id sdma_devtypes[] = { 561 { 562 .name = "imx25-sdma", 563 .driver_data = (unsigned long)&sdma_imx25, 564 }, { 565 .name = "imx31-sdma", 566 .driver_data = (unsigned long)&sdma_imx31, 567 }, { 568 .name = "imx35-sdma", 569 .driver_data = (unsigned long)&sdma_imx35, 570 }, { 571 .name = "imx51-sdma", 572 .driver_data = (unsigned long)&sdma_imx51, 573 }, { 574 .name = "imx53-sdma", 575 .driver_data = (unsigned long)&sdma_imx53, 576 }, { 577 .name = "imx6q-sdma", 578 .driver_data = (unsigned long)&sdma_imx6q, 579 }, { 580 .name = "imx7d-sdma", 581 .driver_data = (unsigned long)&sdma_imx7d, 582 }, { 583 /* sentinel */ 584 } 585 }; 586 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 587 588 static const struct of_device_id sdma_dt_ids[] = { 589 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 590 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 591 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 592 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 593 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 594 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 595 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, 596 { /* sentinel */ } 597 }; 598 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 599 600 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 601 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 602 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 603 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 604 605 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 606 { 607 u32 chnenbl0 = sdma->drvdata->chnenbl0; 608 return chnenbl0 + event * 4; 609 } 610 611 static int sdma_config_ownership(struct sdma_channel *sdmac, 612 bool event_override, bool mcu_override, bool dsp_override) 613 { 614 struct sdma_engine *sdma = sdmac->sdma; 615 int channel = sdmac->channel; 616 unsigned long evt, mcu, dsp; 617 618 if (event_override && mcu_override && dsp_override) 619 return -EINVAL; 620 621 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 622 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 623 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 624 625 if (dsp_override) 626 __clear_bit(channel, &dsp); 627 else 628 __set_bit(channel, &dsp); 629 630 if (event_override) 631 __clear_bit(channel, &evt); 632 else 633 __set_bit(channel, &evt); 634 635 if (mcu_override) 636 __clear_bit(channel, &mcu); 637 else 638 __set_bit(channel, &mcu); 639 640 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 641 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 642 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 643 644 return 0; 645 } 646 647 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 648 { 649 writel(BIT(channel), sdma->regs + SDMA_H_START); 650 } 651 652 /* 653 * sdma_run_channel0 - run a channel and wait till it's done 654 */ 655 static int sdma_run_channel0(struct sdma_engine *sdma) 656 { 657 int ret; 658 u32 reg; 659 660 sdma_enable_channel(sdma, 0); 661 662 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, 663 reg, !(reg & 1), 1, 500); 664 if (ret) 665 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 666 667 /* Set bits of CONFIG register with dynamic context switching */ 668 reg = readl(sdma->regs + SDMA_H_CONFIG); 669 if ((reg & SDMA_H_CONFIG_CSM) == 0) { 670 reg |= SDMA_H_CONFIG_CSM; 671 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); 672 } 673 674 return ret; 675 } 676 677 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 678 u32 address) 679 { 680 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 681 void *buf_virt; 682 dma_addr_t buf_phys; 683 int ret; 684 unsigned long flags; 685 686 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); 687 if (!buf_virt) { 688 return -ENOMEM; 689 } 690 691 spin_lock_irqsave(&sdma->channel_0_lock, flags); 692 693 bd0->mode.command = C0_SETPM; 694 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 695 bd0->mode.count = size / 2; 696 bd0->buffer_addr = buf_phys; 697 bd0->ext_buffer_addr = address; 698 699 memcpy(buf_virt, buf, size); 700 701 ret = sdma_run_channel0(sdma); 702 703 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 704 705 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); 706 707 return ret; 708 } 709 710 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 711 { 712 struct sdma_engine *sdma = sdmac->sdma; 713 int channel = sdmac->channel; 714 unsigned long val; 715 u32 chnenbl = chnenbl_ofs(sdma, event); 716 717 val = readl_relaxed(sdma->regs + chnenbl); 718 __set_bit(channel, &val); 719 writel_relaxed(val, sdma->regs + chnenbl); 720 } 721 722 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 723 { 724 struct sdma_engine *sdma = sdmac->sdma; 725 int channel = sdmac->channel; 726 u32 chnenbl = chnenbl_ofs(sdma, event); 727 unsigned long val; 728 729 val = readl_relaxed(sdma->regs + chnenbl); 730 __clear_bit(channel, &val); 731 writel_relaxed(val, sdma->regs + chnenbl); 732 } 733 734 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t) 735 { 736 return container_of(t, struct sdma_desc, vd.tx); 737 } 738 739 static void sdma_start_desc(struct sdma_channel *sdmac) 740 { 741 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); 742 struct sdma_desc *desc; 743 struct sdma_engine *sdma = sdmac->sdma; 744 int channel = sdmac->channel; 745 746 if (!vd) { 747 sdmac->desc = NULL; 748 return; 749 } 750 sdmac->desc = desc = to_sdma_desc(&vd->tx); 751 /* 752 * Do not delete the node in desc_issued list in cyclic mode, otherwise 753 * the desc allocated will never be freed in vchan_dma_desc_free_list 754 */ 755 if (!(sdmac->flags & IMX_DMA_SG_LOOP)) 756 list_del(&vd->node); 757 758 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; 759 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; 760 sdma_enable_channel(sdma, sdmac->channel); 761 } 762 763 static void sdma_update_channel_loop(struct sdma_channel *sdmac) 764 { 765 struct sdma_buffer_descriptor *bd; 766 int error = 0; 767 enum dma_status old_status = sdmac->status; 768 769 /* 770 * loop mode. Iterate over descriptors, re-setup them and 771 * call callback function. 772 */ 773 while (sdmac->desc) { 774 struct sdma_desc *desc = sdmac->desc; 775 776 bd = &desc->bd[desc->buf_tail]; 777 778 if (bd->mode.status & BD_DONE) 779 break; 780 781 if (bd->mode.status & BD_RROR) { 782 bd->mode.status &= ~BD_RROR; 783 sdmac->status = DMA_ERROR; 784 error = -EIO; 785 } 786 787 /* 788 * We use bd->mode.count to calculate the residue, since contains 789 * the number of bytes present in the current buffer descriptor. 790 */ 791 792 desc->chn_real_count = bd->mode.count; 793 bd->mode.status |= BD_DONE; 794 bd->mode.count = desc->period_len; 795 desc->buf_ptail = desc->buf_tail; 796 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; 797 798 /* 799 * The callback is called from the interrupt context in order 800 * to reduce latency and to avoid the risk of altering the 801 * SDMA transaction status by the time the client tasklet is 802 * executed. 803 */ 804 spin_unlock(&sdmac->vc.lock); 805 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); 806 spin_lock(&sdmac->vc.lock); 807 808 if (error) 809 sdmac->status = old_status; 810 } 811 } 812 813 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data) 814 { 815 struct sdma_channel *sdmac = (struct sdma_channel *) data; 816 struct sdma_buffer_descriptor *bd; 817 int i, error = 0; 818 819 sdmac->desc->chn_real_count = 0; 820 /* 821 * non loop mode. Iterate over all descriptors, collect 822 * errors and call callback function 823 */ 824 for (i = 0; i < sdmac->desc->num_bd; i++) { 825 bd = &sdmac->desc->bd[i]; 826 827 if (bd->mode.status & (BD_DONE | BD_RROR)) 828 error = -EIO; 829 sdmac->desc->chn_real_count += bd->mode.count; 830 } 831 832 if (error) 833 sdmac->status = DMA_ERROR; 834 else 835 sdmac->status = DMA_COMPLETE; 836 } 837 838 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 839 { 840 struct sdma_engine *sdma = dev_id; 841 unsigned long stat; 842 843 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 844 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 845 /* channel 0 is special and not handled here, see run_channel0() */ 846 stat &= ~1; 847 848 while (stat) { 849 int channel = fls(stat) - 1; 850 struct sdma_channel *sdmac = &sdma->channel[channel]; 851 struct sdma_desc *desc; 852 853 spin_lock(&sdmac->vc.lock); 854 desc = sdmac->desc; 855 if (desc) { 856 if (sdmac->flags & IMX_DMA_SG_LOOP) { 857 sdma_update_channel_loop(sdmac); 858 } else { 859 mxc_sdma_handle_channel_normal(sdmac); 860 vchan_cookie_complete(&desc->vd); 861 sdma_start_desc(sdmac); 862 } 863 } 864 865 spin_unlock(&sdmac->vc.lock); 866 __clear_bit(channel, &stat); 867 } 868 869 return IRQ_HANDLED; 870 } 871 872 /* 873 * sets the pc of SDMA script according to the peripheral type 874 */ 875 static void sdma_get_pc(struct sdma_channel *sdmac, 876 enum sdma_peripheral_type peripheral_type) 877 { 878 struct sdma_engine *sdma = sdmac->sdma; 879 int per_2_emi = 0, emi_2_per = 0; 880 /* 881 * These are needed once we start to support transfers between 882 * two peripherals or memory-to-memory transfers 883 */ 884 int per_2_per = 0, emi_2_emi = 0; 885 886 sdmac->pc_from_device = 0; 887 sdmac->pc_to_device = 0; 888 sdmac->device_to_device = 0; 889 sdmac->pc_to_pc = 0; 890 891 switch (peripheral_type) { 892 case IMX_DMATYPE_MEMORY: 893 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 894 break; 895 case IMX_DMATYPE_DSP: 896 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 897 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 898 break; 899 case IMX_DMATYPE_FIRI: 900 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 901 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 902 break; 903 case IMX_DMATYPE_UART: 904 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 905 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 906 break; 907 case IMX_DMATYPE_UART_SP: 908 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 909 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 910 break; 911 case IMX_DMATYPE_ATA: 912 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 913 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 914 break; 915 case IMX_DMATYPE_CSPI: 916 case IMX_DMATYPE_EXT: 917 case IMX_DMATYPE_SSI: 918 case IMX_DMATYPE_SAI: 919 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 920 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 921 break; 922 case IMX_DMATYPE_SSI_DUAL: 923 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 924 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 925 break; 926 case IMX_DMATYPE_SSI_SP: 927 case IMX_DMATYPE_MMC: 928 case IMX_DMATYPE_SDHC: 929 case IMX_DMATYPE_CSPI_SP: 930 case IMX_DMATYPE_ESAI: 931 case IMX_DMATYPE_MSHC_SP: 932 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 933 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 934 break; 935 case IMX_DMATYPE_ASRC: 936 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 937 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 938 per_2_per = sdma->script_addrs->per_2_per_addr; 939 break; 940 case IMX_DMATYPE_ASRC_SP: 941 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 942 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 943 per_2_per = sdma->script_addrs->per_2_per_addr; 944 break; 945 case IMX_DMATYPE_MSHC: 946 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 947 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 948 break; 949 case IMX_DMATYPE_CCM: 950 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 951 break; 952 case IMX_DMATYPE_SPDIF: 953 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 954 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 955 break; 956 case IMX_DMATYPE_IPU_MEMORY: 957 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 958 break; 959 default: 960 break; 961 } 962 963 sdmac->pc_from_device = per_2_emi; 964 sdmac->pc_to_device = emi_2_per; 965 sdmac->device_to_device = per_2_per; 966 sdmac->pc_to_pc = emi_2_emi; 967 } 968 969 static int sdma_load_context(struct sdma_channel *sdmac) 970 { 971 struct sdma_engine *sdma = sdmac->sdma; 972 int channel = sdmac->channel; 973 int load_address; 974 struct sdma_context_data *context = sdma->context; 975 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 976 int ret; 977 unsigned long flags; 978 979 if (sdmac->context_loaded) 980 return 0; 981 982 if (sdmac->direction == DMA_DEV_TO_MEM) 983 load_address = sdmac->pc_from_device; 984 else if (sdmac->direction == DMA_DEV_TO_DEV) 985 load_address = sdmac->device_to_device; 986 else if (sdmac->direction == DMA_MEM_TO_MEM) 987 load_address = sdmac->pc_to_pc; 988 else 989 load_address = sdmac->pc_to_device; 990 991 if (load_address < 0) 992 return load_address; 993 994 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 995 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 996 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 997 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 998 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 999 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 1000 1001 spin_lock_irqsave(&sdma->channel_0_lock, flags); 1002 1003 memset(context, 0, sizeof(*context)); 1004 context->channel_state.pc = load_address; 1005 1006 /* Send by context the event mask,base address for peripheral 1007 * and watermark level 1008 */ 1009 context->gReg[0] = sdmac->event_mask[1]; 1010 context->gReg[1] = sdmac->event_mask[0]; 1011 context->gReg[2] = sdmac->per_addr; 1012 context->gReg[6] = sdmac->shp_addr; 1013 context->gReg[7] = sdmac->watermark_level; 1014 1015 bd0->mode.command = C0_SETDM; 1016 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 1017 bd0->mode.count = sizeof(*context) / 4; 1018 bd0->buffer_addr = sdma->context_phys; 1019 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 1020 ret = sdma_run_channel0(sdma); 1021 1022 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 1023 1024 sdmac->context_loaded = true; 1025 1026 return ret; 1027 } 1028 1029 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 1030 { 1031 return container_of(chan, struct sdma_channel, vc.chan); 1032 } 1033 1034 static int sdma_disable_channel(struct dma_chan *chan) 1035 { 1036 struct sdma_channel *sdmac = to_sdma_chan(chan); 1037 struct sdma_engine *sdma = sdmac->sdma; 1038 int channel = sdmac->channel; 1039 1040 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 1041 sdmac->status = DMA_ERROR; 1042 1043 return 0; 1044 } 1045 static void sdma_channel_terminate_work(struct work_struct *work) 1046 { 1047 struct sdma_channel *sdmac = container_of(work, struct sdma_channel, 1048 terminate_worker); 1049 unsigned long flags; 1050 LIST_HEAD(head); 1051 1052 /* 1053 * According to NXP R&D team a delay of one BD SDMA cost time 1054 * (maximum is 1ms) should be added after disable of the channel 1055 * bit, to ensure SDMA core has really been stopped after SDMA 1056 * clients call .device_terminate_all. 1057 */ 1058 usleep_range(1000, 2000); 1059 1060 spin_lock_irqsave(&sdmac->vc.lock, flags); 1061 vchan_get_all_descriptors(&sdmac->vc, &head); 1062 sdmac->desc = NULL; 1063 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1064 vchan_dma_desc_free_list(&sdmac->vc, &head); 1065 sdmac->context_loaded = false; 1066 } 1067 1068 static int sdma_disable_channel_async(struct dma_chan *chan) 1069 { 1070 struct sdma_channel *sdmac = to_sdma_chan(chan); 1071 1072 sdma_disable_channel(chan); 1073 1074 if (sdmac->desc) 1075 schedule_work(&sdmac->terminate_worker); 1076 1077 return 0; 1078 } 1079 1080 static void sdma_channel_synchronize(struct dma_chan *chan) 1081 { 1082 struct sdma_channel *sdmac = to_sdma_chan(chan); 1083 1084 vchan_synchronize(&sdmac->vc); 1085 1086 flush_work(&sdmac->terminate_worker); 1087 } 1088 1089 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) 1090 { 1091 struct sdma_engine *sdma = sdmac->sdma; 1092 1093 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; 1094 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; 1095 1096 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); 1097 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); 1098 1099 if (sdmac->event_id0 > 31) 1100 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; 1101 1102 if (sdmac->event_id1 > 31) 1103 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; 1104 1105 /* 1106 * If LWML(src_maxburst) > HWML(dst_maxburst), we need 1107 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap 1108 * r0(event_mask[1]) and r1(event_mask[0]). 1109 */ 1110 if (lwml > hwml) { 1111 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | 1112 SDMA_WATERMARK_LEVEL_HWML); 1113 sdmac->watermark_level |= hwml; 1114 sdmac->watermark_level |= lwml << 16; 1115 swap(sdmac->event_mask[0], sdmac->event_mask[1]); 1116 } 1117 1118 if (sdmac->per_address2 >= sdma->spba_start_addr && 1119 sdmac->per_address2 <= sdma->spba_end_addr) 1120 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; 1121 1122 if (sdmac->per_address >= sdma->spba_start_addr && 1123 sdmac->per_address <= sdma->spba_end_addr) 1124 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; 1125 1126 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; 1127 } 1128 1129 static int sdma_config_channel(struct dma_chan *chan) 1130 { 1131 struct sdma_channel *sdmac = to_sdma_chan(chan); 1132 int ret; 1133 1134 sdma_disable_channel(chan); 1135 1136 sdmac->event_mask[0] = 0; 1137 sdmac->event_mask[1] = 0; 1138 sdmac->shp_addr = 0; 1139 sdmac->per_addr = 0; 1140 1141 switch (sdmac->peripheral_type) { 1142 case IMX_DMATYPE_DSP: 1143 sdma_config_ownership(sdmac, false, true, true); 1144 break; 1145 case IMX_DMATYPE_MEMORY: 1146 sdma_config_ownership(sdmac, false, true, false); 1147 break; 1148 default: 1149 sdma_config_ownership(sdmac, true, true, false); 1150 break; 1151 } 1152 1153 sdma_get_pc(sdmac, sdmac->peripheral_type); 1154 1155 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 1156 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 1157 /* Handle multiple event channels differently */ 1158 if (sdmac->event_id1) { 1159 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || 1160 sdmac->peripheral_type == IMX_DMATYPE_ASRC) 1161 sdma_set_watermarklevel_for_p2p(sdmac); 1162 } else 1163 __set_bit(sdmac->event_id0, sdmac->event_mask); 1164 1165 /* Address */ 1166 sdmac->shp_addr = sdmac->per_address; 1167 sdmac->per_addr = sdmac->per_address2; 1168 } else { 1169 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 1170 } 1171 1172 ret = sdma_load_context(sdmac); 1173 1174 return ret; 1175 } 1176 1177 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 1178 unsigned int priority) 1179 { 1180 struct sdma_engine *sdma = sdmac->sdma; 1181 int channel = sdmac->channel; 1182 1183 if (priority < MXC_SDMA_MIN_PRIORITY 1184 || priority > MXC_SDMA_MAX_PRIORITY) { 1185 return -EINVAL; 1186 } 1187 1188 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 1189 1190 return 0; 1191 } 1192 1193 static int sdma_request_channel0(struct sdma_engine *sdma) 1194 { 1195 int ret = -EBUSY; 1196 1197 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, 1198 GFP_NOWAIT); 1199 if (!sdma->bd0) { 1200 ret = -ENOMEM; 1201 goto out; 1202 } 1203 1204 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; 1205 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; 1206 1207 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); 1208 return 0; 1209 out: 1210 1211 return ret; 1212 } 1213 1214 1215 static int sdma_alloc_bd(struct sdma_desc *desc) 1216 { 1217 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1218 int ret = 0; 1219 1220 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, 1221 &desc->bd_phys, GFP_NOWAIT); 1222 if (!desc->bd) { 1223 ret = -ENOMEM; 1224 goto out; 1225 } 1226 out: 1227 return ret; 1228 } 1229 1230 static void sdma_free_bd(struct sdma_desc *desc) 1231 { 1232 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1233 1234 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, 1235 desc->bd_phys); 1236 } 1237 1238 static void sdma_desc_free(struct virt_dma_desc *vd) 1239 { 1240 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd); 1241 1242 sdma_free_bd(desc); 1243 kfree(desc); 1244 } 1245 1246 static int sdma_alloc_chan_resources(struct dma_chan *chan) 1247 { 1248 struct sdma_channel *sdmac = to_sdma_chan(chan); 1249 struct imx_dma_data *data = chan->private; 1250 struct imx_dma_data mem_data; 1251 int prio, ret; 1252 1253 /* 1254 * MEMCPY may never setup chan->private by filter function such as 1255 * dmatest, thus create 'struct imx_dma_data mem_data' for this case. 1256 * Please note in any other slave case, you have to setup chan->private 1257 * with 'struct imx_dma_data' in your own filter function if you want to 1258 * request dma channel by dma_request_channel() rather than 1259 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear 1260 * to warn you to correct your filter function. 1261 */ 1262 if (!data) { 1263 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); 1264 mem_data.priority = 2; 1265 mem_data.peripheral_type = IMX_DMATYPE_MEMORY; 1266 mem_data.dma_request = 0; 1267 mem_data.dma_request2 = 0; 1268 data = &mem_data; 1269 1270 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); 1271 } 1272 1273 switch (data->priority) { 1274 case DMA_PRIO_HIGH: 1275 prio = 3; 1276 break; 1277 case DMA_PRIO_MEDIUM: 1278 prio = 2; 1279 break; 1280 case DMA_PRIO_LOW: 1281 default: 1282 prio = 1; 1283 break; 1284 } 1285 1286 sdmac->peripheral_type = data->peripheral_type; 1287 sdmac->event_id0 = data->dma_request; 1288 sdmac->event_id1 = data->dma_request2; 1289 1290 ret = clk_enable(sdmac->sdma->clk_ipg); 1291 if (ret) 1292 return ret; 1293 ret = clk_enable(sdmac->sdma->clk_ahb); 1294 if (ret) 1295 goto disable_clk_ipg; 1296 1297 ret = sdma_set_channel_priority(sdmac, prio); 1298 if (ret) 1299 goto disable_clk_ahb; 1300 1301 return 0; 1302 1303 disable_clk_ahb: 1304 clk_disable(sdmac->sdma->clk_ahb); 1305 disable_clk_ipg: 1306 clk_disable(sdmac->sdma->clk_ipg); 1307 return ret; 1308 } 1309 1310 static void sdma_free_chan_resources(struct dma_chan *chan) 1311 { 1312 struct sdma_channel *sdmac = to_sdma_chan(chan); 1313 struct sdma_engine *sdma = sdmac->sdma; 1314 1315 sdma_disable_channel_async(chan); 1316 1317 sdma_channel_synchronize(chan); 1318 1319 if (sdmac->event_id0) 1320 sdma_event_disable(sdmac, sdmac->event_id0); 1321 if (sdmac->event_id1) 1322 sdma_event_disable(sdmac, sdmac->event_id1); 1323 1324 sdmac->event_id0 = 0; 1325 sdmac->event_id1 = 0; 1326 1327 sdma_set_channel_priority(sdmac, 0); 1328 1329 clk_disable(sdma->clk_ipg); 1330 clk_disable(sdma->clk_ahb); 1331 } 1332 1333 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, 1334 enum dma_transfer_direction direction, u32 bds) 1335 { 1336 struct sdma_desc *desc; 1337 1338 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); 1339 if (!desc) 1340 goto err_out; 1341 1342 sdmac->status = DMA_IN_PROGRESS; 1343 sdmac->direction = direction; 1344 sdmac->flags = 0; 1345 1346 desc->chn_count = 0; 1347 desc->chn_real_count = 0; 1348 desc->buf_tail = 0; 1349 desc->buf_ptail = 0; 1350 desc->sdmac = sdmac; 1351 desc->num_bd = bds; 1352 1353 if (sdma_alloc_bd(desc)) 1354 goto err_desc_out; 1355 1356 /* No slave_config called in MEMCPY case, so do here */ 1357 if (direction == DMA_MEM_TO_MEM) 1358 sdma_config_ownership(sdmac, false, true, false); 1359 1360 if (sdma_load_context(sdmac)) 1361 goto err_desc_out; 1362 1363 return desc; 1364 1365 err_desc_out: 1366 kfree(desc); 1367 err_out: 1368 return NULL; 1369 } 1370 1371 static struct dma_async_tx_descriptor *sdma_prep_memcpy( 1372 struct dma_chan *chan, dma_addr_t dma_dst, 1373 dma_addr_t dma_src, size_t len, unsigned long flags) 1374 { 1375 struct sdma_channel *sdmac = to_sdma_chan(chan); 1376 struct sdma_engine *sdma = sdmac->sdma; 1377 int channel = sdmac->channel; 1378 size_t count; 1379 int i = 0, param; 1380 struct sdma_buffer_descriptor *bd; 1381 struct sdma_desc *desc; 1382 1383 if (!chan || !len) 1384 return NULL; 1385 1386 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", 1387 &dma_src, &dma_dst, len, channel); 1388 1389 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, 1390 len / SDMA_BD_MAX_CNT + 1); 1391 if (!desc) 1392 return NULL; 1393 1394 do { 1395 count = min_t(size_t, len, SDMA_BD_MAX_CNT); 1396 bd = &desc->bd[i]; 1397 bd->buffer_addr = dma_src; 1398 bd->ext_buffer_addr = dma_dst; 1399 bd->mode.count = count; 1400 desc->chn_count += count; 1401 bd->mode.command = 0; 1402 1403 dma_src += count; 1404 dma_dst += count; 1405 len -= count; 1406 i++; 1407 1408 param = BD_DONE | BD_EXTD | BD_CONT; 1409 /* last bd */ 1410 if (!len) { 1411 param |= BD_INTR; 1412 param |= BD_LAST; 1413 param &= ~BD_CONT; 1414 } 1415 1416 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", 1417 i, count, bd->buffer_addr, 1418 param & BD_WRAP ? "wrap" : "", 1419 param & BD_INTR ? " intr" : ""); 1420 1421 bd->mode.status = param; 1422 } while (len); 1423 1424 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1425 } 1426 1427 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1428 struct dma_chan *chan, struct scatterlist *sgl, 1429 unsigned int sg_len, enum dma_transfer_direction direction, 1430 unsigned long flags, void *context) 1431 { 1432 struct sdma_channel *sdmac = to_sdma_chan(chan); 1433 struct sdma_engine *sdma = sdmac->sdma; 1434 int i, count; 1435 int channel = sdmac->channel; 1436 struct scatterlist *sg; 1437 struct sdma_desc *desc; 1438 1439 sdma_config_write(chan, &sdmac->slave_config, direction); 1440 1441 desc = sdma_transfer_init(sdmac, direction, sg_len); 1442 if (!desc) 1443 goto err_out; 1444 1445 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1446 sg_len, channel); 1447 1448 for_each_sg(sgl, sg, sg_len, i) { 1449 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1450 int param; 1451 1452 bd->buffer_addr = sg->dma_address; 1453 1454 count = sg_dma_len(sg); 1455 1456 if (count > SDMA_BD_MAX_CNT) { 1457 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1458 channel, count, SDMA_BD_MAX_CNT); 1459 goto err_bd_out; 1460 } 1461 1462 bd->mode.count = count; 1463 desc->chn_count += count; 1464 1465 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1466 goto err_bd_out; 1467 1468 switch (sdmac->word_size) { 1469 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1470 bd->mode.command = 0; 1471 if (count & 3 || sg->dma_address & 3) 1472 goto err_bd_out; 1473 break; 1474 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1475 bd->mode.command = 2; 1476 if (count & 1 || sg->dma_address & 1) 1477 goto err_bd_out; 1478 break; 1479 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1480 bd->mode.command = 1; 1481 break; 1482 default: 1483 goto err_bd_out; 1484 } 1485 1486 param = BD_DONE | BD_EXTD | BD_CONT; 1487 1488 if (i + 1 == sg_len) { 1489 param |= BD_INTR; 1490 param |= BD_LAST; 1491 param &= ~BD_CONT; 1492 } 1493 1494 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1495 i, count, (u64)sg->dma_address, 1496 param & BD_WRAP ? "wrap" : "", 1497 param & BD_INTR ? " intr" : ""); 1498 1499 bd->mode.status = param; 1500 } 1501 1502 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1503 err_bd_out: 1504 sdma_free_bd(desc); 1505 kfree(desc); 1506 err_out: 1507 sdmac->status = DMA_ERROR; 1508 return NULL; 1509 } 1510 1511 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1512 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1513 size_t period_len, enum dma_transfer_direction direction, 1514 unsigned long flags) 1515 { 1516 struct sdma_channel *sdmac = to_sdma_chan(chan); 1517 struct sdma_engine *sdma = sdmac->sdma; 1518 int num_periods = buf_len / period_len; 1519 int channel = sdmac->channel; 1520 int i = 0, buf = 0; 1521 struct sdma_desc *desc; 1522 1523 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1524 1525 sdma_config_write(chan, &sdmac->slave_config, direction); 1526 1527 desc = sdma_transfer_init(sdmac, direction, num_periods); 1528 if (!desc) 1529 goto err_out; 1530 1531 desc->period_len = period_len; 1532 1533 sdmac->flags |= IMX_DMA_SG_LOOP; 1534 1535 if (period_len > SDMA_BD_MAX_CNT) { 1536 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", 1537 channel, period_len, SDMA_BD_MAX_CNT); 1538 goto err_bd_out; 1539 } 1540 1541 while (buf < buf_len) { 1542 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1543 int param; 1544 1545 bd->buffer_addr = dma_addr; 1546 1547 bd->mode.count = period_len; 1548 1549 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1550 goto err_bd_out; 1551 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1552 bd->mode.command = 0; 1553 else 1554 bd->mode.command = sdmac->word_size; 1555 1556 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1557 if (i + 1 == num_periods) 1558 param |= BD_WRAP; 1559 1560 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", 1561 i, period_len, (u64)dma_addr, 1562 param & BD_WRAP ? "wrap" : "", 1563 param & BD_INTR ? " intr" : ""); 1564 1565 bd->mode.status = param; 1566 1567 dma_addr += period_len; 1568 buf += period_len; 1569 1570 i++; 1571 } 1572 1573 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1574 err_bd_out: 1575 sdma_free_bd(desc); 1576 kfree(desc); 1577 err_out: 1578 sdmac->status = DMA_ERROR; 1579 return NULL; 1580 } 1581 1582 static int sdma_config_write(struct dma_chan *chan, 1583 struct dma_slave_config *dmaengine_cfg, 1584 enum dma_transfer_direction direction) 1585 { 1586 struct sdma_channel *sdmac = to_sdma_chan(chan); 1587 1588 if (direction == DMA_DEV_TO_MEM) { 1589 sdmac->per_address = dmaengine_cfg->src_addr; 1590 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1591 dmaengine_cfg->src_addr_width; 1592 sdmac->word_size = dmaengine_cfg->src_addr_width; 1593 } else if (direction == DMA_DEV_TO_DEV) { 1594 sdmac->per_address2 = dmaengine_cfg->src_addr; 1595 sdmac->per_address = dmaengine_cfg->dst_addr; 1596 sdmac->watermark_level = dmaengine_cfg->src_maxburst & 1597 SDMA_WATERMARK_LEVEL_LWML; 1598 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & 1599 SDMA_WATERMARK_LEVEL_HWML; 1600 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1601 } else { 1602 sdmac->per_address = dmaengine_cfg->dst_addr; 1603 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1604 dmaengine_cfg->dst_addr_width; 1605 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1606 } 1607 sdmac->direction = direction; 1608 return sdma_config_channel(chan); 1609 } 1610 1611 static int sdma_config(struct dma_chan *chan, 1612 struct dma_slave_config *dmaengine_cfg) 1613 { 1614 struct sdma_channel *sdmac = to_sdma_chan(chan); 1615 1616 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); 1617 1618 /* Set ENBLn earlier to make sure dma request triggered after that */ 1619 if (sdmac->event_id0) { 1620 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 1621 return -EINVAL; 1622 sdma_event_enable(sdmac, sdmac->event_id0); 1623 } 1624 1625 if (sdmac->event_id1) { 1626 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) 1627 return -EINVAL; 1628 sdma_event_enable(sdmac, sdmac->event_id1); 1629 } 1630 1631 return 0; 1632 } 1633 1634 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1635 dma_cookie_t cookie, 1636 struct dma_tx_state *txstate) 1637 { 1638 struct sdma_channel *sdmac = to_sdma_chan(chan); 1639 struct sdma_desc *desc; 1640 u32 residue; 1641 struct virt_dma_desc *vd; 1642 enum dma_status ret; 1643 unsigned long flags; 1644 1645 ret = dma_cookie_status(chan, cookie, txstate); 1646 if (ret == DMA_COMPLETE || !txstate) 1647 return ret; 1648 1649 spin_lock_irqsave(&sdmac->vc.lock, flags); 1650 vd = vchan_find_desc(&sdmac->vc, cookie); 1651 if (vd) { 1652 desc = to_sdma_desc(&vd->tx); 1653 if (sdmac->flags & IMX_DMA_SG_LOOP) 1654 residue = (desc->num_bd - desc->buf_ptail) * 1655 desc->period_len - desc->chn_real_count; 1656 else 1657 residue = desc->chn_count - desc->chn_real_count; 1658 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) { 1659 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count; 1660 } else { 1661 residue = 0; 1662 } 1663 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1664 1665 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1666 residue); 1667 1668 return sdmac->status; 1669 } 1670 1671 static void sdma_issue_pending(struct dma_chan *chan) 1672 { 1673 struct sdma_channel *sdmac = to_sdma_chan(chan); 1674 unsigned long flags; 1675 1676 spin_lock_irqsave(&sdmac->vc.lock, flags); 1677 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) 1678 sdma_start_desc(sdmac); 1679 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1680 } 1681 1682 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1683 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1684 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 1685 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 1686 1687 static void sdma_add_scripts(struct sdma_engine *sdma, 1688 const struct sdma_script_start_addrs *addr) 1689 { 1690 s32 *addr_arr = (u32 *)addr; 1691 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1692 int i; 1693 1694 /* use the default firmware in ROM if missing external firmware */ 1695 if (!sdma->script_number) 1696 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1697 1698 for (i = 0; i < sdma->script_number; i++) 1699 if (addr_arr[i] > 0) 1700 saddr_arr[i] = addr_arr[i]; 1701 } 1702 1703 static void sdma_load_firmware(const struct firmware *fw, void *context) 1704 { 1705 struct sdma_engine *sdma = context; 1706 const struct sdma_firmware_header *header; 1707 const struct sdma_script_start_addrs *addr; 1708 unsigned short *ram_code; 1709 1710 if (!fw) { 1711 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); 1712 /* In this case we just use the ROM firmware. */ 1713 return; 1714 } 1715 1716 if (fw->size < sizeof(*header)) 1717 goto err_firmware; 1718 1719 header = (struct sdma_firmware_header *)fw->data; 1720 1721 if (header->magic != SDMA_FIRMWARE_MAGIC) 1722 goto err_firmware; 1723 if (header->ram_code_start + header->ram_code_size > fw->size) 1724 goto err_firmware; 1725 switch (header->version_major) { 1726 case 1: 1727 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1728 break; 1729 case 2: 1730 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1731 break; 1732 case 3: 1733 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; 1734 break; 1735 case 4: 1736 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; 1737 break; 1738 default: 1739 dev_err(sdma->dev, "unknown firmware version\n"); 1740 goto err_firmware; 1741 } 1742 1743 addr = (void *)header + header->script_addrs_start; 1744 ram_code = (void *)header + header->ram_code_start; 1745 1746 clk_enable(sdma->clk_ipg); 1747 clk_enable(sdma->clk_ahb); 1748 /* download the RAM image for SDMA */ 1749 sdma_load_script(sdma, ram_code, 1750 header->ram_code_size, 1751 addr->ram_code_start_addr); 1752 clk_disable(sdma->clk_ipg); 1753 clk_disable(sdma->clk_ahb); 1754 1755 sdma_add_scripts(sdma, addr); 1756 1757 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1758 header->version_major, 1759 header->version_minor); 1760 1761 err_firmware: 1762 release_firmware(fw); 1763 } 1764 1765 #define EVENT_REMAP_CELLS 3 1766 1767 static int sdma_event_remap(struct sdma_engine *sdma) 1768 { 1769 struct device_node *np = sdma->dev->of_node; 1770 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); 1771 struct property *event_remap; 1772 struct regmap *gpr; 1773 char propname[] = "fsl,sdma-event-remap"; 1774 u32 reg, val, shift, num_map, i; 1775 int ret = 0; 1776 1777 if (IS_ERR(np) || IS_ERR(gpr_np)) 1778 goto out; 1779 1780 event_remap = of_find_property(np, propname, NULL); 1781 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; 1782 if (!num_map) { 1783 dev_dbg(sdma->dev, "no event needs to be remapped\n"); 1784 goto out; 1785 } else if (num_map % EVENT_REMAP_CELLS) { 1786 dev_err(sdma->dev, "the property %s must modulo %d\n", 1787 propname, EVENT_REMAP_CELLS); 1788 ret = -EINVAL; 1789 goto out; 1790 } 1791 1792 gpr = syscon_node_to_regmap(gpr_np); 1793 if (IS_ERR(gpr)) { 1794 dev_err(sdma->dev, "failed to get gpr regmap\n"); 1795 ret = PTR_ERR(gpr); 1796 goto out; 1797 } 1798 1799 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { 1800 ret = of_property_read_u32_index(np, propname, i, ®); 1801 if (ret) { 1802 dev_err(sdma->dev, "failed to read property %s index %d\n", 1803 propname, i); 1804 goto out; 1805 } 1806 1807 ret = of_property_read_u32_index(np, propname, i + 1, &shift); 1808 if (ret) { 1809 dev_err(sdma->dev, "failed to read property %s index %d\n", 1810 propname, i + 1); 1811 goto out; 1812 } 1813 1814 ret = of_property_read_u32_index(np, propname, i + 2, &val); 1815 if (ret) { 1816 dev_err(sdma->dev, "failed to read property %s index %d\n", 1817 propname, i + 2); 1818 goto out; 1819 } 1820 1821 regmap_update_bits(gpr, reg, BIT(shift), val << shift); 1822 } 1823 1824 out: 1825 if (!IS_ERR(gpr_np)) 1826 of_node_put(gpr_np); 1827 1828 return ret; 1829 } 1830 1831 static int sdma_get_firmware(struct sdma_engine *sdma, 1832 const char *fw_name) 1833 { 1834 int ret; 1835 1836 ret = request_firmware_nowait(THIS_MODULE, 1837 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1838 GFP_KERNEL, sdma, sdma_load_firmware); 1839 1840 return ret; 1841 } 1842 1843 static int sdma_init(struct sdma_engine *sdma) 1844 { 1845 int i, ret; 1846 dma_addr_t ccb_phys; 1847 1848 ret = clk_enable(sdma->clk_ipg); 1849 if (ret) 1850 return ret; 1851 ret = clk_enable(sdma->clk_ahb); 1852 if (ret) 1853 goto disable_clk_ipg; 1854 1855 if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)) 1856 sdma->clk_ratio = 1; 1857 1858 /* Be sure SDMA has not started yet */ 1859 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1860 1861 sdma->channel_control = dma_alloc_coherent(sdma->dev, 1862 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1863 sizeof(struct sdma_context_data), 1864 &ccb_phys, GFP_KERNEL); 1865 1866 if (!sdma->channel_control) { 1867 ret = -ENOMEM; 1868 goto err_dma_alloc; 1869 } 1870 1871 sdma->context = (void *)sdma->channel_control + 1872 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1873 sdma->context_phys = ccb_phys + 1874 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1875 1876 /* Zero-out the CCB structures array just allocated */ 1877 memset(sdma->channel_control, 0, 1878 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1879 1880 /* disable all channels */ 1881 for (i = 0; i < sdma->drvdata->num_events; i++) 1882 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1883 1884 /* All channels have priority 0 */ 1885 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1886 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1887 1888 ret = sdma_request_channel0(sdma); 1889 if (ret) 1890 goto err_dma_alloc; 1891 1892 sdma_config_ownership(&sdma->channel[0], false, true, false); 1893 1894 /* Set Command Channel (Channel Zero) */ 1895 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1896 1897 /* Set bits of CONFIG register but with static context switching */ 1898 if (sdma->clk_ratio) 1899 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); 1900 else 1901 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1902 1903 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1904 1905 /* Initializes channel's priorities */ 1906 sdma_set_channel_priority(&sdma->channel[0], 7); 1907 1908 clk_disable(sdma->clk_ipg); 1909 clk_disable(sdma->clk_ahb); 1910 1911 return 0; 1912 1913 err_dma_alloc: 1914 clk_disable(sdma->clk_ahb); 1915 disable_clk_ipg: 1916 clk_disable(sdma->clk_ipg); 1917 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1918 return ret; 1919 } 1920 1921 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1922 { 1923 struct sdma_channel *sdmac = to_sdma_chan(chan); 1924 struct sdma_engine *sdma = sdmac->sdma; 1925 struct imx_dma_data *data = fn_param; 1926 1927 if (!imx_dma_is_general_purpose(chan)) 1928 return false; 1929 1930 /* return false if it's not the right device */ 1931 if (sdma->dev->of_node != data->of_node) 1932 return false; 1933 1934 sdmac->data = *data; 1935 chan->private = &sdmac->data; 1936 1937 return true; 1938 } 1939 1940 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1941 struct of_dma *ofdma) 1942 { 1943 struct sdma_engine *sdma = ofdma->of_dma_data; 1944 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1945 struct imx_dma_data data; 1946 1947 if (dma_spec->args_count != 3) 1948 return NULL; 1949 1950 data.dma_request = dma_spec->args[0]; 1951 data.peripheral_type = dma_spec->args[1]; 1952 data.priority = dma_spec->args[2]; 1953 /* 1954 * init dma_request2 to zero, which is not used by the dts. 1955 * For P2P, dma_request2 is init from dma_request_channel(), 1956 * chan->private will point to the imx_dma_data, and in 1957 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will 1958 * be set to sdmac->event_id1. 1959 */ 1960 data.dma_request2 = 0; 1961 data.of_node = ofdma->of_node; 1962 1963 return dma_request_channel(mask, sdma_filter_fn, &data); 1964 } 1965 1966 static int sdma_probe(struct platform_device *pdev) 1967 { 1968 const struct of_device_id *of_id = 1969 of_match_device(sdma_dt_ids, &pdev->dev); 1970 struct device_node *np = pdev->dev.of_node; 1971 struct device_node *spba_bus; 1972 const char *fw_name; 1973 int ret; 1974 int irq; 1975 struct resource *iores; 1976 struct resource spba_res; 1977 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1978 int i; 1979 struct sdma_engine *sdma; 1980 s32 *saddr_arr; 1981 const struct sdma_driver_data *drvdata = NULL; 1982 1983 if (of_id) 1984 drvdata = of_id->data; 1985 else if (pdev->id_entry) 1986 drvdata = (void *)pdev->id_entry->driver_data; 1987 1988 if (!drvdata) { 1989 dev_err(&pdev->dev, "unable to find driver data\n"); 1990 return -EINVAL; 1991 } 1992 1993 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1994 if (ret) 1995 return ret; 1996 1997 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); 1998 if (!sdma) 1999 return -ENOMEM; 2000 2001 spin_lock_init(&sdma->channel_0_lock); 2002 2003 sdma->dev = &pdev->dev; 2004 sdma->drvdata = drvdata; 2005 2006 irq = platform_get_irq(pdev, 0); 2007 if (irq < 0) 2008 return irq; 2009 2010 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2011 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); 2012 if (IS_ERR(sdma->regs)) 2013 return PTR_ERR(sdma->regs); 2014 2015 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2016 if (IS_ERR(sdma->clk_ipg)) 2017 return PTR_ERR(sdma->clk_ipg); 2018 2019 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2020 if (IS_ERR(sdma->clk_ahb)) 2021 return PTR_ERR(sdma->clk_ahb); 2022 2023 ret = clk_prepare(sdma->clk_ipg); 2024 if (ret) 2025 return ret; 2026 2027 ret = clk_prepare(sdma->clk_ahb); 2028 if (ret) 2029 goto err_clk; 2030 2031 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", 2032 sdma); 2033 if (ret) 2034 goto err_irq; 2035 2036 sdma->irq = irq; 2037 2038 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 2039 if (!sdma->script_addrs) { 2040 ret = -ENOMEM; 2041 goto err_irq; 2042 } 2043 2044 /* initially no scripts available */ 2045 saddr_arr = (s32 *)sdma->script_addrs; 2046 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 2047 saddr_arr[i] = -EINVAL; 2048 2049 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 2050 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 2051 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); 2052 2053 INIT_LIST_HEAD(&sdma->dma_device.channels); 2054 /* Initialize channel parameters */ 2055 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2056 struct sdma_channel *sdmac = &sdma->channel[i]; 2057 2058 sdmac->sdma = sdma; 2059 2060 sdmac->channel = i; 2061 sdmac->vc.desc_free = sdma_desc_free; 2062 INIT_WORK(&sdmac->terminate_worker, 2063 sdma_channel_terminate_work); 2064 /* 2065 * Add the channel to the DMAC list. Do not add channel 0 though 2066 * because we need it internally in the SDMA driver. This also means 2067 * that channel 0 in dmaengine counting matches sdma channel 1. 2068 */ 2069 if (i) 2070 vchan_init(&sdmac->vc, &sdma->dma_device); 2071 } 2072 2073 ret = sdma_init(sdma); 2074 if (ret) 2075 goto err_init; 2076 2077 ret = sdma_event_remap(sdma); 2078 if (ret) 2079 goto err_init; 2080 2081 if (sdma->drvdata->script_addrs) 2082 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 2083 if (pdata && pdata->script_addrs) 2084 sdma_add_scripts(sdma, pdata->script_addrs); 2085 2086 if (pdata) { 2087 ret = sdma_get_firmware(sdma, pdata->fw_name); 2088 if (ret) 2089 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 2090 } else { 2091 /* 2092 * Because that device tree does not encode ROM script address, 2093 * the RAM script in firmware is mandatory for device tree 2094 * probe, otherwise it fails. 2095 */ 2096 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 2097 &fw_name); 2098 if (ret) 2099 dev_warn(&pdev->dev, "failed to get firmware name\n"); 2100 else { 2101 ret = sdma_get_firmware(sdma, fw_name); 2102 if (ret) 2103 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 2104 } 2105 } 2106 2107 sdma->dma_device.dev = &pdev->dev; 2108 2109 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 2110 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 2111 sdma->dma_device.device_tx_status = sdma_tx_status; 2112 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 2113 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 2114 sdma->dma_device.device_config = sdma_config; 2115 sdma->dma_device.device_terminate_all = sdma_disable_channel_async; 2116 sdma->dma_device.device_synchronize = sdma_channel_synchronize; 2117 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; 2118 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; 2119 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; 2120 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2121 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; 2122 sdma->dma_device.device_issue_pending = sdma_issue_pending; 2123 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 2124 sdma->dma_device.copy_align = 2; 2125 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); 2126 2127 platform_set_drvdata(pdev, sdma); 2128 2129 ret = dma_async_device_register(&sdma->dma_device); 2130 if (ret) { 2131 dev_err(&pdev->dev, "unable to register\n"); 2132 goto err_init; 2133 } 2134 2135 if (np) { 2136 ret = of_dma_controller_register(np, sdma_xlate, sdma); 2137 if (ret) { 2138 dev_err(&pdev->dev, "failed to register controller\n"); 2139 goto err_register; 2140 } 2141 2142 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); 2143 ret = of_address_to_resource(spba_bus, 0, &spba_res); 2144 if (!ret) { 2145 sdma->spba_start_addr = spba_res.start; 2146 sdma->spba_end_addr = spba_res.end; 2147 } 2148 of_node_put(spba_bus); 2149 } 2150 2151 return 0; 2152 2153 err_register: 2154 dma_async_device_unregister(&sdma->dma_device); 2155 err_init: 2156 kfree(sdma->script_addrs); 2157 err_irq: 2158 clk_unprepare(sdma->clk_ahb); 2159 err_clk: 2160 clk_unprepare(sdma->clk_ipg); 2161 return ret; 2162 } 2163 2164 static int sdma_remove(struct platform_device *pdev) 2165 { 2166 struct sdma_engine *sdma = platform_get_drvdata(pdev); 2167 int i; 2168 2169 devm_free_irq(&pdev->dev, sdma->irq, sdma); 2170 dma_async_device_unregister(&sdma->dma_device); 2171 kfree(sdma->script_addrs); 2172 clk_unprepare(sdma->clk_ahb); 2173 clk_unprepare(sdma->clk_ipg); 2174 /* Kill the tasklet */ 2175 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2176 struct sdma_channel *sdmac = &sdma->channel[i]; 2177 2178 tasklet_kill(&sdmac->vc.task); 2179 sdma_free_chan_resources(&sdmac->vc.chan); 2180 } 2181 2182 platform_set_drvdata(pdev, NULL); 2183 return 0; 2184 } 2185 2186 static struct platform_driver sdma_driver = { 2187 .driver = { 2188 .name = "imx-sdma", 2189 .of_match_table = sdma_dt_ids, 2190 }, 2191 .id_table = sdma_devtypes, 2192 .remove = sdma_remove, 2193 .probe = sdma_probe, 2194 }; 2195 2196 module_platform_driver(sdma_driver); 2197 2198 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 2199 MODULE_DESCRIPTION("i.MX SDMA driver"); 2200 #if IS_ENABLED(CONFIG_SOC_IMX6Q) 2201 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin"); 2202 #endif 2203 #if IS_ENABLED(CONFIG_SOC_IMX7D) 2204 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin"); 2205 #endif 2206 MODULE_LICENSE("GPL"); 2207