1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // drivers/dma/imx-sdma.c 4 // 5 // This file contains a driver for the Freescale Smart DMA engine 6 // 7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 // 9 // Based on code from Freescale: 10 // 11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 12 13 #include <linux/init.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/types.h> 17 #include <linux/bitops.h> 18 #include <linux/mm.h> 19 #include <linux/interrupt.h> 20 #include <linux/clk.h> 21 #include <linux/delay.h> 22 #include <linux/sched.h> 23 #include <linux/semaphore.h> 24 #include <linux/spinlock.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firmware.h> 28 #include <linux/slab.h> 29 #include <linux/platform_device.h> 30 #include <linux/dmaengine.h> 31 #include <linux/of.h> 32 #include <linux/of_address.h> 33 #include <linux/of_device.h> 34 #include <linux/of_dma.h> 35 #include <linux/workqueue.h> 36 37 #include <asm/irq.h> 38 #include <linux/platform_data/dma-imx-sdma.h> 39 #include <linux/platform_data/dma-imx.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 43 44 #include "dmaengine.h" 45 #include "virt-dma.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * p_2_p watermark_level description 128 * Bits Name Description 129 * 0-7 Lower WML Lower watermark level 130 * 8 PS 1: Pad Swallowing 131 * 0: No Pad Swallowing 132 * 9 PA 1: Pad Adding 133 * 0: No Pad Adding 134 * 10 SPDIF If this bit is set both source 135 * and destination are on SPBA 136 * 11 Source Bit(SP) 1: Source on SPBA 137 * 0: Source on AIPS 138 * 12 Destination Bit(DP) 1: Destination on SPBA 139 * 0: Destination on AIPS 140 * 13-15 --------- MUST BE 0 141 * 16-23 Higher WML HWML 142 * 24-27 N Total number of samples after 143 * which Pad adding/Swallowing 144 * must be done. It must be odd. 145 * 28 Lower WML Event(LWE) SDMA events reg to check for 146 * LWML event mask 147 * 0: LWE in EVENTS register 148 * 1: LWE in EVENTS2 register 149 * 29 Higher WML Event(HWE) SDMA events reg to check for 150 * HWML event mask 151 * 0: HWE in EVENTS register 152 * 1: HWE in EVENTS2 register 153 * 30 --------- MUST BE 0 154 * 31 CONT 1: Amount of samples to be 155 * transferred is unknown and 156 * script will keep on 157 * transferring samples as long as 158 * both events are detected and 159 * script must be manually stopped 160 * by the application 161 * 0: The amount of samples to be 162 * transferred is equal to the 163 * count field of mode word 164 */ 165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF 166 #define SDMA_WATERMARK_LEVEL_PS BIT(8) 167 #define SDMA_WATERMARK_LEVEL_PA BIT(9) 168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) 169 #define SDMA_WATERMARK_LEVEL_SP BIT(11) 170 #define SDMA_WATERMARK_LEVEL_DP BIT(12) 171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) 172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28) 173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29) 174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31) 175 176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 179 180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ 181 BIT(DMA_MEM_TO_DEV) | \ 182 BIT(DMA_DEV_TO_DEV)) 183 184 /* 185 * Mode/Count of data node descriptors - IPCv2 186 */ 187 struct sdma_mode_count { 188 #define SDMA_BD_MAX_CNT 0xffff 189 u32 count : 16; /* size of the buffer pointed by this BD */ 190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 191 u32 command : 8; /* command mostly used for channel 0 */ 192 }; 193 194 /* 195 * Buffer descriptor 196 */ 197 struct sdma_buffer_descriptor { 198 struct sdma_mode_count mode; 199 u32 buffer_addr; /* address of the buffer described */ 200 u32 ext_buffer_addr; /* extended buffer address */ 201 } __attribute__ ((packed)); 202 203 /** 204 * struct sdma_channel_control - Channel control Block 205 * 206 * @current_bd_ptr: current buffer descriptor processed 207 * @base_bd_ptr: first element of buffer descriptor array 208 * @unused: padding. The SDMA engine expects an array of 128 byte 209 * control blocks 210 */ 211 struct sdma_channel_control { 212 u32 current_bd_ptr; 213 u32 base_bd_ptr; 214 u32 unused[2]; 215 } __attribute__ ((packed)); 216 217 /** 218 * struct sdma_state_registers - SDMA context for a channel 219 * 220 * @pc: program counter 221 * @unused1: unused 222 * @t: test bit: status of arithmetic & test instruction 223 * @rpc: return program counter 224 * @unused0: unused 225 * @sf: source fault while loading data 226 * @spc: loop start program counter 227 * @unused2: unused 228 * @df: destination fault while storing data 229 * @epc: loop end program counter 230 * @lm: loop mode 231 */ 232 struct sdma_state_registers { 233 u32 pc :14; 234 u32 unused1: 1; 235 u32 t : 1; 236 u32 rpc :14; 237 u32 unused0: 1; 238 u32 sf : 1; 239 u32 spc :14; 240 u32 unused2: 1; 241 u32 df : 1; 242 u32 epc :14; 243 u32 lm : 2; 244 } __attribute__ ((packed)); 245 246 /** 247 * struct sdma_context_data - sdma context specific to a channel 248 * 249 * @channel_state: channel state bits 250 * @gReg: general registers 251 * @mda: burst dma destination address register 252 * @msa: burst dma source address register 253 * @ms: burst dma status register 254 * @md: burst dma data register 255 * @pda: peripheral dma destination address register 256 * @psa: peripheral dma source address register 257 * @ps: peripheral dma status register 258 * @pd: peripheral dma data register 259 * @ca: CRC polynomial register 260 * @cs: CRC accumulator register 261 * @dda: dedicated core destination address register 262 * @dsa: dedicated core source address register 263 * @ds: dedicated core status register 264 * @dd: dedicated core data register 265 * @scratch0: 1st word of dedicated ram for context switch 266 * @scratch1: 2nd word of dedicated ram for context switch 267 * @scratch2: 3rd word of dedicated ram for context switch 268 * @scratch3: 4th word of dedicated ram for context switch 269 * @scratch4: 5th word of dedicated ram for context switch 270 * @scratch5: 6th word of dedicated ram for context switch 271 * @scratch6: 7th word of dedicated ram for context switch 272 * @scratch7: 8th word of dedicated ram for context switch 273 */ 274 struct sdma_context_data { 275 struct sdma_state_registers channel_state; 276 u32 gReg[8]; 277 u32 mda; 278 u32 msa; 279 u32 ms; 280 u32 md; 281 u32 pda; 282 u32 psa; 283 u32 ps; 284 u32 pd; 285 u32 ca; 286 u32 cs; 287 u32 dda; 288 u32 dsa; 289 u32 ds; 290 u32 dd; 291 u32 scratch0; 292 u32 scratch1; 293 u32 scratch2; 294 u32 scratch3; 295 u32 scratch4; 296 u32 scratch5; 297 u32 scratch6; 298 u32 scratch7; 299 } __attribute__ ((packed)); 300 301 302 struct sdma_engine; 303 304 /** 305 * struct sdma_desc - descriptor structor for one transfer 306 * @vd: descriptor for virt dma 307 * @num_bd: number of descriptors currently handling 308 * @bd_phys: physical address of bd 309 * @buf_tail: ID of the buffer that was processed 310 * @buf_ptail: ID of the previous buffer that was processed 311 * @period_len: period length, used in cyclic. 312 * @chn_real_count: the real count updated from bd->mode.count 313 * @chn_count: the transfer count set 314 * @sdmac: sdma_channel pointer 315 * @bd: pointer of allocate bd 316 */ 317 struct sdma_desc { 318 struct virt_dma_desc vd; 319 unsigned int num_bd; 320 dma_addr_t bd_phys; 321 unsigned int buf_tail; 322 unsigned int buf_ptail; 323 unsigned int period_len; 324 unsigned int chn_real_count; 325 unsigned int chn_count; 326 struct sdma_channel *sdmac; 327 struct sdma_buffer_descriptor *bd; 328 }; 329 330 /** 331 * struct sdma_channel - housekeeping for a SDMA channel 332 * 333 * @vc: virt_dma base structure 334 * @desc: sdma description including vd and other special member 335 * @sdma: pointer to the SDMA engine for this channel 336 * @channel: the channel number, matches dmaengine chan_id + 1 337 * @direction: transfer type. Needed for setting SDMA script 338 * @slave_config: Slave configuration 339 * @peripheral_type: Peripheral type. Needed for setting SDMA script 340 * @event_id0: aka dma request line 341 * @event_id1: for channels that use 2 events 342 * @word_size: peripheral access size 343 * @pc_from_device: script address for those device_2_memory 344 * @pc_to_device: script address for those memory_2_device 345 * @device_to_device: script address for those device_2_device 346 * @pc_to_pc: script address for those memory_2_memory 347 * @flags: loop mode or not 348 * @per_address: peripheral source or destination address in common case 349 * destination address in p_2_p case 350 * @per_address2: peripheral source address in p_2_p case 351 * @event_mask: event mask used in p_2_p script 352 * @watermark_level: value for gReg[7], some script will extend it from 353 * basic watermark such as p_2_p 354 * @shp_addr: value for gReg[6] 355 * @per_addr: value for gReg[2] 356 * @status: status of dma channel 357 * @context_loaded: ensure context is only loaded once 358 * @data: specific sdma interface structure 359 * @bd_pool: dma_pool for bd 360 * @terminate_worker: used to call back into terminate work function 361 */ 362 struct sdma_channel { 363 struct virt_dma_chan vc; 364 struct sdma_desc *desc; 365 struct sdma_engine *sdma; 366 unsigned int channel; 367 enum dma_transfer_direction direction; 368 struct dma_slave_config slave_config; 369 enum sdma_peripheral_type peripheral_type; 370 unsigned int event_id0; 371 unsigned int event_id1; 372 enum dma_slave_buswidth word_size; 373 unsigned int pc_from_device, pc_to_device; 374 unsigned int device_to_device; 375 unsigned int pc_to_pc; 376 unsigned long flags; 377 dma_addr_t per_address, per_address2; 378 unsigned long event_mask[2]; 379 unsigned long watermark_level; 380 u32 shp_addr, per_addr; 381 enum dma_status status; 382 bool context_loaded; 383 struct imx_dma_data data; 384 struct work_struct terminate_worker; 385 }; 386 387 #define IMX_DMA_SG_LOOP BIT(0) 388 389 #define MAX_DMA_CHANNELS 32 390 #define MXC_SDMA_DEFAULT_PRIORITY 1 391 #define MXC_SDMA_MIN_PRIORITY 1 392 #define MXC_SDMA_MAX_PRIORITY 7 393 394 #define SDMA_FIRMWARE_MAGIC 0x414d4453 395 396 /** 397 * struct sdma_firmware_header - Layout of the firmware image 398 * 399 * @magic: "SDMA" 400 * @version_major: increased whenever layout of struct 401 * sdma_script_start_addrs changes. 402 * @version_minor: firmware minor version (for binary compatible changes) 403 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image 404 * @num_script_addrs: Number of script addresses in this image 405 * @ram_code_start: offset of SDMA ram image in this firmware image 406 * @ram_code_size: size of SDMA ram image 407 * @script_addrs: Stores the start address of the SDMA scripts 408 * (in SDMA memory space) 409 */ 410 struct sdma_firmware_header { 411 u32 magic; 412 u32 version_major; 413 u32 version_minor; 414 u32 script_addrs_start; 415 u32 num_script_addrs; 416 u32 ram_code_start; 417 u32 ram_code_size; 418 }; 419 420 struct sdma_driver_data { 421 int chnenbl0; 422 int num_events; 423 struct sdma_script_start_addrs *script_addrs; 424 bool check_ratio; 425 }; 426 427 struct sdma_engine { 428 struct device *dev; 429 struct sdma_channel channel[MAX_DMA_CHANNELS]; 430 struct sdma_channel_control *channel_control; 431 void __iomem *regs; 432 struct sdma_context_data *context; 433 dma_addr_t context_phys; 434 struct dma_device dma_device; 435 struct clk *clk_ipg; 436 struct clk *clk_ahb; 437 spinlock_t channel_0_lock; 438 u32 script_number; 439 struct sdma_script_start_addrs *script_addrs; 440 const struct sdma_driver_data *drvdata; 441 u32 spba_start_addr; 442 u32 spba_end_addr; 443 unsigned int irq; 444 dma_addr_t bd0_phys; 445 struct sdma_buffer_descriptor *bd0; 446 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ 447 bool clk_ratio; 448 }; 449 450 static int sdma_config_write(struct dma_chan *chan, 451 struct dma_slave_config *dmaengine_cfg, 452 enum dma_transfer_direction direction); 453 454 static struct sdma_driver_data sdma_imx31 = { 455 .chnenbl0 = SDMA_CHNENBL0_IMX31, 456 .num_events = 32, 457 }; 458 459 static struct sdma_script_start_addrs sdma_script_imx25 = { 460 .ap_2_ap_addr = 729, 461 .uart_2_mcu_addr = 904, 462 .per_2_app_addr = 1255, 463 .mcu_2_app_addr = 834, 464 .uartsh_2_mcu_addr = 1120, 465 .per_2_shp_addr = 1329, 466 .mcu_2_shp_addr = 1048, 467 .ata_2_mcu_addr = 1560, 468 .mcu_2_ata_addr = 1479, 469 .app_2_per_addr = 1189, 470 .app_2_mcu_addr = 770, 471 .shp_2_per_addr = 1407, 472 .shp_2_mcu_addr = 979, 473 }; 474 475 static struct sdma_driver_data sdma_imx25 = { 476 .chnenbl0 = SDMA_CHNENBL0_IMX35, 477 .num_events = 48, 478 .script_addrs = &sdma_script_imx25, 479 }; 480 481 static struct sdma_driver_data sdma_imx35 = { 482 .chnenbl0 = SDMA_CHNENBL0_IMX35, 483 .num_events = 48, 484 }; 485 486 static struct sdma_script_start_addrs sdma_script_imx51 = { 487 .ap_2_ap_addr = 642, 488 .uart_2_mcu_addr = 817, 489 .mcu_2_app_addr = 747, 490 .mcu_2_shp_addr = 961, 491 .ata_2_mcu_addr = 1473, 492 .mcu_2_ata_addr = 1392, 493 .app_2_per_addr = 1033, 494 .app_2_mcu_addr = 683, 495 .shp_2_per_addr = 1251, 496 .shp_2_mcu_addr = 892, 497 }; 498 499 static struct sdma_driver_data sdma_imx51 = { 500 .chnenbl0 = SDMA_CHNENBL0_IMX35, 501 .num_events = 48, 502 .script_addrs = &sdma_script_imx51, 503 }; 504 505 static struct sdma_script_start_addrs sdma_script_imx53 = { 506 .ap_2_ap_addr = 642, 507 .app_2_mcu_addr = 683, 508 .mcu_2_app_addr = 747, 509 .uart_2_mcu_addr = 817, 510 .shp_2_mcu_addr = 891, 511 .mcu_2_shp_addr = 960, 512 .uartsh_2_mcu_addr = 1032, 513 .spdif_2_mcu_addr = 1100, 514 .mcu_2_spdif_addr = 1134, 515 .firi_2_mcu_addr = 1193, 516 .mcu_2_firi_addr = 1290, 517 }; 518 519 static struct sdma_driver_data sdma_imx53 = { 520 .chnenbl0 = SDMA_CHNENBL0_IMX35, 521 .num_events = 48, 522 .script_addrs = &sdma_script_imx53, 523 }; 524 525 static struct sdma_script_start_addrs sdma_script_imx6q = { 526 .ap_2_ap_addr = 642, 527 .uart_2_mcu_addr = 817, 528 .mcu_2_app_addr = 747, 529 .per_2_per_addr = 6331, 530 .uartsh_2_mcu_addr = 1032, 531 .mcu_2_shp_addr = 960, 532 .app_2_mcu_addr = 683, 533 .shp_2_mcu_addr = 891, 534 .spdif_2_mcu_addr = 1100, 535 .mcu_2_spdif_addr = 1134, 536 }; 537 538 static struct sdma_driver_data sdma_imx6q = { 539 .chnenbl0 = SDMA_CHNENBL0_IMX35, 540 .num_events = 48, 541 .script_addrs = &sdma_script_imx6q, 542 }; 543 544 static struct sdma_script_start_addrs sdma_script_imx7d = { 545 .ap_2_ap_addr = 644, 546 .uart_2_mcu_addr = 819, 547 .mcu_2_app_addr = 749, 548 .uartsh_2_mcu_addr = 1034, 549 .mcu_2_shp_addr = 962, 550 .app_2_mcu_addr = 685, 551 .shp_2_mcu_addr = 893, 552 .spdif_2_mcu_addr = 1102, 553 .mcu_2_spdif_addr = 1136, 554 }; 555 556 static struct sdma_driver_data sdma_imx7d = { 557 .chnenbl0 = SDMA_CHNENBL0_IMX35, 558 .num_events = 48, 559 .script_addrs = &sdma_script_imx7d, 560 }; 561 562 static struct sdma_driver_data sdma_imx8mq = { 563 .chnenbl0 = SDMA_CHNENBL0_IMX35, 564 .num_events = 48, 565 .script_addrs = &sdma_script_imx7d, 566 .check_ratio = 1, 567 }; 568 569 static const struct platform_device_id sdma_devtypes[] = { 570 { 571 .name = "imx25-sdma", 572 .driver_data = (unsigned long)&sdma_imx25, 573 }, { 574 .name = "imx31-sdma", 575 .driver_data = (unsigned long)&sdma_imx31, 576 }, { 577 .name = "imx35-sdma", 578 .driver_data = (unsigned long)&sdma_imx35, 579 }, { 580 .name = "imx51-sdma", 581 .driver_data = (unsigned long)&sdma_imx51, 582 }, { 583 .name = "imx53-sdma", 584 .driver_data = (unsigned long)&sdma_imx53, 585 }, { 586 .name = "imx6q-sdma", 587 .driver_data = (unsigned long)&sdma_imx6q, 588 }, { 589 .name = "imx7d-sdma", 590 .driver_data = (unsigned long)&sdma_imx7d, 591 }, { 592 .name = "imx8mq-sdma", 593 .driver_data = (unsigned long)&sdma_imx8mq, 594 }, { 595 /* sentinel */ 596 } 597 }; 598 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 599 600 static const struct of_device_id sdma_dt_ids[] = { 601 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 602 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 603 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 604 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 605 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 606 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 607 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, 608 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, 609 { /* sentinel */ } 610 }; 611 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 612 613 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 614 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 615 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 616 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 617 618 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 619 { 620 u32 chnenbl0 = sdma->drvdata->chnenbl0; 621 return chnenbl0 + event * 4; 622 } 623 624 static int sdma_config_ownership(struct sdma_channel *sdmac, 625 bool event_override, bool mcu_override, bool dsp_override) 626 { 627 struct sdma_engine *sdma = sdmac->sdma; 628 int channel = sdmac->channel; 629 unsigned long evt, mcu, dsp; 630 631 if (event_override && mcu_override && dsp_override) 632 return -EINVAL; 633 634 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 635 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 636 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 637 638 if (dsp_override) 639 __clear_bit(channel, &dsp); 640 else 641 __set_bit(channel, &dsp); 642 643 if (event_override) 644 __clear_bit(channel, &evt); 645 else 646 __set_bit(channel, &evt); 647 648 if (mcu_override) 649 __clear_bit(channel, &mcu); 650 else 651 __set_bit(channel, &mcu); 652 653 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 654 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 655 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 656 657 return 0; 658 } 659 660 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 661 { 662 writel(BIT(channel), sdma->regs + SDMA_H_START); 663 } 664 665 /* 666 * sdma_run_channel0 - run a channel and wait till it's done 667 */ 668 static int sdma_run_channel0(struct sdma_engine *sdma) 669 { 670 int ret; 671 u32 reg; 672 673 sdma_enable_channel(sdma, 0); 674 675 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, 676 reg, !(reg & 1), 1, 500); 677 if (ret) 678 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 679 680 /* Set bits of CONFIG register with dynamic context switching */ 681 reg = readl(sdma->regs + SDMA_H_CONFIG); 682 if ((reg & SDMA_H_CONFIG_CSM) == 0) { 683 reg |= SDMA_H_CONFIG_CSM; 684 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); 685 } 686 687 return ret; 688 } 689 690 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 691 u32 address) 692 { 693 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 694 void *buf_virt; 695 dma_addr_t buf_phys; 696 int ret; 697 unsigned long flags; 698 699 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); 700 if (!buf_virt) { 701 return -ENOMEM; 702 } 703 704 spin_lock_irqsave(&sdma->channel_0_lock, flags); 705 706 bd0->mode.command = C0_SETPM; 707 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; 708 bd0->mode.count = size / 2; 709 bd0->buffer_addr = buf_phys; 710 bd0->ext_buffer_addr = address; 711 712 memcpy(buf_virt, buf, size); 713 714 ret = sdma_run_channel0(sdma); 715 716 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 717 718 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); 719 720 return ret; 721 } 722 723 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 724 { 725 struct sdma_engine *sdma = sdmac->sdma; 726 int channel = sdmac->channel; 727 unsigned long val; 728 u32 chnenbl = chnenbl_ofs(sdma, event); 729 730 val = readl_relaxed(sdma->regs + chnenbl); 731 __set_bit(channel, &val); 732 writel_relaxed(val, sdma->regs + chnenbl); 733 } 734 735 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 736 { 737 struct sdma_engine *sdma = sdmac->sdma; 738 int channel = sdmac->channel; 739 u32 chnenbl = chnenbl_ofs(sdma, event); 740 unsigned long val; 741 742 val = readl_relaxed(sdma->regs + chnenbl); 743 __clear_bit(channel, &val); 744 writel_relaxed(val, sdma->regs + chnenbl); 745 } 746 747 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t) 748 { 749 return container_of(t, struct sdma_desc, vd.tx); 750 } 751 752 static void sdma_start_desc(struct sdma_channel *sdmac) 753 { 754 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); 755 struct sdma_desc *desc; 756 struct sdma_engine *sdma = sdmac->sdma; 757 int channel = sdmac->channel; 758 759 if (!vd) { 760 sdmac->desc = NULL; 761 return; 762 } 763 sdmac->desc = desc = to_sdma_desc(&vd->tx); 764 765 list_del(&vd->node); 766 767 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; 768 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; 769 sdma_enable_channel(sdma, sdmac->channel); 770 } 771 772 static void sdma_update_channel_loop(struct sdma_channel *sdmac) 773 { 774 struct sdma_buffer_descriptor *bd; 775 int error = 0; 776 enum dma_status old_status = sdmac->status; 777 778 /* 779 * loop mode. Iterate over descriptors, re-setup them and 780 * call callback function. 781 */ 782 while (sdmac->desc) { 783 struct sdma_desc *desc = sdmac->desc; 784 785 bd = &desc->bd[desc->buf_tail]; 786 787 if (bd->mode.status & BD_DONE) 788 break; 789 790 if (bd->mode.status & BD_RROR) { 791 bd->mode.status &= ~BD_RROR; 792 sdmac->status = DMA_ERROR; 793 error = -EIO; 794 } 795 796 /* 797 * We use bd->mode.count to calculate the residue, since contains 798 * the number of bytes present in the current buffer descriptor. 799 */ 800 801 desc->chn_real_count = bd->mode.count; 802 bd->mode.status |= BD_DONE; 803 bd->mode.count = desc->period_len; 804 desc->buf_ptail = desc->buf_tail; 805 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; 806 807 /* 808 * The callback is called from the interrupt context in order 809 * to reduce latency and to avoid the risk of altering the 810 * SDMA transaction status by the time the client tasklet is 811 * executed. 812 */ 813 spin_unlock(&sdmac->vc.lock); 814 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); 815 spin_lock(&sdmac->vc.lock); 816 817 if (error) 818 sdmac->status = old_status; 819 } 820 } 821 822 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data) 823 { 824 struct sdma_channel *sdmac = (struct sdma_channel *) data; 825 struct sdma_buffer_descriptor *bd; 826 int i, error = 0; 827 828 sdmac->desc->chn_real_count = 0; 829 /* 830 * non loop mode. Iterate over all descriptors, collect 831 * errors and call callback function 832 */ 833 for (i = 0; i < sdmac->desc->num_bd; i++) { 834 bd = &sdmac->desc->bd[i]; 835 836 if (bd->mode.status & (BD_DONE | BD_RROR)) 837 error = -EIO; 838 sdmac->desc->chn_real_count += bd->mode.count; 839 } 840 841 if (error) 842 sdmac->status = DMA_ERROR; 843 else 844 sdmac->status = DMA_COMPLETE; 845 } 846 847 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 848 { 849 struct sdma_engine *sdma = dev_id; 850 unsigned long stat; 851 852 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 853 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 854 /* channel 0 is special and not handled here, see run_channel0() */ 855 stat &= ~1; 856 857 while (stat) { 858 int channel = fls(stat) - 1; 859 struct sdma_channel *sdmac = &sdma->channel[channel]; 860 struct sdma_desc *desc; 861 862 spin_lock(&sdmac->vc.lock); 863 desc = sdmac->desc; 864 if (desc) { 865 if (sdmac->flags & IMX_DMA_SG_LOOP) { 866 sdma_update_channel_loop(sdmac); 867 } else { 868 mxc_sdma_handle_channel_normal(sdmac); 869 vchan_cookie_complete(&desc->vd); 870 sdma_start_desc(sdmac); 871 } 872 } 873 874 spin_unlock(&sdmac->vc.lock); 875 __clear_bit(channel, &stat); 876 } 877 878 return IRQ_HANDLED; 879 } 880 881 /* 882 * sets the pc of SDMA script according to the peripheral type 883 */ 884 static void sdma_get_pc(struct sdma_channel *sdmac, 885 enum sdma_peripheral_type peripheral_type) 886 { 887 struct sdma_engine *sdma = sdmac->sdma; 888 int per_2_emi = 0, emi_2_per = 0; 889 /* 890 * These are needed once we start to support transfers between 891 * two peripherals or memory-to-memory transfers 892 */ 893 int per_2_per = 0, emi_2_emi = 0; 894 895 sdmac->pc_from_device = 0; 896 sdmac->pc_to_device = 0; 897 sdmac->device_to_device = 0; 898 sdmac->pc_to_pc = 0; 899 900 switch (peripheral_type) { 901 case IMX_DMATYPE_MEMORY: 902 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 903 break; 904 case IMX_DMATYPE_DSP: 905 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 906 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 907 break; 908 case IMX_DMATYPE_FIRI: 909 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 910 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 911 break; 912 case IMX_DMATYPE_UART: 913 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 914 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 915 break; 916 case IMX_DMATYPE_UART_SP: 917 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 918 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 919 break; 920 case IMX_DMATYPE_ATA: 921 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 922 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 923 break; 924 case IMX_DMATYPE_CSPI: 925 case IMX_DMATYPE_EXT: 926 case IMX_DMATYPE_SSI: 927 case IMX_DMATYPE_SAI: 928 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 929 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 930 break; 931 case IMX_DMATYPE_SSI_DUAL: 932 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 933 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 934 break; 935 case IMX_DMATYPE_SSI_SP: 936 case IMX_DMATYPE_MMC: 937 case IMX_DMATYPE_SDHC: 938 case IMX_DMATYPE_CSPI_SP: 939 case IMX_DMATYPE_ESAI: 940 case IMX_DMATYPE_MSHC_SP: 941 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 942 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 943 break; 944 case IMX_DMATYPE_ASRC: 945 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 946 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 947 per_2_per = sdma->script_addrs->per_2_per_addr; 948 break; 949 case IMX_DMATYPE_ASRC_SP: 950 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 951 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 952 per_2_per = sdma->script_addrs->per_2_per_addr; 953 break; 954 case IMX_DMATYPE_MSHC: 955 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 956 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 957 break; 958 case IMX_DMATYPE_CCM: 959 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 960 break; 961 case IMX_DMATYPE_SPDIF: 962 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 963 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 964 break; 965 case IMX_DMATYPE_IPU_MEMORY: 966 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 967 break; 968 default: 969 break; 970 } 971 972 sdmac->pc_from_device = per_2_emi; 973 sdmac->pc_to_device = emi_2_per; 974 sdmac->device_to_device = per_2_per; 975 sdmac->pc_to_pc = emi_2_emi; 976 } 977 978 static int sdma_load_context(struct sdma_channel *sdmac) 979 { 980 struct sdma_engine *sdma = sdmac->sdma; 981 int channel = sdmac->channel; 982 int load_address; 983 struct sdma_context_data *context = sdma->context; 984 struct sdma_buffer_descriptor *bd0 = sdma->bd0; 985 int ret; 986 unsigned long flags; 987 988 if (sdmac->context_loaded) 989 return 0; 990 991 if (sdmac->direction == DMA_DEV_TO_MEM) 992 load_address = sdmac->pc_from_device; 993 else if (sdmac->direction == DMA_DEV_TO_DEV) 994 load_address = sdmac->device_to_device; 995 else if (sdmac->direction == DMA_MEM_TO_MEM) 996 load_address = sdmac->pc_to_pc; 997 else 998 load_address = sdmac->pc_to_device; 999 1000 if (load_address < 0) 1001 return load_address; 1002 1003 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 1004 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 1005 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 1006 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 1007 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 1008 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 1009 1010 spin_lock_irqsave(&sdma->channel_0_lock, flags); 1011 1012 memset(context, 0, sizeof(*context)); 1013 context->channel_state.pc = load_address; 1014 1015 /* Send by context the event mask,base address for peripheral 1016 * and watermark level 1017 */ 1018 context->gReg[0] = sdmac->event_mask[1]; 1019 context->gReg[1] = sdmac->event_mask[0]; 1020 context->gReg[2] = sdmac->per_addr; 1021 context->gReg[6] = sdmac->shp_addr; 1022 context->gReg[7] = sdmac->watermark_level; 1023 1024 bd0->mode.command = C0_SETDM; 1025 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; 1026 bd0->mode.count = sizeof(*context) / 4; 1027 bd0->buffer_addr = sdma->context_phys; 1028 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 1029 ret = sdma_run_channel0(sdma); 1030 1031 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 1032 1033 sdmac->context_loaded = true; 1034 1035 return ret; 1036 } 1037 1038 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 1039 { 1040 return container_of(chan, struct sdma_channel, vc.chan); 1041 } 1042 1043 static int sdma_disable_channel(struct dma_chan *chan) 1044 { 1045 struct sdma_channel *sdmac = to_sdma_chan(chan); 1046 struct sdma_engine *sdma = sdmac->sdma; 1047 int channel = sdmac->channel; 1048 1049 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 1050 sdmac->status = DMA_ERROR; 1051 1052 return 0; 1053 } 1054 static void sdma_channel_terminate_work(struct work_struct *work) 1055 { 1056 struct sdma_channel *sdmac = container_of(work, struct sdma_channel, 1057 terminate_worker); 1058 unsigned long flags; 1059 LIST_HEAD(head); 1060 1061 /* 1062 * According to NXP R&D team a delay of one BD SDMA cost time 1063 * (maximum is 1ms) should be added after disable of the channel 1064 * bit, to ensure SDMA core has really been stopped after SDMA 1065 * clients call .device_terminate_all. 1066 */ 1067 usleep_range(1000, 2000); 1068 1069 spin_lock_irqsave(&sdmac->vc.lock, flags); 1070 vchan_get_all_descriptors(&sdmac->vc, &head); 1071 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1072 vchan_dma_desc_free_list(&sdmac->vc, &head); 1073 sdmac->context_loaded = false; 1074 } 1075 1076 static int sdma_terminate_all(struct dma_chan *chan) 1077 { 1078 struct sdma_channel *sdmac = to_sdma_chan(chan); 1079 unsigned long flags; 1080 1081 spin_lock_irqsave(&sdmac->vc.lock, flags); 1082 1083 sdma_disable_channel(chan); 1084 1085 if (sdmac->desc) { 1086 vchan_terminate_vdesc(&sdmac->desc->vd); 1087 sdmac->desc = NULL; 1088 schedule_work(&sdmac->terminate_worker); 1089 } 1090 1091 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1092 1093 return 0; 1094 } 1095 1096 static void sdma_channel_synchronize(struct dma_chan *chan) 1097 { 1098 struct sdma_channel *sdmac = to_sdma_chan(chan); 1099 1100 vchan_synchronize(&sdmac->vc); 1101 1102 flush_work(&sdmac->terminate_worker); 1103 } 1104 1105 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) 1106 { 1107 struct sdma_engine *sdma = sdmac->sdma; 1108 1109 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; 1110 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; 1111 1112 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); 1113 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); 1114 1115 if (sdmac->event_id0 > 31) 1116 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; 1117 1118 if (sdmac->event_id1 > 31) 1119 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; 1120 1121 /* 1122 * If LWML(src_maxburst) > HWML(dst_maxburst), we need 1123 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap 1124 * r0(event_mask[1]) and r1(event_mask[0]). 1125 */ 1126 if (lwml > hwml) { 1127 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | 1128 SDMA_WATERMARK_LEVEL_HWML); 1129 sdmac->watermark_level |= hwml; 1130 sdmac->watermark_level |= lwml << 16; 1131 swap(sdmac->event_mask[0], sdmac->event_mask[1]); 1132 } 1133 1134 if (sdmac->per_address2 >= sdma->spba_start_addr && 1135 sdmac->per_address2 <= sdma->spba_end_addr) 1136 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; 1137 1138 if (sdmac->per_address >= sdma->spba_start_addr && 1139 sdmac->per_address <= sdma->spba_end_addr) 1140 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; 1141 1142 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; 1143 } 1144 1145 static int sdma_config_channel(struct dma_chan *chan) 1146 { 1147 struct sdma_channel *sdmac = to_sdma_chan(chan); 1148 int ret; 1149 1150 sdma_disable_channel(chan); 1151 1152 sdmac->event_mask[0] = 0; 1153 sdmac->event_mask[1] = 0; 1154 sdmac->shp_addr = 0; 1155 sdmac->per_addr = 0; 1156 1157 switch (sdmac->peripheral_type) { 1158 case IMX_DMATYPE_DSP: 1159 sdma_config_ownership(sdmac, false, true, true); 1160 break; 1161 case IMX_DMATYPE_MEMORY: 1162 sdma_config_ownership(sdmac, false, true, false); 1163 break; 1164 default: 1165 sdma_config_ownership(sdmac, true, true, false); 1166 break; 1167 } 1168 1169 sdma_get_pc(sdmac, sdmac->peripheral_type); 1170 1171 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 1172 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 1173 /* Handle multiple event channels differently */ 1174 if (sdmac->event_id1) { 1175 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || 1176 sdmac->peripheral_type == IMX_DMATYPE_ASRC) 1177 sdma_set_watermarklevel_for_p2p(sdmac); 1178 } else 1179 __set_bit(sdmac->event_id0, sdmac->event_mask); 1180 1181 /* Address */ 1182 sdmac->shp_addr = sdmac->per_address; 1183 sdmac->per_addr = sdmac->per_address2; 1184 } else { 1185 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 1186 } 1187 1188 ret = sdma_load_context(sdmac); 1189 1190 return ret; 1191 } 1192 1193 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 1194 unsigned int priority) 1195 { 1196 struct sdma_engine *sdma = sdmac->sdma; 1197 int channel = sdmac->channel; 1198 1199 if (priority < MXC_SDMA_MIN_PRIORITY 1200 || priority > MXC_SDMA_MAX_PRIORITY) { 1201 return -EINVAL; 1202 } 1203 1204 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 1205 1206 return 0; 1207 } 1208 1209 static int sdma_request_channel0(struct sdma_engine *sdma) 1210 { 1211 int ret = -EBUSY; 1212 1213 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, 1214 GFP_NOWAIT); 1215 if (!sdma->bd0) { 1216 ret = -ENOMEM; 1217 goto out; 1218 } 1219 1220 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; 1221 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; 1222 1223 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); 1224 return 0; 1225 out: 1226 1227 return ret; 1228 } 1229 1230 1231 static int sdma_alloc_bd(struct sdma_desc *desc) 1232 { 1233 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1234 int ret = 0; 1235 1236 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, 1237 &desc->bd_phys, GFP_NOWAIT); 1238 if (!desc->bd) { 1239 ret = -ENOMEM; 1240 goto out; 1241 } 1242 out: 1243 return ret; 1244 } 1245 1246 static void sdma_free_bd(struct sdma_desc *desc) 1247 { 1248 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); 1249 1250 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, 1251 desc->bd_phys); 1252 } 1253 1254 static void sdma_desc_free(struct virt_dma_desc *vd) 1255 { 1256 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd); 1257 1258 sdma_free_bd(desc); 1259 kfree(desc); 1260 } 1261 1262 static int sdma_alloc_chan_resources(struct dma_chan *chan) 1263 { 1264 struct sdma_channel *sdmac = to_sdma_chan(chan); 1265 struct imx_dma_data *data = chan->private; 1266 struct imx_dma_data mem_data; 1267 int prio, ret; 1268 1269 /* 1270 * MEMCPY may never setup chan->private by filter function such as 1271 * dmatest, thus create 'struct imx_dma_data mem_data' for this case. 1272 * Please note in any other slave case, you have to setup chan->private 1273 * with 'struct imx_dma_data' in your own filter function if you want to 1274 * request dma channel by dma_request_channel() rather than 1275 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear 1276 * to warn you to correct your filter function. 1277 */ 1278 if (!data) { 1279 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); 1280 mem_data.priority = 2; 1281 mem_data.peripheral_type = IMX_DMATYPE_MEMORY; 1282 mem_data.dma_request = 0; 1283 mem_data.dma_request2 = 0; 1284 data = &mem_data; 1285 1286 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); 1287 } 1288 1289 switch (data->priority) { 1290 case DMA_PRIO_HIGH: 1291 prio = 3; 1292 break; 1293 case DMA_PRIO_MEDIUM: 1294 prio = 2; 1295 break; 1296 case DMA_PRIO_LOW: 1297 default: 1298 prio = 1; 1299 break; 1300 } 1301 1302 sdmac->peripheral_type = data->peripheral_type; 1303 sdmac->event_id0 = data->dma_request; 1304 sdmac->event_id1 = data->dma_request2; 1305 1306 ret = clk_enable(sdmac->sdma->clk_ipg); 1307 if (ret) 1308 return ret; 1309 ret = clk_enable(sdmac->sdma->clk_ahb); 1310 if (ret) 1311 goto disable_clk_ipg; 1312 1313 ret = sdma_set_channel_priority(sdmac, prio); 1314 if (ret) 1315 goto disable_clk_ahb; 1316 1317 return 0; 1318 1319 disable_clk_ahb: 1320 clk_disable(sdmac->sdma->clk_ahb); 1321 disable_clk_ipg: 1322 clk_disable(sdmac->sdma->clk_ipg); 1323 return ret; 1324 } 1325 1326 static void sdma_free_chan_resources(struct dma_chan *chan) 1327 { 1328 struct sdma_channel *sdmac = to_sdma_chan(chan); 1329 struct sdma_engine *sdma = sdmac->sdma; 1330 1331 sdma_terminate_all(chan); 1332 1333 sdma_channel_synchronize(chan); 1334 1335 sdma_event_disable(sdmac, sdmac->event_id0); 1336 if (sdmac->event_id1) 1337 sdma_event_disable(sdmac, sdmac->event_id1); 1338 1339 sdmac->event_id0 = 0; 1340 sdmac->event_id1 = 0; 1341 sdmac->context_loaded = false; 1342 1343 sdma_set_channel_priority(sdmac, 0); 1344 1345 clk_disable(sdma->clk_ipg); 1346 clk_disable(sdma->clk_ahb); 1347 } 1348 1349 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, 1350 enum dma_transfer_direction direction, u32 bds) 1351 { 1352 struct sdma_desc *desc; 1353 1354 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); 1355 if (!desc) 1356 goto err_out; 1357 1358 sdmac->status = DMA_IN_PROGRESS; 1359 sdmac->direction = direction; 1360 sdmac->flags = 0; 1361 1362 desc->chn_count = 0; 1363 desc->chn_real_count = 0; 1364 desc->buf_tail = 0; 1365 desc->buf_ptail = 0; 1366 desc->sdmac = sdmac; 1367 desc->num_bd = bds; 1368 1369 if (sdma_alloc_bd(desc)) 1370 goto err_desc_out; 1371 1372 /* No slave_config called in MEMCPY case, so do here */ 1373 if (direction == DMA_MEM_TO_MEM) 1374 sdma_config_ownership(sdmac, false, true, false); 1375 1376 if (sdma_load_context(sdmac)) 1377 goto err_desc_out; 1378 1379 return desc; 1380 1381 err_desc_out: 1382 kfree(desc); 1383 err_out: 1384 return NULL; 1385 } 1386 1387 static struct dma_async_tx_descriptor *sdma_prep_memcpy( 1388 struct dma_chan *chan, dma_addr_t dma_dst, 1389 dma_addr_t dma_src, size_t len, unsigned long flags) 1390 { 1391 struct sdma_channel *sdmac = to_sdma_chan(chan); 1392 struct sdma_engine *sdma = sdmac->sdma; 1393 int channel = sdmac->channel; 1394 size_t count; 1395 int i = 0, param; 1396 struct sdma_buffer_descriptor *bd; 1397 struct sdma_desc *desc; 1398 1399 if (!chan || !len) 1400 return NULL; 1401 1402 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", 1403 &dma_src, &dma_dst, len, channel); 1404 1405 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, 1406 len / SDMA_BD_MAX_CNT + 1); 1407 if (!desc) 1408 return NULL; 1409 1410 do { 1411 count = min_t(size_t, len, SDMA_BD_MAX_CNT); 1412 bd = &desc->bd[i]; 1413 bd->buffer_addr = dma_src; 1414 bd->ext_buffer_addr = dma_dst; 1415 bd->mode.count = count; 1416 desc->chn_count += count; 1417 bd->mode.command = 0; 1418 1419 dma_src += count; 1420 dma_dst += count; 1421 len -= count; 1422 i++; 1423 1424 param = BD_DONE | BD_EXTD | BD_CONT; 1425 /* last bd */ 1426 if (!len) { 1427 param |= BD_INTR; 1428 param |= BD_LAST; 1429 param &= ~BD_CONT; 1430 } 1431 1432 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", 1433 i, count, bd->buffer_addr, 1434 param & BD_WRAP ? "wrap" : "", 1435 param & BD_INTR ? " intr" : ""); 1436 1437 bd->mode.status = param; 1438 } while (len); 1439 1440 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1441 } 1442 1443 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1444 struct dma_chan *chan, struct scatterlist *sgl, 1445 unsigned int sg_len, enum dma_transfer_direction direction, 1446 unsigned long flags, void *context) 1447 { 1448 struct sdma_channel *sdmac = to_sdma_chan(chan); 1449 struct sdma_engine *sdma = sdmac->sdma; 1450 int i, count; 1451 int channel = sdmac->channel; 1452 struct scatterlist *sg; 1453 struct sdma_desc *desc; 1454 1455 sdma_config_write(chan, &sdmac->slave_config, direction); 1456 1457 desc = sdma_transfer_init(sdmac, direction, sg_len); 1458 if (!desc) 1459 goto err_out; 1460 1461 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1462 sg_len, channel); 1463 1464 for_each_sg(sgl, sg, sg_len, i) { 1465 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1466 int param; 1467 1468 bd->buffer_addr = sg->dma_address; 1469 1470 count = sg_dma_len(sg); 1471 1472 if (count > SDMA_BD_MAX_CNT) { 1473 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1474 channel, count, SDMA_BD_MAX_CNT); 1475 goto err_bd_out; 1476 } 1477 1478 bd->mode.count = count; 1479 desc->chn_count += count; 1480 1481 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1482 goto err_bd_out; 1483 1484 switch (sdmac->word_size) { 1485 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1486 bd->mode.command = 0; 1487 if (count & 3 || sg->dma_address & 3) 1488 goto err_bd_out; 1489 break; 1490 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1491 bd->mode.command = 2; 1492 if (count & 1 || sg->dma_address & 1) 1493 goto err_bd_out; 1494 break; 1495 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1496 bd->mode.command = 1; 1497 break; 1498 default: 1499 goto err_bd_out; 1500 } 1501 1502 param = BD_DONE | BD_EXTD | BD_CONT; 1503 1504 if (i + 1 == sg_len) { 1505 param |= BD_INTR; 1506 param |= BD_LAST; 1507 param &= ~BD_CONT; 1508 } 1509 1510 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1511 i, count, (u64)sg->dma_address, 1512 param & BD_WRAP ? "wrap" : "", 1513 param & BD_INTR ? " intr" : ""); 1514 1515 bd->mode.status = param; 1516 } 1517 1518 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1519 err_bd_out: 1520 sdma_free_bd(desc); 1521 kfree(desc); 1522 err_out: 1523 sdmac->status = DMA_ERROR; 1524 return NULL; 1525 } 1526 1527 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1528 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1529 size_t period_len, enum dma_transfer_direction direction, 1530 unsigned long flags) 1531 { 1532 struct sdma_channel *sdmac = to_sdma_chan(chan); 1533 struct sdma_engine *sdma = sdmac->sdma; 1534 int num_periods = buf_len / period_len; 1535 int channel = sdmac->channel; 1536 int i = 0, buf = 0; 1537 struct sdma_desc *desc; 1538 1539 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1540 1541 sdma_config_write(chan, &sdmac->slave_config, direction); 1542 1543 desc = sdma_transfer_init(sdmac, direction, num_periods); 1544 if (!desc) 1545 goto err_out; 1546 1547 desc->period_len = period_len; 1548 1549 sdmac->flags |= IMX_DMA_SG_LOOP; 1550 1551 if (period_len > SDMA_BD_MAX_CNT) { 1552 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", 1553 channel, period_len, SDMA_BD_MAX_CNT); 1554 goto err_bd_out; 1555 } 1556 1557 while (buf < buf_len) { 1558 struct sdma_buffer_descriptor *bd = &desc->bd[i]; 1559 int param; 1560 1561 bd->buffer_addr = dma_addr; 1562 1563 bd->mode.count = period_len; 1564 1565 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1566 goto err_bd_out; 1567 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1568 bd->mode.command = 0; 1569 else 1570 bd->mode.command = sdmac->word_size; 1571 1572 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1573 if (i + 1 == num_periods) 1574 param |= BD_WRAP; 1575 1576 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", 1577 i, period_len, (u64)dma_addr, 1578 param & BD_WRAP ? "wrap" : "", 1579 param & BD_INTR ? " intr" : ""); 1580 1581 bd->mode.status = param; 1582 1583 dma_addr += period_len; 1584 buf += period_len; 1585 1586 i++; 1587 } 1588 1589 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); 1590 err_bd_out: 1591 sdma_free_bd(desc); 1592 kfree(desc); 1593 err_out: 1594 sdmac->status = DMA_ERROR; 1595 return NULL; 1596 } 1597 1598 static int sdma_config_write(struct dma_chan *chan, 1599 struct dma_slave_config *dmaengine_cfg, 1600 enum dma_transfer_direction direction) 1601 { 1602 struct sdma_channel *sdmac = to_sdma_chan(chan); 1603 1604 if (direction == DMA_DEV_TO_MEM) { 1605 sdmac->per_address = dmaengine_cfg->src_addr; 1606 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1607 dmaengine_cfg->src_addr_width; 1608 sdmac->word_size = dmaengine_cfg->src_addr_width; 1609 } else if (direction == DMA_DEV_TO_DEV) { 1610 sdmac->per_address2 = dmaengine_cfg->src_addr; 1611 sdmac->per_address = dmaengine_cfg->dst_addr; 1612 sdmac->watermark_level = dmaengine_cfg->src_maxburst & 1613 SDMA_WATERMARK_LEVEL_LWML; 1614 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & 1615 SDMA_WATERMARK_LEVEL_HWML; 1616 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1617 } else { 1618 sdmac->per_address = dmaengine_cfg->dst_addr; 1619 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1620 dmaengine_cfg->dst_addr_width; 1621 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1622 } 1623 sdmac->direction = direction; 1624 return sdma_config_channel(chan); 1625 } 1626 1627 static int sdma_config(struct dma_chan *chan, 1628 struct dma_slave_config *dmaengine_cfg) 1629 { 1630 struct sdma_channel *sdmac = to_sdma_chan(chan); 1631 1632 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); 1633 1634 /* Set ENBLn earlier to make sure dma request triggered after that */ 1635 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 1636 return -EINVAL; 1637 sdma_event_enable(sdmac, sdmac->event_id0); 1638 1639 if (sdmac->event_id1) { 1640 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) 1641 return -EINVAL; 1642 sdma_event_enable(sdmac, sdmac->event_id1); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1649 dma_cookie_t cookie, 1650 struct dma_tx_state *txstate) 1651 { 1652 struct sdma_channel *sdmac = to_sdma_chan(chan); 1653 struct sdma_desc *desc = NULL; 1654 u32 residue; 1655 struct virt_dma_desc *vd; 1656 enum dma_status ret; 1657 unsigned long flags; 1658 1659 ret = dma_cookie_status(chan, cookie, txstate); 1660 if (ret == DMA_COMPLETE || !txstate) 1661 return ret; 1662 1663 spin_lock_irqsave(&sdmac->vc.lock, flags); 1664 1665 vd = vchan_find_desc(&sdmac->vc, cookie); 1666 if (vd) 1667 desc = to_sdma_desc(&vd->tx); 1668 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) 1669 desc = sdmac->desc; 1670 1671 if (desc) { 1672 if (sdmac->flags & IMX_DMA_SG_LOOP) 1673 residue = (desc->num_bd - desc->buf_ptail) * 1674 desc->period_len - desc->chn_real_count; 1675 else 1676 residue = desc->chn_count - desc->chn_real_count; 1677 } else { 1678 residue = 0; 1679 } 1680 1681 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1682 1683 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1684 residue); 1685 1686 return sdmac->status; 1687 } 1688 1689 static void sdma_issue_pending(struct dma_chan *chan) 1690 { 1691 struct sdma_channel *sdmac = to_sdma_chan(chan); 1692 unsigned long flags; 1693 1694 spin_lock_irqsave(&sdmac->vc.lock, flags); 1695 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) 1696 sdma_start_desc(sdmac); 1697 spin_unlock_irqrestore(&sdmac->vc.lock, flags); 1698 } 1699 1700 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1701 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1702 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 1703 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 1704 1705 static void sdma_add_scripts(struct sdma_engine *sdma, 1706 const struct sdma_script_start_addrs *addr) 1707 { 1708 s32 *addr_arr = (u32 *)addr; 1709 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1710 int i; 1711 1712 /* use the default firmware in ROM if missing external firmware */ 1713 if (!sdma->script_number) 1714 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1715 1716 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) 1717 / sizeof(s32)) { 1718 dev_err(sdma->dev, 1719 "SDMA script number %d not match with firmware.\n", 1720 sdma->script_number); 1721 return; 1722 } 1723 1724 for (i = 0; i < sdma->script_number; i++) 1725 if (addr_arr[i] > 0) 1726 saddr_arr[i] = addr_arr[i]; 1727 } 1728 1729 static void sdma_load_firmware(const struct firmware *fw, void *context) 1730 { 1731 struct sdma_engine *sdma = context; 1732 const struct sdma_firmware_header *header; 1733 const struct sdma_script_start_addrs *addr; 1734 unsigned short *ram_code; 1735 1736 if (!fw) { 1737 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); 1738 /* In this case we just use the ROM firmware. */ 1739 return; 1740 } 1741 1742 if (fw->size < sizeof(*header)) 1743 goto err_firmware; 1744 1745 header = (struct sdma_firmware_header *)fw->data; 1746 1747 if (header->magic != SDMA_FIRMWARE_MAGIC) 1748 goto err_firmware; 1749 if (header->ram_code_start + header->ram_code_size > fw->size) 1750 goto err_firmware; 1751 switch (header->version_major) { 1752 case 1: 1753 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1754 break; 1755 case 2: 1756 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1757 break; 1758 case 3: 1759 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; 1760 break; 1761 case 4: 1762 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; 1763 break; 1764 default: 1765 dev_err(sdma->dev, "unknown firmware version\n"); 1766 goto err_firmware; 1767 } 1768 1769 addr = (void *)header + header->script_addrs_start; 1770 ram_code = (void *)header + header->ram_code_start; 1771 1772 clk_enable(sdma->clk_ipg); 1773 clk_enable(sdma->clk_ahb); 1774 /* download the RAM image for SDMA */ 1775 sdma_load_script(sdma, ram_code, 1776 header->ram_code_size, 1777 addr->ram_code_start_addr); 1778 clk_disable(sdma->clk_ipg); 1779 clk_disable(sdma->clk_ahb); 1780 1781 sdma_add_scripts(sdma, addr); 1782 1783 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1784 header->version_major, 1785 header->version_minor); 1786 1787 err_firmware: 1788 release_firmware(fw); 1789 } 1790 1791 #define EVENT_REMAP_CELLS 3 1792 1793 static int sdma_event_remap(struct sdma_engine *sdma) 1794 { 1795 struct device_node *np = sdma->dev->of_node; 1796 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); 1797 struct property *event_remap; 1798 struct regmap *gpr; 1799 char propname[] = "fsl,sdma-event-remap"; 1800 u32 reg, val, shift, num_map, i; 1801 int ret = 0; 1802 1803 if (IS_ERR(np) || IS_ERR(gpr_np)) 1804 goto out; 1805 1806 event_remap = of_find_property(np, propname, NULL); 1807 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; 1808 if (!num_map) { 1809 dev_dbg(sdma->dev, "no event needs to be remapped\n"); 1810 goto out; 1811 } else if (num_map % EVENT_REMAP_CELLS) { 1812 dev_err(sdma->dev, "the property %s must modulo %d\n", 1813 propname, EVENT_REMAP_CELLS); 1814 ret = -EINVAL; 1815 goto out; 1816 } 1817 1818 gpr = syscon_node_to_regmap(gpr_np); 1819 if (IS_ERR(gpr)) { 1820 dev_err(sdma->dev, "failed to get gpr regmap\n"); 1821 ret = PTR_ERR(gpr); 1822 goto out; 1823 } 1824 1825 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { 1826 ret = of_property_read_u32_index(np, propname, i, ®); 1827 if (ret) { 1828 dev_err(sdma->dev, "failed to read property %s index %d\n", 1829 propname, i); 1830 goto out; 1831 } 1832 1833 ret = of_property_read_u32_index(np, propname, i + 1, &shift); 1834 if (ret) { 1835 dev_err(sdma->dev, "failed to read property %s index %d\n", 1836 propname, i + 1); 1837 goto out; 1838 } 1839 1840 ret = of_property_read_u32_index(np, propname, i + 2, &val); 1841 if (ret) { 1842 dev_err(sdma->dev, "failed to read property %s index %d\n", 1843 propname, i + 2); 1844 goto out; 1845 } 1846 1847 regmap_update_bits(gpr, reg, BIT(shift), val << shift); 1848 } 1849 1850 out: 1851 if (!IS_ERR(gpr_np)) 1852 of_node_put(gpr_np); 1853 1854 return ret; 1855 } 1856 1857 static int sdma_get_firmware(struct sdma_engine *sdma, 1858 const char *fw_name) 1859 { 1860 int ret; 1861 1862 ret = request_firmware_nowait(THIS_MODULE, 1863 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1864 GFP_KERNEL, sdma, sdma_load_firmware); 1865 1866 return ret; 1867 } 1868 1869 static int sdma_init(struct sdma_engine *sdma) 1870 { 1871 int i, ret; 1872 dma_addr_t ccb_phys; 1873 1874 ret = clk_enable(sdma->clk_ipg); 1875 if (ret) 1876 return ret; 1877 ret = clk_enable(sdma->clk_ahb); 1878 if (ret) 1879 goto disable_clk_ipg; 1880 1881 if (sdma->drvdata->check_ratio && 1882 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) 1883 sdma->clk_ratio = 1; 1884 1885 /* Be sure SDMA has not started yet */ 1886 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1887 1888 sdma->channel_control = dma_alloc_coherent(sdma->dev, 1889 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1890 sizeof(struct sdma_context_data), 1891 &ccb_phys, GFP_KERNEL); 1892 1893 if (!sdma->channel_control) { 1894 ret = -ENOMEM; 1895 goto err_dma_alloc; 1896 } 1897 1898 sdma->context = (void *)sdma->channel_control + 1899 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1900 sdma->context_phys = ccb_phys + 1901 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1902 1903 /* disable all channels */ 1904 for (i = 0; i < sdma->drvdata->num_events; i++) 1905 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1906 1907 /* All channels have priority 0 */ 1908 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1909 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1910 1911 ret = sdma_request_channel0(sdma); 1912 if (ret) 1913 goto err_dma_alloc; 1914 1915 sdma_config_ownership(&sdma->channel[0], false, true, false); 1916 1917 /* Set Command Channel (Channel Zero) */ 1918 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1919 1920 /* Set bits of CONFIG register but with static context switching */ 1921 if (sdma->clk_ratio) 1922 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); 1923 else 1924 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1925 1926 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1927 1928 /* Initializes channel's priorities */ 1929 sdma_set_channel_priority(&sdma->channel[0], 7); 1930 1931 clk_disable(sdma->clk_ipg); 1932 clk_disable(sdma->clk_ahb); 1933 1934 return 0; 1935 1936 err_dma_alloc: 1937 clk_disable(sdma->clk_ahb); 1938 disable_clk_ipg: 1939 clk_disable(sdma->clk_ipg); 1940 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1941 return ret; 1942 } 1943 1944 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1945 { 1946 struct sdma_channel *sdmac = to_sdma_chan(chan); 1947 struct imx_dma_data *data = fn_param; 1948 1949 if (!imx_dma_is_general_purpose(chan)) 1950 return false; 1951 1952 sdmac->data = *data; 1953 chan->private = &sdmac->data; 1954 1955 return true; 1956 } 1957 1958 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1959 struct of_dma *ofdma) 1960 { 1961 struct sdma_engine *sdma = ofdma->of_dma_data; 1962 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1963 struct imx_dma_data data; 1964 1965 if (dma_spec->args_count != 3) 1966 return NULL; 1967 1968 data.dma_request = dma_spec->args[0]; 1969 data.peripheral_type = dma_spec->args[1]; 1970 data.priority = dma_spec->args[2]; 1971 /* 1972 * init dma_request2 to zero, which is not used by the dts. 1973 * For P2P, dma_request2 is init from dma_request_channel(), 1974 * chan->private will point to the imx_dma_data, and in 1975 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will 1976 * be set to sdmac->event_id1. 1977 */ 1978 data.dma_request2 = 0; 1979 1980 return __dma_request_channel(&mask, sdma_filter_fn, &data, 1981 ofdma->of_node); 1982 } 1983 1984 static int sdma_probe(struct platform_device *pdev) 1985 { 1986 const struct of_device_id *of_id = 1987 of_match_device(sdma_dt_ids, &pdev->dev); 1988 struct device_node *np = pdev->dev.of_node; 1989 struct device_node *spba_bus; 1990 const char *fw_name; 1991 int ret; 1992 int irq; 1993 struct resource *iores; 1994 struct resource spba_res; 1995 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1996 int i; 1997 struct sdma_engine *sdma; 1998 s32 *saddr_arr; 1999 const struct sdma_driver_data *drvdata = NULL; 2000 2001 if (of_id) 2002 drvdata = of_id->data; 2003 else if (pdev->id_entry) 2004 drvdata = (void *)pdev->id_entry->driver_data; 2005 2006 if (!drvdata) { 2007 dev_err(&pdev->dev, "unable to find driver data\n"); 2008 return -EINVAL; 2009 } 2010 2011 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2012 if (ret) 2013 return ret; 2014 2015 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); 2016 if (!sdma) 2017 return -ENOMEM; 2018 2019 spin_lock_init(&sdma->channel_0_lock); 2020 2021 sdma->dev = &pdev->dev; 2022 sdma->drvdata = drvdata; 2023 2024 irq = platform_get_irq(pdev, 0); 2025 if (irq < 0) 2026 return irq; 2027 2028 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2029 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); 2030 if (IS_ERR(sdma->regs)) 2031 return PTR_ERR(sdma->regs); 2032 2033 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2034 if (IS_ERR(sdma->clk_ipg)) 2035 return PTR_ERR(sdma->clk_ipg); 2036 2037 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2038 if (IS_ERR(sdma->clk_ahb)) 2039 return PTR_ERR(sdma->clk_ahb); 2040 2041 ret = clk_prepare(sdma->clk_ipg); 2042 if (ret) 2043 return ret; 2044 2045 ret = clk_prepare(sdma->clk_ahb); 2046 if (ret) 2047 goto err_clk; 2048 2049 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", 2050 sdma); 2051 if (ret) 2052 goto err_irq; 2053 2054 sdma->irq = irq; 2055 2056 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 2057 if (!sdma->script_addrs) { 2058 ret = -ENOMEM; 2059 goto err_irq; 2060 } 2061 2062 /* initially no scripts available */ 2063 saddr_arr = (s32 *)sdma->script_addrs; 2064 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) 2065 saddr_arr[i] = -EINVAL; 2066 2067 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 2068 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 2069 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); 2070 2071 INIT_LIST_HEAD(&sdma->dma_device.channels); 2072 /* Initialize channel parameters */ 2073 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2074 struct sdma_channel *sdmac = &sdma->channel[i]; 2075 2076 sdmac->sdma = sdma; 2077 2078 sdmac->channel = i; 2079 sdmac->vc.desc_free = sdma_desc_free; 2080 INIT_WORK(&sdmac->terminate_worker, 2081 sdma_channel_terminate_work); 2082 /* 2083 * Add the channel to the DMAC list. Do not add channel 0 though 2084 * because we need it internally in the SDMA driver. This also means 2085 * that channel 0 in dmaengine counting matches sdma channel 1. 2086 */ 2087 if (i) 2088 vchan_init(&sdmac->vc, &sdma->dma_device); 2089 } 2090 2091 ret = sdma_init(sdma); 2092 if (ret) 2093 goto err_init; 2094 2095 ret = sdma_event_remap(sdma); 2096 if (ret) 2097 goto err_init; 2098 2099 if (sdma->drvdata->script_addrs) 2100 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 2101 if (pdata && pdata->script_addrs) 2102 sdma_add_scripts(sdma, pdata->script_addrs); 2103 2104 sdma->dma_device.dev = &pdev->dev; 2105 2106 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 2107 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 2108 sdma->dma_device.device_tx_status = sdma_tx_status; 2109 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 2110 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 2111 sdma->dma_device.device_config = sdma_config; 2112 sdma->dma_device.device_terminate_all = sdma_terminate_all; 2113 sdma->dma_device.device_synchronize = sdma_channel_synchronize; 2114 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; 2115 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; 2116 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; 2117 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2118 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; 2119 sdma->dma_device.device_issue_pending = sdma_issue_pending; 2120 sdma->dma_device.copy_align = 2; 2121 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); 2122 2123 platform_set_drvdata(pdev, sdma); 2124 2125 ret = dma_async_device_register(&sdma->dma_device); 2126 if (ret) { 2127 dev_err(&pdev->dev, "unable to register\n"); 2128 goto err_init; 2129 } 2130 2131 if (np) { 2132 ret = of_dma_controller_register(np, sdma_xlate, sdma); 2133 if (ret) { 2134 dev_err(&pdev->dev, "failed to register controller\n"); 2135 goto err_register; 2136 } 2137 2138 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); 2139 ret = of_address_to_resource(spba_bus, 0, &spba_res); 2140 if (!ret) { 2141 sdma->spba_start_addr = spba_res.start; 2142 sdma->spba_end_addr = spba_res.end; 2143 } 2144 of_node_put(spba_bus); 2145 } 2146 2147 /* 2148 * Kick off firmware loading as the very last step: 2149 * attempt to load firmware only if we're not on the error path, because 2150 * the firmware callback requires a fully functional and allocated sdma 2151 * instance. 2152 */ 2153 if (pdata) { 2154 ret = sdma_get_firmware(sdma, pdata->fw_name); 2155 if (ret) 2156 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 2157 } else { 2158 /* 2159 * Because that device tree does not encode ROM script address, 2160 * the RAM script in firmware is mandatory for device tree 2161 * probe, otherwise it fails. 2162 */ 2163 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 2164 &fw_name); 2165 if (ret) { 2166 dev_warn(&pdev->dev, "failed to get firmware name\n"); 2167 } else { 2168 ret = sdma_get_firmware(sdma, fw_name); 2169 if (ret) 2170 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 2171 } 2172 } 2173 2174 return 0; 2175 2176 err_register: 2177 dma_async_device_unregister(&sdma->dma_device); 2178 err_init: 2179 kfree(sdma->script_addrs); 2180 err_irq: 2181 clk_unprepare(sdma->clk_ahb); 2182 err_clk: 2183 clk_unprepare(sdma->clk_ipg); 2184 return ret; 2185 } 2186 2187 static int sdma_remove(struct platform_device *pdev) 2188 { 2189 struct sdma_engine *sdma = platform_get_drvdata(pdev); 2190 int i; 2191 2192 devm_free_irq(&pdev->dev, sdma->irq, sdma); 2193 dma_async_device_unregister(&sdma->dma_device); 2194 kfree(sdma->script_addrs); 2195 clk_unprepare(sdma->clk_ahb); 2196 clk_unprepare(sdma->clk_ipg); 2197 /* Kill the tasklet */ 2198 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2199 struct sdma_channel *sdmac = &sdma->channel[i]; 2200 2201 tasklet_kill(&sdmac->vc.task); 2202 sdma_free_chan_resources(&sdmac->vc.chan); 2203 } 2204 2205 platform_set_drvdata(pdev, NULL); 2206 return 0; 2207 } 2208 2209 static struct platform_driver sdma_driver = { 2210 .driver = { 2211 .name = "imx-sdma", 2212 .of_match_table = sdma_dt_ids, 2213 }, 2214 .id_table = sdma_devtypes, 2215 .remove = sdma_remove, 2216 .probe = sdma_probe, 2217 }; 2218 2219 module_platform_driver(sdma_driver); 2220 2221 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 2222 MODULE_DESCRIPTION("i.MX SDMA driver"); 2223 #if IS_ENABLED(CONFIG_SOC_IMX6Q) 2224 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin"); 2225 #endif 2226 #if IS_ENABLED(CONFIG_SOC_IMX7D) 2227 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin"); 2228 #endif 2229 MODULE_LICENSE("GPL"); 2230