1 /* 2 * drivers/dma/imx-sdma.c 3 * 4 * This file contains a driver for the Freescale Smart DMA engine 5 * 6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 7 * 8 * Based on code from Freescale: 9 * 10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 11 * 12 * The code contained herein is licensed under the GNU General Public 13 * License. You may obtain a copy of the GNU General Public License 14 * Version 2 or later at the following locations: 15 * 16 * http://www.opensource.org/licenses/gpl-license.html 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/mm.h> 25 #include <linux/interrupt.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/sched.h> 29 #include <linux/semaphore.h> 30 #include <linux/spinlock.h> 31 #include <linux/device.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/firmware.h> 34 #include <linux/slab.h> 35 #include <linux/platform_device.h> 36 #include <linux/dmaengine.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_dma.h> 40 41 #include <asm/irq.h> 42 #include <linux/platform_data/dma-imx-sdma.h> 43 #include <linux/platform_data/dma-imx.h> 44 45 #include "dmaengine.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * Mode/Count of data node descriptors - IPCv2 128 */ 129 struct sdma_mode_count { 130 u32 count : 16; /* size of the buffer pointed by this BD */ 131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 132 u32 command : 8; /* command mostlky used for channel 0 */ 133 }; 134 135 /* 136 * Buffer descriptor 137 */ 138 struct sdma_buffer_descriptor { 139 struct sdma_mode_count mode; 140 u32 buffer_addr; /* address of the buffer described */ 141 u32 ext_buffer_addr; /* extended buffer address */ 142 } __attribute__ ((packed)); 143 144 /** 145 * struct sdma_channel_control - Channel control Block 146 * 147 * @current_bd_ptr current buffer descriptor processed 148 * @base_bd_ptr first element of buffer descriptor array 149 * @unused padding. The SDMA engine expects an array of 128 byte 150 * control blocks 151 */ 152 struct sdma_channel_control { 153 u32 current_bd_ptr; 154 u32 base_bd_ptr; 155 u32 unused[2]; 156 } __attribute__ ((packed)); 157 158 /** 159 * struct sdma_state_registers - SDMA context for a channel 160 * 161 * @pc: program counter 162 * @t: test bit: status of arithmetic & test instruction 163 * @rpc: return program counter 164 * @sf: source fault while loading data 165 * @spc: loop start program counter 166 * @df: destination fault while storing data 167 * @epc: loop end program counter 168 * @lm: loop mode 169 */ 170 struct sdma_state_registers { 171 u32 pc :14; 172 u32 unused1: 1; 173 u32 t : 1; 174 u32 rpc :14; 175 u32 unused0: 1; 176 u32 sf : 1; 177 u32 spc :14; 178 u32 unused2: 1; 179 u32 df : 1; 180 u32 epc :14; 181 u32 lm : 2; 182 } __attribute__ ((packed)); 183 184 /** 185 * struct sdma_context_data - sdma context specific to a channel 186 * 187 * @channel_state: channel state bits 188 * @gReg: general registers 189 * @mda: burst dma destination address register 190 * @msa: burst dma source address register 191 * @ms: burst dma status register 192 * @md: burst dma data register 193 * @pda: peripheral dma destination address register 194 * @psa: peripheral dma source address register 195 * @ps: peripheral dma status register 196 * @pd: peripheral dma data register 197 * @ca: CRC polynomial register 198 * @cs: CRC accumulator register 199 * @dda: dedicated core destination address register 200 * @dsa: dedicated core source address register 201 * @ds: dedicated core status register 202 * @dd: dedicated core data register 203 */ 204 struct sdma_context_data { 205 struct sdma_state_registers channel_state; 206 u32 gReg[8]; 207 u32 mda; 208 u32 msa; 209 u32 ms; 210 u32 md; 211 u32 pda; 212 u32 psa; 213 u32 ps; 214 u32 pd; 215 u32 ca; 216 u32 cs; 217 u32 dda; 218 u32 dsa; 219 u32 ds; 220 u32 dd; 221 u32 scratch0; 222 u32 scratch1; 223 u32 scratch2; 224 u32 scratch3; 225 u32 scratch4; 226 u32 scratch5; 227 u32 scratch6; 228 u32 scratch7; 229 } __attribute__ ((packed)); 230 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 232 233 struct sdma_engine; 234 235 /** 236 * struct sdma_channel - housekeeping for a SDMA channel 237 * 238 * @sdma pointer to the SDMA engine for this channel 239 * @channel the channel number, matches dmaengine chan_id + 1 240 * @direction transfer type. Needed for setting SDMA script 241 * @peripheral_type Peripheral type. Needed for setting SDMA script 242 * @event_id0 aka dma request line 243 * @event_id1 for channels that use 2 events 244 * @word_size peripheral access size 245 * @buf_tail ID of the buffer that was processed 246 * @num_bd max NUM_BD. number of descriptors currently handling 247 */ 248 struct sdma_channel { 249 struct sdma_engine *sdma; 250 unsigned int channel; 251 enum dma_transfer_direction direction; 252 enum sdma_peripheral_type peripheral_type; 253 unsigned int event_id0; 254 unsigned int event_id1; 255 enum dma_slave_buswidth word_size; 256 unsigned int buf_tail; 257 unsigned int num_bd; 258 struct sdma_buffer_descriptor *bd; 259 dma_addr_t bd_phys; 260 unsigned int pc_from_device, pc_to_device; 261 unsigned long flags; 262 dma_addr_t per_address; 263 unsigned long event_mask[2]; 264 unsigned long watermark_level; 265 u32 shp_addr, per_addr; 266 struct dma_chan chan; 267 spinlock_t lock; 268 struct dma_async_tx_descriptor desc; 269 enum dma_status status; 270 unsigned int chn_count; 271 unsigned int chn_real_count; 272 struct tasklet_struct tasklet; 273 }; 274 275 #define IMX_DMA_SG_LOOP BIT(0) 276 277 #define MAX_DMA_CHANNELS 32 278 #define MXC_SDMA_DEFAULT_PRIORITY 1 279 #define MXC_SDMA_MIN_PRIORITY 1 280 #define MXC_SDMA_MAX_PRIORITY 7 281 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453 283 284 /** 285 * struct sdma_firmware_header - Layout of the firmware image 286 * 287 * @magic "SDMA" 288 * @version_major increased whenever layout of struct sdma_script_start_addrs 289 * changes. 290 * @version_minor firmware minor version (for binary compatible changes) 291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image 292 * @num_script_addrs Number of script addresses in this image 293 * @ram_code_start offset of SDMA ram image in this firmware image 294 * @ram_code_size size of SDMA ram image 295 * @script_addrs Stores the start address of the SDMA scripts 296 * (in SDMA memory space) 297 */ 298 struct sdma_firmware_header { 299 u32 magic; 300 u32 version_major; 301 u32 version_minor; 302 u32 script_addrs_start; 303 u32 num_script_addrs; 304 u32 ram_code_start; 305 u32 ram_code_size; 306 }; 307 308 struct sdma_driver_data { 309 int chnenbl0; 310 int num_events; 311 struct sdma_script_start_addrs *script_addrs; 312 }; 313 314 struct sdma_engine { 315 struct device *dev; 316 struct device_dma_parameters dma_parms; 317 struct sdma_channel channel[MAX_DMA_CHANNELS]; 318 struct sdma_channel_control *channel_control; 319 void __iomem *regs; 320 struct sdma_context_data *context; 321 dma_addr_t context_phys; 322 struct dma_device dma_device; 323 struct clk *clk_ipg; 324 struct clk *clk_ahb; 325 spinlock_t channel_0_lock; 326 u32 script_number; 327 struct sdma_script_start_addrs *script_addrs; 328 const struct sdma_driver_data *drvdata; 329 }; 330 331 static struct sdma_driver_data sdma_imx31 = { 332 .chnenbl0 = SDMA_CHNENBL0_IMX31, 333 .num_events = 32, 334 }; 335 336 static struct sdma_script_start_addrs sdma_script_imx25 = { 337 .ap_2_ap_addr = 729, 338 .uart_2_mcu_addr = 904, 339 .per_2_app_addr = 1255, 340 .mcu_2_app_addr = 834, 341 .uartsh_2_mcu_addr = 1120, 342 .per_2_shp_addr = 1329, 343 .mcu_2_shp_addr = 1048, 344 .ata_2_mcu_addr = 1560, 345 .mcu_2_ata_addr = 1479, 346 .app_2_per_addr = 1189, 347 .app_2_mcu_addr = 770, 348 .shp_2_per_addr = 1407, 349 .shp_2_mcu_addr = 979, 350 }; 351 352 static struct sdma_driver_data sdma_imx25 = { 353 .chnenbl0 = SDMA_CHNENBL0_IMX35, 354 .num_events = 48, 355 .script_addrs = &sdma_script_imx25, 356 }; 357 358 static struct sdma_driver_data sdma_imx35 = { 359 .chnenbl0 = SDMA_CHNENBL0_IMX35, 360 .num_events = 48, 361 }; 362 363 static struct sdma_script_start_addrs sdma_script_imx51 = { 364 .ap_2_ap_addr = 642, 365 .uart_2_mcu_addr = 817, 366 .mcu_2_app_addr = 747, 367 .mcu_2_shp_addr = 961, 368 .ata_2_mcu_addr = 1473, 369 .mcu_2_ata_addr = 1392, 370 .app_2_per_addr = 1033, 371 .app_2_mcu_addr = 683, 372 .shp_2_per_addr = 1251, 373 .shp_2_mcu_addr = 892, 374 }; 375 376 static struct sdma_driver_data sdma_imx51 = { 377 .chnenbl0 = SDMA_CHNENBL0_IMX35, 378 .num_events = 48, 379 .script_addrs = &sdma_script_imx51, 380 }; 381 382 static struct sdma_script_start_addrs sdma_script_imx53 = { 383 .ap_2_ap_addr = 642, 384 .app_2_mcu_addr = 683, 385 .mcu_2_app_addr = 747, 386 .uart_2_mcu_addr = 817, 387 .shp_2_mcu_addr = 891, 388 .mcu_2_shp_addr = 960, 389 .uartsh_2_mcu_addr = 1032, 390 .spdif_2_mcu_addr = 1100, 391 .mcu_2_spdif_addr = 1134, 392 .firi_2_mcu_addr = 1193, 393 .mcu_2_firi_addr = 1290, 394 }; 395 396 static struct sdma_driver_data sdma_imx53 = { 397 .chnenbl0 = SDMA_CHNENBL0_IMX35, 398 .num_events = 48, 399 .script_addrs = &sdma_script_imx53, 400 }; 401 402 static struct sdma_script_start_addrs sdma_script_imx6q = { 403 .ap_2_ap_addr = 642, 404 .uart_2_mcu_addr = 817, 405 .mcu_2_app_addr = 747, 406 .per_2_per_addr = 6331, 407 .uartsh_2_mcu_addr = 1032, 408 .mcu_2_shp_addr = 960, 409 .app_2_mcu_addr = 683, 410 .shp_2_mcu_addr = 891, 411 .spdif_2_mcu_addr = 1100, 412 .mcu_2_spdif_addr = 1134, 413 }; 414 415 static struct sdma_driver_data sdma_imx6q = { 416 .chnenbl0 = SDMA_CHNENBL0_IMX35, 417 .num_events = 48, 418 .script_addrs = &sdma_script_imx6q, 419 }; 420 421 static struct platform_device_id sdma_devtypes[] = { 422 { 423 .name = "imx25-sdma", 424 .driver_data = (unsigned long)&sdma_imx25, 425 }, { 426 .name = "imx31-sdma", 427 .driver_data = (unsigned long)&sdma_imx31, 428 }, { 429 .name = "imx35-sdma", 430 .driver_data = (unsigned long)&sdma_imx35, 431 }, { 432 .name = "imx51-sdma", 433 .driver_data = (unsigned long)&sdma_imx51, 434 }, { 435 .name = "imx53-sdma", 436 .driver_data = (unsigned long)&sdma_imx53, 437 }, { 438 .name = "imx6q-sdma", 439 .driver_data = (unsigned long)&sdma_imx6q, 440 }, { 441 /* sentinel */ 442 } 443 }; 444 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 445 446 static const struct of_device_id sdma_dt_ids[] = { 447 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 448 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 449 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 450 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 451 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 452 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, 453 { /* sentinel */ } 454 }; 455 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 456 457 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 458 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 459 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 460 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 461 462 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 463 { 464 u32 chnenbl0 = sdma->drvdata->chnenbl0; 465 return chnenbl0 + event * 4; 466 } 467 468 static int sdma_config_ownership(struct sdma_channel *sdmac, 469 bool event_override, bool mcu_override, bool dsp_override) 470 { 471 struct sdma_engine *sdma = sdmac->sdma; 472 int channel = sdmac->channel; 473 unsigned long evt, mcu, dsp; 474 475 if (event_override && mcu_override && dsp_override) 476 return -EINVAL; 477 478 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 479 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 480 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 481 482 if (dsp_override) 483 __clear_bit(channel, &dsp); 484 else 485 __set_bit(channel, &dsp); 486 487 if (event_override) 488 __clear_bit(channel, &evt); 489 else 490 __set_bit(channel, &evt); 491 492 if (mcu_override) 493 __clear_bit(channel, &mcu); 494 else 495 __set_bit(channel, &mcu); 496 497 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 498 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 499 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 500 501 return 0; 502 } 503 504 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 505 { 506 writel(BIT(channel), sdma->regs + SDMA_H_START); 507 } 508 509 /* 510 * sdma_run_channel0 - run a channel and wait till it's done 511 */ 512 static int sdma_run_channel0(struct sdma_engine *sdma) 513 { 514 int ret; 515 unsigned long timeout = 500; 516 517 sdma_enable_channel(sdma, 0); 518 519 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { 520 if (timeout-- <= 0) 521 break; 522 udelay(1); 523 } 524 525 if (ret) { 526 /* Clear the interrupt status */ 527 writel_relaxed(ret, sdma->regs + SDMA_H_INTR); 528 } else { 529 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 530 } 531 532 return ret ? 0 : -ETIMEDOUT; 533 } 534 535 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 536 u32 address) 537 { 538 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 539 void *buf_virt; 540 dma_addr_t buf_phys; 541 int ret; 542 unsigned long flags; 543 544 buf_virt = dma_alloc_coherent(NULL, 545 size, 546 &buf_phys, GFP_KERNEL); 547 if (!buf_virt) { 548 return -ENOMEM; 549 } 550 551 spin_lock_irqsave(&sdma->channel_0_lock, flags); 552 553 bd0->mode.command = C0_SETPM; 554 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 555 bd0->mode.count = size / 2; 556 bd0->buffer_addr = buf_phys; 557 bd0->ext_buffer_addr = address; 558 559 memcpy(buf_virt, buf, size); 560 561 ret = sdma_run_channel0(sdma); 562 563 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 564 565 dma_free_coherent(NULL, size, buf_virt, buf_phys); 566 567 return ret; 568 } 569 570 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 571 { 572 struct sdma_engine *sdma = sdmac->sdma; 573 int channel = sdmac->channel; 574 unsigned long val; 575 u32 chnenbl = chnenbl_ofs(sdma, event); 576 577 val = readl_relaxed(sdma->regs + chnenbl); 578 __set_bit(channel, &val); 579 writel_relaxed(val, sdma->regs + chnenbl); 580 } 581 582 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 583 { 584 struct sdma_engine *sdma = sdmac->sdma; 585 int channel = sdmac->channel; 586 u32 chnenbl = chnenbl_ofs(sdma, event); 587 unsigned long val; 588 589 val = readl_relaxed(sdma->regs + chnenbl); 590 __clear_bit(channel, &val); 591 writel_relaxed(val, sdma->regs + chnenbl); 592 } 593 594 static void sdma_handle_channel_loop(struct sdma_channel *sdmac) 595 { 596 struct sdma_buffer_descriptor *bd; 597 598 /* 599 * loop mode. Iterate over descriptors, re-setup them and 600 * call callback function. 601 */ 602 while (1) { 603 bd = &sdmac->bd[sdmac->buf_tail]; 604 605 if (bd->mode.status & BD_DONE) 606 break; 607 608 if (bd->mode.status & BD_RROR) 609 sdmac->status = DMA_ERROR; 610 611 bd->mode.status |= BD_DONE; 612 sdmac->buf_tail++; 613 sdmac->buf_tail %= sdmac->num_bd; 614 615 if (sdmac->desc.callback) 616 sdmac->desc.callback(sdmac->desc.callback_param); 617 } 618 } 619 620 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) 621 { 622 struct sdma_buffer_descriptor *bd; 623 int i, error = 0; 624 625 sdmac->chn_real_count = 0; 626 /* 627 * non loop mode. Iterate over all descriptors, collect 628 * errors and call callback function 629 */ 630 for (i = 0; i < sdmac->num_bd; i++) { 631 bd = &sdmac->bd[i]; 632 633 if (bd->mode.status & (BD_DONE | BD_RROR)) 634 error = -EIO; 635 sdmac->chn_real_count += bd->mode.count; 636 } 637 638 if (error) 639 sdmac->status = DMA_ERROR; 640 else 641 sdmac->status = DMA_COMPLETE; 642 643 dma_cookie_complete(&sdmac->desc); 644 if (sdmac->desc.callback) 645 sdmac->desc.callback(sdmac->desc.callback_param); 646 } 647 648 static void sdma_tasklet(unsigned long data) 649 { 650 struct sdma_channel *sdmac = (struct sdma_channel *) data; 651 652 if (sdmac->flags & IMX_DMA_SG_LOOP) 653 sdma_handle_channel_loop(sdmac); 654 else 655 mxc_sdma_handle_channel_normal(sdmac); 656 } 657 658 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 659 { 660 struct sdma_engine *sdma = dev_id; 661 unsigned long stat; 662 663 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 664 /* not interested in channel 0 interrupts */ 665 stat &= ~1; 666 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 667 668 while (stat) { 669 int channel = fls(stat) - 1; 670 struct sdma_channel *sdmac = &sdma->channel[channel]; 671 672 tasklet_schedule(&sdmac->tasklet); 673 674 __clear_bit(channel, &stat); 675 } 676 677 return IRQ_HANDLED; 678 } 679 680 /* 681 * sets the pc of SDMA script according to the peripheral type 682 */ 683 static void sdma_get_pc(struct sdma_channel *sdmac, 684 enum sdma_peripheral_type peripheral_type) 685 { 686 struct sdma_engine *sdma = sdmac->sdma; 687 int per_2_emi = 0, emi_2_per = 0; 688 /* 689 * These are needed once we start to support transfers between 690 * two peripherals or memory-to-memory transfers 691 */ 692 int per_2_per = 0, emi_2_emi = 0; 693 694 sdmac->pc_from_device = 0; 695 sdmac->pc_to_device = 0; 696 697 switch (peripheral_type) { 698 case IMX_DMATYPE_MEMORY: 699 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 700 break; 701 case IMX_DMATYPE_DSP: 702 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 703 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 704 break; 705 case IMX_DMATYPE_FIRI: 706 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 707 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 708 break; 709 case IMX_DMATYPE_UART: 710 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 711 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 712 break; 713 case IMX_DMATYPE_UART_SP: 714 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 715 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 716 break; 717 case IMX_DMATYPE_ATA: 718 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 719 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 720 break; 721 case IMX_DMATYPE_CSPI: 722 case IMX_DMATYPE_EXT: 723 case IMX_DMATYPE_SSI: 724 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 725 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 726 break; 727 case IMX_DMATYPE_SSI_DUAL: 728 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; 729 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; 730 break; 731 case IMX_DMATYPE_SSI_SP: 732 case IMX_DMATYPE_MMC: 733 case IMX_DMATYPE_SDHC: 734 case IMX_DMATYPE_CSPI_SP: 735 case IMX_DMATYPE_ESAI: 736 case IMX_DMATYPE_MSHC_SP: 737 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 738 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 739 break; 740 case IMX_DMATYPE_ASRC: 741 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 742 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 743 per_2_per = sdma->script_addrs->per_2_per_addr; 744 break; 745 case IMX_DMATYPE_MSHC: 746 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 747 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 748 break; 749 case IMX_DMATYPE_CCM: 750 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 751 break; 752 case IMX_DMATYPE_SPDIF: 753 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 754 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 755 break; 756 case IMX_DMATYPE_IPU_MEMORY: 757 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 758 break; 759 default: 760 break; 761 } 762 763 sdmac->pc_from_device = per_2_emi; 764 sdmac->pc_to_device = emi_2_per; 765 } 766 767 static int sdma_load_context(struct sdma_channel *sdmac) 768 { 769 struct sdma_engine *sdma = sdmac->sdma; 770 int channel = sdmac->channel; 771 int load_address; 772 struct sdma_context_data *context = sdma->context; 773 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 774 int ret; 775 unsigned long flags; 776 777 if (sdmac->direction == DMA_DEV_TO_MEM) { 778 load_address = sdmac->pc_from_device; 779 } else { 780 load_address = sdmac->pc_to_device; 781 } 782 783 if (load_address < 0) 784 return load_address; 785 786 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 787 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 788 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 789 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 790 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 791 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 792 793 spin_lock_irqsave(&sdma->channel_0_lock, flags); 794 795 memset(context, 0, sizeof(*context)); 796 context->channel_state.pc = load_address; 797 798 /* Send by context the event mask,base address for peripheral 799 * and watermark level 800 */ 801 context->gReg[0] = sdmac->event_mask[1]; 802 context->gReg[1] = sdmac->event_mask[0]; 803 context->gReg[2] = sdmac->per_addr; 804 context->gReg[6] = sdmac->shp_addr; 805 context->gReg[7] = sdmac->watermark_level; 806 807 bd0->mode.command = C0_SETDM; 808 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 809 bd0->mode.count = sizeof(*context) / 4; 810 bd0->buffer_addr = sdma->context_phys; 811 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 812 ret = sdma_run_channel0(sdma); 813 814 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 815 816 return ret; 817 } 818 819 static void sdma_disable_channel(struct sdma_channel *sdmac) 820 { 821 struct sdma_engine *sdma = sdmac->sdma; 822 int channel = sdmac->channel; 823 824 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 825 sdmac->status = DMA_ERROR; 826 } 827 828 static int sdma_config_channel(struct sdma_channel *sdmac) 829 { 830 int ret; 831 832 sdma_disable_channel(sdmac); 833 834 sdmac->event_mask[0] = 0; 835 sdmac->event_mask[1] = 0; 836 sdmac->shp_addr = 0; 837 sdmac->per_addr = 0; 838 839 if (sdmac->event_id0) { 840 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 841 return -EINVAL; 842 sdma_event_enable(sdmac, sdmac->event_id0); 843 } 844 845 switch (sdmac->peripheral_type) { 846 case IMX_DMATYPE_DSP: 847 sdma_config_ownership(sdmac, false, true, true); 848 break; 849 case IMX_DMATYPE_MEMORY: 850 sdma_config_ownership(sdmac, false, true, false); 851 break; 852 default: 853 sdma_config_ownership(sdmac, true, true, false); 854 break; 855 } 856 857 sdma_get_pc(sdmac, sdmac->peripheral_type); 858 859 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 860 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 861 /* Handle multiple event channels differently */ 862 if (sdmac->event_id1) { 863 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); 864 if (sdmac->event_id1 > 31) 865 __set_bit(31, &sdmac->watermark_level); 866 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); 867 if (sdmac->event_id0 > 31) 868 __set_bit(30, &sdmac->watermark_level); 869 } else { 870 __set_bit(sdmac->event_id0, sdmac->event_mask); 871 } 872 /* Watermark Level */ 873 sdmac->watermark_level |= sdmac->watermark_level; 874 /* Address */ 875 sdmac->shp_addr = sdmac->per_address; 876 } else { 877 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 878 } 879 880 ret = sdma_load_context(sdmac); 881 882 return ret; 883 } 884 885 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 886 unsigned int priority) 887 { 888 struct sdma_engine *sdma = sdmac->sdma; 889 int channel = sdmac->channel; 890 891 if (priority < MXC_SDMA_MIN_PRIORITY 892 || priority > MXC_SDMA_MAX_PRIORITY) { 893 return -EINVAL; 894 } 895 896 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 897 898 return 0; 899 } 900 901 static int sdma_request_channel(struct sdma_channel *sdmac) 902 { 903 struct sdma_engine *sdma = sdmac->sdma; 904 int channel = sdmac->channel; 905 int ret = -EBUSY; 906 907 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); 908 if (!sdmac->bd) { 909 ret = -ENOMEM; 910 goto out; 911 } 912 913 memset(sdmac->bd, 0, PAGE_SIZE); 914 915 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; 916 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 917 918 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); 919 return 0; 920 out: 921 922 return ret; 923 } 924 925 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 926 { 927 return container_of(chan, struct sdma_channel, chan); 928 } 929 930 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) 931 { 932 unsigned long flags; 933 struct sdma_channel *sdmac = to_sdma_chan(tx->chan); 934 dma_cookie_t cookie; 935 936 spin_lock_irqsave(&sdmac->lock, flags); 937 938 cookie = dma_cookie_assign(tx); 939 940 spin_unlock_irqrestore(&sdmac->lock, flags); 941 942 return cookie; 943 } 944 945 static int sdma_alloc_chan_resources(struct dma_chan *chan) 946 { 947 struct sdma_channel *sdmac = to_sdma_chan(chan); 948 struct imx_dma_data *data = chan->private; 949 int prio, ret; 950 951 if (!data) 952 return -EINVAL; 953 954 switch (data->priority) { 955 case DMA_PRIO_HIGH: 956 prio = 3; 957 break; 958 case DMA_PRIO_MEDIUM: 959 prio = 2; 960 break; 961 case DMA_PRIO_LOW: 962 default: 963 prio = 1; 964 break; 965 } 966 967 sdmac->peripheral_type = data->peripheral_type; 968 sdmac->event_id0 = data->dma_request; 969 970 clk_enable(sdmac->sdma->clk_ipg); 971 clk_enable(sdmac->sdma->clk_ahb); 972 973 ret = sdma_request_channel(sdmac); 974 if (ret) 975 return ret; 976 977 ret = sdma_set_channel_priority(sdmac, prio); 978 if (ret) 979 return ret; 980 981 dma_async_tx_descriptor_init(&sdmac->desc, chan); 982 sdmac->desc.tx_submit = sdma_tx_submit; 983 /* txd.flags will be overwritten in prep funcs */ 984 sdmac->desc.flags = DMA_CTRL_ACK; 985 986 return 0; 987 } 988 989 static void sdma_free_chan_resources(struct dma_chan *chan) 990 { 991 struct sdma_channel *sdmac = to_sdma_chan(chan); 992 struct sdma_engine *sdma = sdmac->sdma; 993 994 sdma_disable_channel(sdmac); 995 996 if (sdmac->event_id0) 997 sdma_event_disable(sdmac, sdmac->event_id0); 998 if (sdmac->event_id1) 999 sdma_event_disable(sdmac, sdmac->event_id1); 1000 1001 sdmac->event_id0 = 0; 1002 sdmac->event_id1 = 0; 1003 1004 sdma_set_channel_priority(sdmac, 0); 1005 1006 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); 1007 1008 clk_disable(sdma->clk_ipg); 1009 clk_disable(sdma->clk_ahb); 1010 } 1011 1012 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1013 struct dma_chan *chan, struct scatterlist *sgl, 1014 unsigned int sg_len, enum dma_transfer_direction direction, 1015 unsigned long flags, void *context) 1016 { 1017 struct sdma_channel *sdmac = to_sdma_chan(chan); 1018 struct sdma_engine *sdma = sdmac->sdma; 1019 int ret, i, count; 1020 int channel = sdmac->channel; 1021 struct scatterlist *sg; 1022 1023 if (sdmac->status == DMA_IN_PROGRESS) 1024 return NULL; 1025 sdmac->status = DMA_IN_PROGRESS; 1026 1027 sdmac->flags = 0; 1028 1029 sdmac->buf_tail = 0; 1030 1031 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1032 sg_len, channel); 1033 1034 sdmac->direction = direction; 1035 ret = sdma_load_context(sdmac); 1036 if (ret) 1037 goto err_out; 1038 1039 if (sg_len > NUM_BD) { 1040 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1041 channel, sg_len, NUM_BD); 1042 ret = -EINVAL; 1043 goto err_out; 1044 } 1045 1046 sdmac->chn_count = 0; 1047 for_each_sg(sgl, sg, sg_len, i) { 1048 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1049 int param; 1050 1051 bd->buffer_addr = sg->dma_address; 1052 1053 count = sg_dma_len(sg); 1054 1055 if (count > 0xffff) { 1056 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1057 channel, count, 0xffff); 1058 ret = -EINVAL; 1059 goto err_out; 1060 } 1061 1062 bd->mode.count = count; 1063 sdmac->chn_count += count; 1064 1065 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { 1066 ret = -EINVAL; 1067 goto err_out; 1068 } 1069 1070 switch (sdmac->word_size) { 1071 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1072 bd->mode.command = 0; 1073 if (count & 3 || sg->dma_address & 3) 1074 return NULL; 1075 break; 1076 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1077 bd->mode.command = 2; 1078 if (count & 1 || sg->dma_address & 1) 1079 return NULL; 1080 break; 1081 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1082 bd->mode.command = 1; 1083 break; 1084 default: 1085 return NULL; 1086 } 1087 1088 param = BD_DONE | BD_EXTD | BD_CONT; 1089 1090 if (i + 1 == sg_len) { 1091 param |= BD_INTR; 1092 param |= BD_LAST; 1093 param &= ~BD_CONT; 1094 } 1095 1096 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1097 i, count, (u64)sg->dma_address, 1098 param & BD_WRAP ? "wrap" : "", 1099 param & BD_INTR ? " intr" : ""); 1100 1101 bd->mode.status = param; 1102 } 1103 1104 sdmac->num_bd = sg_len; 1105 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1106 1107 return &sdmac->desc; 1108 err_out: 1109 sdmac->status = DMA_ERROR; 1110 return NULL; 1111 } 1112 1113 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1114 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1115 size_t period_len, enum dma_transfer_direction direction, 1116 unsigned long flags, void *context) 1117 { 1118 struct sdma_channel *sdmac = to_sdma_chan(chan); 1119 struct sdma_engine *sdma = sdmac->sdma; 1120 int num_periods = buf_len / period_len; 1121 int channel = sdmac->channel; 1122 int ret, i = 0, buf = 0; 1123 1124 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1125 1126 if (sdmac->status == DMA_IN_PROGRESS) 1127 return NULL; 1128 1129 sdmac->status = DMA_IN_PROGRESS; 1130 1131 sdmac->buf_tail = 0; 1132 1133 sdmac->flags |= IMX_DMA_SG_LOOP; 1134 sdmac->direction = direction; 1135 ret = sdma_load_context(sdmac); 1136 if (ret) 1137 goto err_out; 1138 1139 if (num_periods > NUM_BD) { 1140 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1141 channel, num_periods, NUM_BD); 1142 goto err_out; 1143 } 1144 1145 if (period_len > 0xffff) { 1146 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", 1147 channel, period_len, 0xffff); 1148 goto err_out; 1149 } 1150 1151 while (buf < buf_len) { 1152 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1153 int param; 1154 1155 bd->buffer_addr = dma_addr; 1156 1157 bd->mode.count = period_len; 1158 1159 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1160 goto err_out; 1161 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1162 bd->mode.command = 0; 1163 else 1164 bd->mode.command = sdmac->word_size; 1165 1166 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1167 if (i + 1 == num_periods) 1168 param |= BD_WRAP; 1169 1170 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1171 i, period_len, (u64)dma_addr, 1172 param & BD_WRAP ? "wrap" : "", 1173 param & BD_INTR ? " intr" : ""); 1174 1175 bd->mode.status = param; 1176 1177 dma_addr += period_len; 1178 buf += period_len; 1179 1180 i++; 1181 } 1182 1183 sdmac->num_bd = num_periods; 1184 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1185 1186 return &sdmac->desc; 1187 err_out: 1188 sdmac->status = DMA_ERROR; 1189 return NULL; 1190 } 1191 1192 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1193 unsigned long arg) 1194 { 1195 struct sdma_channel *sdmac = to_sdma_chan(chan); 1196 struct dma_slave_config *dmaengine_cfg = (void *)arg; 1197 1198 switch (cmd) { 1199 case DMA_TERMINATE_ALL: 1200 sdma_disable_channel(sdmac); 1201 return 0; 1202 case DMA_SLAVE_CONFIG: 1203 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 1204 sdmac->per_address = dmaengine_cfg->src_addr; 1205 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1206 dmaengine_cfg->src_addr_width; 1207 sdmac->word_size = dmaengine_cfg->src_addr_width; 1208 } else { 1209 sdmac->per_address = dmaengine_cfg->dst_addr; 1210 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1211 dmaengine_cfg->dst_addr_width; 1212 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1213 } 1214 sdmac->direction = dmaengine_cfg->direction; 1215 return sdma_config_channel(sdmac); 1216 default: 1217 return -ENOSYS; 1218 } 1219 1220 return -EINVAL; 1221 } 1222 1223 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1224 dma_cookie_t cookie, 1225 struct dma_tx_state *txstate) 1226 { 1227 struct sdma_channel *sdmac = to_sdma_chan(chan); 1228 1229 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1230 sdmac->chn_count - sdmac->chn_real_count); 1231 1232 return sdmac->status; 1233 } 1234 1235 static void sdma_issue_pending(struct dma_chan *chan) 1236 { 1237 struct sdma_channel *sdmac = to_sdma_chan(chan); 1238 struct sdma_engine *sdma = sdmac->sdma; 1239 1240 if (sdmac->status == DMA_IN_PROGRESS) 1241 sdma_enable_channel(sdma, sdmac->channel); 1242 } 1243 1244 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1245 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1246 1247 static void sdma_add_scripts(struct sdma_engine *sdma, 1248 const struct sdma_script_start_addrs *addr) 1249 { 1250 s32 *addr_arr = (u32 *)addr; 1251 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1252 int i; 1253 1254 /* use the default firmware in ROM if missing external firmware */ 1255 if (!sdma->script_number) 1256 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1257 1258 for (i = 0; i < sdma->script_number; i++) 1259 if (addr_arr[i] > 0) 1260 saddr_arr[i] = addr_arr[i]; 1261 } 1262 1263 static void sdma_load_firmware(const struct firmware *fw, void *context) 1264 { 1265 struct sdma_engine *sdma = context; 1266 const struct sdma_firmware_header *header; 1267 const struct sdma_script_start_addrs *addr; 1268 unsigned short *ram_code; 1269 1270 if (!fw) { 1271 dev_err(sdma->dev, "firmware not found\n"); 1272 return; 1273 } 1274 1275 if (fw->size < sizeof(*header)) 1276 goto err_firmware; 1277 1278 header = (struct sdma_firmware_header *)fw->data; 1279 1280 if (header->magic != SDMA_FIRMWARE_MAGIC) 1281 goto err_firmware; 1282 if (header->ram_code_start + header->ram_code_size > fw->size) 1283 goto err_firmware; 1284 switch (header->version_major) { 1285 case 1: 1286 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1287 break; 1288 case 2: 1289 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1290 break; 1291 default: 1292 dev_err(sdma->dev, "unknown firmware version\n"); 1293 goto err_firmware; 1294 } 1295 1296 addr = (void *)header + header->script_addrs_start; 1297 ram_code = (void *)header + header->ram_code_start; 1298 1299 clk_enable(sdma->clk_ipg); 1300 clk_enable(sdma->clk_ahb); 1301 /* download the RAM image for SDMA */ 1302 sdma_load_script(sdma, ram_code, 1303 header->ram_code_size, 1304 addr->ram_code_start_addr); 1305 clk_disable(sdma->clk_ipg); 1306 clk_disable(sdma->clk_ahb); 1307 1308 sdma_add_scripts(sdma, addr); 1309 1310 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1311 header->version_major, 1312 header->version_minor); 1313 1314 err_firmware: 1315 release_firmware(fw); 1316 } 1317 1318 static int __init sdma_get_firmware(struct sdma_engine *sdma, 1319 const char *fw_name) 1320 { 1321 int ret; 1322 1323 ret = request_firmware_nowait(THIS_MODULE, 1324 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1325 GFP_KERNEL, sdma, sdma_load_firmware); 1326 1327 return ret; 1328 } 1329 1330 static int __init sdma_init(struct sdma_engine *sdma) 1331 { 1332 int i, ret; 1333 dma_addr_t ccb_phys; 1334 1335 clk_enable(sdma->clk_ipg); 1336 clk_enable(sdma->clk_ahb); 1337 1338 /* Be sure SDMA has not started yet */ 1339 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1340 1341 sdma->channel_control = dma_alloc_coherent(NULL, 1342 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1343 sizeof(struct sdma_context_data), 1344 &ccb_phys, GFP_KERNEL); 1345 1346 if (!sdma->channel_control) { 1347 ret = -ENOMEM; 1348 goto err_dma_alloc; 1349 } 1350 1351 sdma->context = (void *)sdma->channel_control + 1352 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1353 sdma->context_phys = ccb_phys + 1354 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1355 1356 /* Zero-out the CCB structures array just allocated */ 1357 memset(sdma->channel_control, 0, 1358 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1359 1360 /* disable all channels */ 1361 for (i = 0; i < sdma->drvdata->num_events; i++) 1362 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1363 1364 /* All channels have priority 0 */ 1365 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1366 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1367 1368 ret = sdma_request_channel(&sdma->channel[0]); 1369 if (ret) 1370 goto err_dma_alloc; 1371 1372 sdma_config_ownership(&sdma->channel[0], false, true, false); 1373 1374 /* Set Command Channel (Channel Zero) */ 1375 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1376 1377 /* Set bits of CONFIG register but with static context switching */ 1378 /* FIXME: Check whether to set ACR bit depending on clock ratios */ 1379 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1380 1381 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1382 1383 /* Set bits of CONFIG register with given context switching mode */ 1384 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 1385 1386 /* Initializes channel's priorities */ 1387 sdma_set_channel_priority(&sdma->channel[0], 7); 1388 1389 clk_disable(sdma->clk_ipg); 1390 clk_disable(sdma->clk_ahb); 1391 1392 return 0; 1393 1394 err_dma_alloc: 1395 clk_disable(sdma->clk_ipg); 1396 clk_disable(sdma->clk_ahb); 1397 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1398 return ret; 1399 } 1400 1401 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1402 { 1403 struct imx_dma_data *data = fn_param; 1404 1405 if (!imx_dma_is_general_purpose(chan)) 1406 return false; 1407 1408 chan->private = data; 1409 1410 return true; 1411 } 1412 1413 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1414 struct of_dma *ofdma) 1415 { 1416 struct sdma_engine *sdma = ofdma->of_dma_data; 1417 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1418 struct imx_dma_data data; 1419 1420 if (dma_spec->args_count != 3) 1421 return NULL; 1422 1423 data.dma_request = dma_spec->args[0]; 1424 data.peripheral_type = dma_spec->args[1]; 1425 data.priority = dma_spec->args[2]; 1426 1427 return dma_request_channel(mask, sdma_filter_fn, &data); 1428 } 1429 1430 static int __init sdma_probe(struct platform_device *pdev) 1431 { 1432 const struct of_device_id *of_id = 1433 of_match_device(sdma_dt_ids, &pdev->dev); 1434 struct device_node *np = pdev->dev.of_node; 1435 const char *fw_name; 1436 int ret; 1437 int irq; 1438 struct resource *iores; 1439 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1440 int i; 1441 struct sdma_engine *sdma; 1442 s32 *saddr_arr; 1443 const struct sdma_driver_data *drvdata = NULL; 1444 1445 if (of_id) 1446 drvdata = of_id->data; 1447 else if (pdev->id_entry) 1448 drvdata = (void *)pdev->id_entry->driver_data; 1449 1450 if (!drvdata) { 1451 dev_err(&pdev->dev, "unable to find driver data\n"); 1452 return -EINVAL; 1453 } 1454 1455 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1456 if (ret) 1457 return ret; 1458 1459 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); 1460 if (!sdma) 1461 return -ENOMEM; 1462 1463 spin_lock_init(&sdma->channel_0_lock); 1464 1465 sdma->dev = &pdev->dev; 1466 sdma->drvdata = drvdata; 1467 1468 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1469 irq = platform_get_irq(pdev, 0); 1470 if (!iores || irq < 0) { 1471 ret = -EINVAL; 1472 goto err_irq; 1473 } 1474 1475 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { 1476 ret = -EBUSY; 1477 goto err_request_region; 1478 } 1479 1480 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1481 if (IS_ERR(sdma->clk_ipg)) { 1482 ret = PTR_ERR(sdma->clk_ipg); 1483 goto err_clk; 1484 } 1485 1486 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1487 if (IS_ERR(sdma->clk_ahb)) { 1488 ret = PTR_ERR(sdma->clk_ahb); 1489 goto err_clk; 1490 } 1491 1492 clk_prepare(sdma->clk_ipg); 1493 clk_prepare(sdma->clk_ahb); 1494 1495 sdma->regs = ioremap(iores->start, resource_size(iores)); 1496 if (!sdma->regs) { 1497 ret = -ENOMEM; 1498 goto err_ioremap; 1499 } 1500 1501 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); 1502 if (ret) 1503 goto err_request_irq; 1504 1505 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 1506 if (!sdma->script_addrs) { 1507 ret = -ENOMEM; 1508 goto err_alloc; 1509 } 1510 1511 /* initially no scripts available */ 1512 saddr_arr = (s32 *)sdma->script_addrs; 1513 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 1514 saddr_arr[i] = -EINVAL; 1515 1516 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1517 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1518 1519 INIT_LIST_HEAD(&sdma->dma_device.channels); 1520 /* Initialize channel parameters */ 1521 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1522 struct sdma_channel *sdmac = &sdma->channel[i]; 1523 1524 sdmac->sdma = sdma; 1525 spin_lock_init(&sdmac->lock); 1526 1527 sdmac->chan.device = &sdma->dma_device; 1528 dma_cookie_init(&sdmac->chan); 1529 sdmac->channel = i; 1530 1531 tasklet_init(&sdmac->tasklet, sdma_tasklet, 1532 (unsigned long) sdmac); 1533 /* 1534 * Add the channel to the DMAC list. Do not add channel 0 though 1535 * because we need it internally in the SDMA driver. This also means 1536 * that channel 0 in dmaengine counting matches sdma channel 1. 1537 */ 1538 if (i) 1539 list_add_tail(&sdmac->chan.device_node, 1540 &sdma->dma_device.channels); 1541 } 1542 1543 ret = sdma_init(sdma); 1544 if (ret) 1545 goto err_init; 1546 1547 if (sdma->drvdata->script_addrs) 1548 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 1549 if (pdata && pdata->script_addrs) 1550 sdma_add_scripts(sdma, pdata->script_addrs); 1551 1552 if (pdata) { 1553 ret = sdma_get_firmware(sdma, pdata->fw_name); 1554 if (ret) 1555 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 1556 } else { 1557 /* 1558 * Because that device tree does not encode ROM script address, 1559 * the RAM script in firmware is mandatory for device tree 1560 * probe, otherwise it fails. 1561 */ 1562 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 1563 &fw_name); 1564 if (ret) 1565 dev_warn(&pdev->dev, "failed to get firmware name\n"); 1566 else { 1567 ret = sdma_get_firmware(sdma, fw_name); 1568 if (ret) 1569 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 1570 } 1571 } 1572 1573 sdma->dma_device.dev = &pdev->dev; 1574 1575 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 1576 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 1577 sdma->dma_device.device_tx_status = sdma_tx_status; 1578 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 1579 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1580 sdma->dma_device.device_control = sdma_control; 1581 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1582 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1583 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1584 1585 ret = dma_async_device_register(&sdma->dma_device); 1586 if (ret) { 1587 dev_err(&pdev->dev, "unable to register\n"); 1588 goto err_init; 1589 } 1590 1591 if (np) { 1592 ret = of_dma_controller_register(np, sdma_xlate, sdma); 1593 if (ret) { 1594 dev_err(&pdev->dev, "failed to register controller\n"); 1595 goto err_register; 1596 } 1597 } 1598 1599 dev_info(sdma->dev, "initialized\n"); 1600 1601 return 0; 1602 1603 err_register: 1604 dma_async_device_unregister(&sdma->dma_device); 1605 err_init: 1606 kfree(sdma->script_addrs); 1607 err_alloc: 1608 free_irq(irq, sdma); 1609 err_request_irq: 1610 iounmap(sdma->regs); 1611 err_ioremap: 1612 err_clk: 1613 release_mem_region(iores->start, resource_size(iores)); 1614 err_request_region: 1615 err_irq: 1616 kfree(sdma); 1617 return ret; 1618 } 1619 1620 static int sdma_remove(struct platform_device *pdev) 1621 { 1622 return -EBUSY; 1623 } 1624 1625 static struct platform_driver sdma_driver = { 1626 .driver = { 1627 .name = "imx-sdma", 1628 .of_match_table = sdma_dt_ids, 1629 }, 1630 .id_table = sdma_devtypes, 1631 .remove = sdma_remove, 1632 }; 1633 1634 static int __init sdma_module_init(void) 1635 { 1636 return platform_driver_probe(&sdma_driver, sdma_probe); 1637 } 1638 module_init(sdma_module_init); 1639 1640 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1641 MODULE_DESCRIPTION("i.MX SDMA driver"); 1642 MODULE_LICENSE("GPL"); 1643