1 /* 2 * drivers/dma/imx-dma.c 3 * 4 * This file contains a driver for the Freescale i.MX DMA engine 5 * found on i.MX1/21/27 6 * 7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> 9 * 10 * The code contained herein is licensed under the GNU General Public 11 * License. You may obtain a copy of the GNU General Public License 12 * Version 2 or later at the following locations: 13 * 14 * http://www.opensource.org/licenses/gpl-license.html 15 * http://www.gnu.org/copyleft/gpl.html 16 */ 17 #include <linux/err.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/mm.h> 21 #include <linux/interrupt.h> 22 #include <linux/spinlock.h> 23 #include <linux/device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/slab.h> 26 #include <linux/platform_device.h> 27 #include <linux/clk.h> 28 #include <linux/dmaengine.h> 29 #include <linux/module.h> 30 #include <linux/of_device.h> 31 #include <linux/of_dma.h> 32 33 #include <asm/irq.h> 34 #include <linux/platform_data/dma-imx.h> 35 36 #include "dmaengine.h" 37 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 38 #define IMX_DMA_CHANNELS 16 39 40 #define IMX_DMA_2D_SLOTS 2 41 #define IMX_DMA_2D_SLOT_A 0 42 #define IMX_DMA_2D_SLOT_B 1 43 44 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) 45 #define IMX_DMA_MEMSIZE_32 (0 << 4) 46 #define IMX_DMA_MEMSIZE_8 (1 << 4) 47 #define IMX_DMA_MEMSIZE_16 (2 << 4) 48 #define IMX_DMA_TYPE_LINEAR (0 << 10) 49 #define IMX_DMA_TYPE_2D (1 << 10) 50 #define IMX_DMA_TYPE_FIFO (2 << 10) 51 52 #define IMX_DMA_ERR_BURST (1 << 0) 53 #define IMX_DMA_ERR_REQUEST (1 << 1) 54 #define IMX_DMA_ERR_TRANSFER (1 << 2) 55 #define IMX_DMA_ERR_BUFFER (1 << 3) 56 #define IMX_DMA_ERR_TIMEOUT (1 << 4) 57 58 #define DMA_DCR 0x00 /* Control Register */ 59 #define DMA_DISR 0x04 /* Interrupt status Register */ 60 #define DMA_DIMR 0x08 /* Interrupt mask Register */ 61 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ 62 #define DMA_DRTOSR 0x10 /* Request timeout Register */ 63 #define DMA_DSESR 0x14 /* Transfer Error Status Register */ 64 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ 65 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ 66 #define DMA_WSRA 0x40 /* W-Size Register A */ 67 #define DMA_XSRA 0x44 /* X-Size Register A */ 68 #define DMA_YSRA 0x48 /* Y-Size Register A */ 69 #define DMA_WSRB 0x4c /* W-Size Register B */ 70 #define DMA_XSRB 0x50 /* X-Size Register B */ 71 #define DMA_YSRB 0x54 /* Y-Size Register B */ 72 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ 73 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ 74 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ 75 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ 76 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ 77 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ 78 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ 79 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ 80 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ 81 82 #define DCR_DRST (1<<1) 83 #define DCR_DEN (1<<0) 84 #define DBTOCR_EN (1<<15) 85 #define DBTOCR_CNT(x) ((x) & 0x7fff) 86 #define CNTR_CNT(x) ((x) & 0xffffff) 87 #define CCR_ACRPT (1<<14) 88 #define CCR_DMOD_LINEAR (0x0 << 12) 89 #define CCR_DMOD_2D (0x1 << 12) 90 #define CCR_DMOD_FIFO (0x2 << 12) 91 #define CCR_DMOD_EOBFIFO (0x3 << 12) 92 #define CCR_SMOD_LINEAR (0x0 << 10) 93 #define CCR_SMOD_2D (0x1 << 10) 94 #define CCR_SMOD_FIFO (0x2 << 10) 95 #define CCR_SMOD_EOBFIFO (0x3 << 10) 96 #define CCR_MDIR_DEC (1<<9) 97 #define CCR_MSEL_B (1<<8) 98 #define CCR_DSIZ_32 (0x0 << 6) 99 #define CCR_DSIZ_8 (0x1 << 6) 100 #define CCR_DSIZ_16 (0x2 << 6) 101 #define CCR_SSIZ_32 (0x0 << 4) 102 #define CCR_SSIZ_8 (0x1 << 4) 103 #define CCR_SSIZ_16 (0x2 << 4) 104 #define CCR_REN (1<<3) 105 #define CCR_RPT (1<<2) 106 #define CCR_FRC (1<<1) 107 #define CCR_CEN (1<<0) 108 #define RTOR_EN (1<<15) 109 #define RTOR_CLK (1<<14) 110 #define RTOR_PSC (1<<13) 111 112 enum imxdma_prep_type { 113 IMXDMA_DESC_MEMCPY, 114 IMXDMA_DESC_INTERLEAVED, 115 IMXDMA_DESC_SLAVE_SG, 116 IMXDMA_DESC_CYCLIC, 117 }; 118 119 struct imx_dma_2d_config { 120 u16 xsr; 121 u16 ysr; 122 u16 wsr; 123 int count; 124 }; 125 126 struct imxdma_desc { 127 struct list_head node; 128 struct dma_async_tx_descriptor desc; 129 enum dma_status status; 130 dma_addr_t src; 131 dma_addr_t dest; 132 size_t len; 133 enum dma_transfer_direction direction; 134 enum imxdma_prep_type type; 135 /* For memcpy and interleaved */ 136 unsigned int config_port; 137 unsigned int config_mem; 138 /* For interleaved transfers */ 139 unsigned int x; 140 unsigned int y; 141 unsigned int w; 142 /* For slave sg and cyclic */ 143 struct scatterlist *sg; 144 unsigned int sgcount; 145 }; 146 147 struct imxdma_channel { 148 int hw_chaining; 149 struct timer_list watchdog; 150 struct imxdma_engine *imxdma; 151 unsigned int channel; 152 153 struct tasklet_struct dma_tasklet; 154 struct list_head ld_free; 155 struct list_head ld_queue; 156 struct list_head ld_active; 157 int descs_allocated; 158 enum dma_slave_buswidth word_size; 159 dma_addr_t per_address; 160 u32 watermark_level; 161 struct dma_chan chan; 162 struct dma_async_tx_descriptor desc; 163 enum dma_status status; 164 int dma_request; 165 struct scatterlist *sg_list; 166 u32 ccr_from_device; 167 u32 ccr_to_device; 168 bool enabled_2d; 169 int slot_2d; 170 }; 171 172 enum imx_dma_type { 173 IMX1_DMA, 174 IMX21_DMA, 175 IMX27_DMA, 176 }; 177 178 struct imxdma_engine { 179 struct device *dev; 180 struct device_dma_parameters dma_parms; 181 struct dma_device dma_device; 182 void __iomem *base; 183 struct clk *dma_ahb; 184 struct clk *dma_ipg; 185 spinlock_t lock; 186 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; 187 struct imxdma_channel channel[IMX_DMA_CHANNELS]; 188 enum imx_dma_type devtype; 189 }; 190 191 struct imxdma_filter_data { 192 struct imxdma_engine *imxdma; 193 int request; 194 }; 195 196 static struct platform_device_id imx_dma_devtype[] = { 197 { 198 .name = "imx1-dma", 199 .driver_data = IMX1_DMA, 200 }, { 201 .name = "imx21-dma", 202 .driver_data = IMX21_DMA, 203 }, { 204 .name = "imx27-dma", 205 .driver_data = IMX27_DMA, 206 }, { 207 /* sentinel */ 208 } 209 }; 210 MODULE_DEVICE_TABLE(platform, imx_dma_devtype); 211 212 static const struct of_device_id imx_dma_of_dev_id[] = { 213 { 214 .compatible = "fsl,imx1-dma", 215 .data = &imx_dma_devtype[IMX1_DMA], 216 }, { 217 .compatible = "fsl,imx21-dma", 218 .data = &imx_dma_devtype[IMX21_DMA], 219 }, { 220 .compatible = "fsl,imx27-dma", 221 .data = &imx_dma_devtype[IMX27_DMA], 222 }, { 223 /* sentinel */ 224 } 225 }; 226 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); 227 228 static inline int is_imx1_dma(struct imxdma_engine *imxdma) 229 { 230 return imxdma->devtype == IMX1_DMA; 231 } 232 233 static inline int is_imx21_dma(struct imxdma_engine *imxdma) 234 { 235 return imxdma->devtype == IMX21_DMA; 236 } 237 238 static inline int is_imx27_dma(struct imxdma_engine *imxdma) 239 { 240 return imxdma->devtype == IMX27_DMA; 241 } 242 243 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) 244 { 245 return container_of(chan, struct imxdma_channel, chan); 246 } 247 248 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) 249 { 250 struct imxdma_desc *desc; 251 252 if (!list_empty(&imxdmac->ld_active)) { 253 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, 254 node); 255 if (desc->type == IMXDMA_DESC_CYCLIC) 256 return true; 257 } 258 return false; 259 } 260 261 262 263 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, 264 unsigned offset) 265 { 266 __raw_writel(val, imxdma->base + offset); 267 } 268 269 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) 270 { 271 return __raw_readl(imxdma->base + offset); 272 } 273 274 static int imxdma_hw_chain(struct imxdma_channel *imxdmac) 275 { 276 struct imxdma_engine *imxdma = imxdmac->imxdma; 277 278 if (is_imx27_dma(imxdma)) 279 return imxdmac->hw_chaining; 280 else 281 return 0; 282 } 283 284 /* 285 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation 286 */ 287 static inline int imxdma_sg_next(struct imxdma_desc *d) 288 { 289 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 290 struct imxdma_engine *imxdma = imxdmac->imxdma; 291 struct scatterlist *sg = d->sg; 292 unsigned long now; 293 294 now = min(d->len, sg_dma_len(sg)); 295 if (d->len != IMX_DMA_LENGTH_LOOP) 296 d->len -= now; 297 298 if (d->direction == DMA_DEV_TO_MEM) 299 imx_dmav1_writel(imxdma, sg->dma_address, 300 DMA_DAR(imxdmac->channel)); 301 else 302 imx_dmav1_writel(imxdma, sg->dma_address, 303 DMA_SAR(imxdmac->channel)); 304 305 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); 306 307 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " 308 "size 0x%08x\n", __func__, imxdmac->channel, 309 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), 310 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), 311 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); 312 313 return now; 314 } 315 316 static void imxdma_enable_hw(struct imxdma_desc *d) 317 { 318 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 319 struct imxdma_engine *imxdma = imxdmac->imxdma; 320 int channel = imxdmac->channel; 321 unsigned long flags; 322 323 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); 324 325 local_irq_save(flags); 326 327 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); 328 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & 329 ~(1 << channel), DMA_DIMR); 330 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | 331 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); 332 333 if (!is_imx1_dma(imxdma) && 334 d->sg && imxdma_hw_chain(imxdmac)) { 335 d->sg = sg_next(d->sg); 336 if (d->sg) { 337 u32 tmp; 338 imxdma_sg_next(d); 339 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); 340 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, 341 DMA_CCR(channel)); 342 } 343 } 344 345 local_irq_restore(flags); 346 } 347 348 static void imxdma_disable_hw(struct imxdma_channel *imxdmac) 349 { 350 struct imxdma_engine *imxdma = imxdmac->imxdma; 351 int channel = imxdmac->channel; 352 unsigned long flags; 353 354 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); 355 356 if (imxdma_hw_chain(imxdmac)) 357 del_timer(&imxdmac->watchdog); 358 359 local_irq_save(flags); 360 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | 361 (1 << channel), DMA_DIMR); 362 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & 363 ~CCR_CEN, DMA_CCR(channel)); 364 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); 365 local_irq_restore(flags); 366 } 367 368 static void imxdma_watchdog(unsigned long data) 369 { 370 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; 371 struct imxdma_engine *imxdma = imxdmac->imxdma; 372 int channel = imxdmac->channel; 373 374 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); 375 376 /* Tasklet watchdog error handler */ 377 tasklet_schedule(&imxdmac->dma_tasklet); 378 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", 379 imxdmac->channel); 380 } 381 382 static irqreturn_t imxdma_err_handler(int irq, void *dev_id) 383 { 384 struct imxdma_engine *imxdma = dev_id; 385 unsigned int err_mask; 386 int i, disr; 387 int errcode; 388 389 disr = imx_dmav1_readl(imxdma, DMA_DISR); 390 391 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | 392 imx_dmav1_readl(imxdma, DMA_DRTOSR) | 393 imx_dmav1_readl(imxdma, DMA_DSESR) | 394 imx_dmav1_readl(imxdma, DMA_DBOSR); 395 396 if (!err_mask) 397 return IRQ_HANDLED; 398 399 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); 400 401 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 402 if (!(err_mask & (1 << i))) 403 continue; 404 errcode = 0; 405 406 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { 407 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); 408 errcode |= IMX_DMA_ERR_BURST; 409 } 410 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { 411 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); 412 errcode |= IMX_DMA_ERR_REQUEST; 413 } 414 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { 415 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); 416 errcode |= IMX_DMA_ERR_TRANSFER; 417 } 418 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { 419 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); 420 errcode |= IMX_DMA_ERR_BUFFER; 421 } 422 /* Tasklet error handler */ 423 tasklet_schedule(&imxdma->channel[i].dma_tasklet); 424 425 printk(KERN_WARNING 426 "DMA timeout on channel %d -%s%s%s%s\n", i, 427 errcode & IMX_DMA_ERR_BURST ? " burst" : "", 428 errcode & IMX_DMA_ERR_REQUEST ? " request" : "", 429 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", 430 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); 431 } 432 return IRQ_HANDLED; 433 } 434 435 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) 436 { 437 struct imxdma_engine *imxdma = imxdmac->imxdma; 438 int chno = imxdmac->channel; 439 struct imxdma_desc *desc; 440 unsigned long flags; 441 442 spin_lock_irqsave(&imxdma->lock, flags); 443 if (list_empty(&imxdmac->ld_active)) { 444 spin_unlock_irqrestore(&imxdma->lock, flags); 445 goto out; 446 } 447 448 desc = list_first_entry(&imxdmac->ld_active, 449 struct imxdma_desc, 450 node); 451 spin_unlock_irqrestore(&imxdma->lock, flags); 452 453 if (desc->sg) { 454 u32 tmp; 455 desc->sg = sg_next(desc->sg); 456 457 if (desc->sg) { 458 imxdma_sg_next(desc); 459 460 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); 461 462 if (imxdma_hw_chain(imxdmac)) { 463 /* FIXME: The timeout should probably be 464 * configurable 465 */ 466 mod_timer(&imxdmac->watchdog, 467 jiffies + msecs_to_jiffies(500)); 468 469 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; 470 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); 471 } else { 472 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, 473 DMA_CCR(chno)); 474 tmp |= CCR_CEN; 475 } 476 477 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); 478 479 if (imxdma_chan_is_doing_cyclic(imxdmac)) 480 /* Tasklet progression */ 481 tasklet_schedule(&imxdmac->dma_tasklet); 482 483 return; 484 } 485 486 if (imxdma_hw_chain(imxdmac)) { 487 del_timer(&imxdmac->watchdog); 488 return; 489 } 490 } 491 492 out: 493 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); 494 /* Tasklet irq */ 495 tasklet_schedule(&imxdmac->dma_tasklet); 496 } 497 498 static irqreturn_t dma_irq_handler(int irq, void *dev_id) 499 { 500 struct imxdma_engine *imxdma = dev_id; 501 int i, disr; 502 503 if (!is_imx1_dma(imxdma)) 504 imxdma_err_handler(irq, dev_id); 505 506 disr = imx_dmav1_readl(imxdma, DMA_DISR); 507 508 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); 509 510 imx_dmav1_writel(imxdma, disr, DMA_DISR); 511 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 512 if (disr & (1 << i)) 513 dma_irq_handle_channel(&imxdma->channel[i]); 514 } 515 516 return IRQ_HANDLED; 517 } 518 519 static int imxdma_xfer_desc(struct imxdma_desc *d) 520 { 521 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 522 struct imxdma_engine *imxdma = imxdmac->imxdma; 523 int slot = -1; 524 int i; 525 526 /* Configure and enable */ 527 switch (d->type) { 528 case IMXDMA_DESC_INTERLEAVED: 529 /* Try to get a free 2D slot */ 530 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { 531 if ((imxdma->slots_2d[i].count > 0) && 532 ((imxdma->slots_2d[i].xsr != d->x) || 533 (imxdma->slots_2d[i].ysr != d->y) || 534 (imxdma->slots_2d[i].wsr != d->w))) 535 continue; 536 slot = i; 537 break; 538 } 539 if (slot < 0) 540 return -EBUSY; 541 542 imxdma->slots_2d[slot].xsr = d->x; 543 imxdma->slots_2d[slot].ysr = d->y; 544 imxdma->slots_2d[slot].wsr = d->w; 545 imxdma->slots_2d[slot].count++; 546 547 imxdmac->slot_2d = slot; 548 imxdmac->enabled_2d = true; 549 550 if (slot == IMX_DMA_2D_SLOT_A) { 551 d->config_mem &= ~CCR_MSEL_B; 552 d->config_port &= ~CCR_MSEL_B; 553 imx_dmav1_writel(imxdma, d->x, DMA_XSRA); 554 imx_dmav1_writel(imxdma, d->y, DMA_YSRA); 555 imx_dmav1_writel(imxdma, d->w, DMA_WSRA); 556 } else { 557 d->config_mem |= CCR_MSEL_B; 558 d->config_port |= CCR_MSEL_B; 559 imx_dmav1_writel(imxdma, d->x, DMA_XSRB); 560 imx_dmav1_writel(imxdma, d->y, DMA_YSRB); 561 imx_dmav1_writel(imxdma, d->w, DMA_WSRB); 562 } 563 /* 564 * We fall-through here intentionally, since a 2D transfer is 565 * similar to MEMCPY just adding the 2D slot configuration. 566 */ 567 case IMXDMA_DESC_MEMCPY: 568 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); 569 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); 570 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), 571 DMA_CCR(imxdmac->channel)); 572 573 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); 574 575 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " 576 "dma_length=%d\n", __func__, imxdmac->channel, 577 d->dest, d->src, d->len); 578 579 break; 580 /* Cyclic transfer is the same as slave_sg with special sg configuration. */ 581 case IMXDMA_DESC_CYCLIC: 582 case IMXDMA_DESC_SLAVE_SG: 583 if (d->direction == DMA_DEV_TO_MEM) { 584 imx_dmav1_writel(imxdma, imxdmac->per_address, 585 DMA_SAR(imxdmac->channel)); 586 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, 587 DMA_CCR(imxdmac->channel)); 588 589 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " 590 "total length=%d dev_addr=0x%08x (dev2mem)\n", 591 __func__, imxdmac->channel, d->sg, d->sgcount, 592 d->len, imxdmac->per_address); 593 } else if (d->direction == DMA_MEM_TO_DEV) { 594 imx_dmav1_writel(imxdma, imxdmac->per_address, 595 DMA_DAR(imxdmac->channel)); 596 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, 597 DMA_CCR(imxdmac->channel)); 598 599 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " 600 "total length=%d dev_addr=0x%08x (mem2dev)\n", 601 __func__, imxdmac->channel, d->sg, d->sgcount, 602 d->len, imxdmac->per_address); 603 } else { 604 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", 605 __func__, imxdmac->channel); 606 return -EINVAL; 607 } 608 609 imxdma_sg_next(d); 610 611 break; 612 default: 613 return -EINVAL; 614 } 615 imxdma_enable_hw(d); 616 return 0; 617 } 618 619 static void imxdma_tasklet(unsigned long data) 620 { 621 struct imxdma_channel *imxdmac = (void *)data; 622 struct imxdma_engine *imxdma = imxdmac->imxdma; 623 struct imxdma_desc *desc; 624 unsigned long flags; 625 626 spin_lock_irqsave(&imxdma->lock, flags); 627 628 if (list_empty(&imxdmac->ld_active)) { 629 /* Someone might have called terminate all */ 630 spin_unlock_irqrestore(&imxdma->lock, flags); 631 return; 632 } 633 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); 634 635 /* If we are dealing with a cyclic descriptor, keep it on ld_active 636 * and dont mark the descriptor as complete. 637 * Only in non-cyclic cases it would be marked as complete 638 */ 639 if (imxdma_chan_is_doing_cyclic(imxdmac)) 640 goto out; 641 else 642 dma_cookie_complete(&desc->desc); 643 644 /* Free 2D slot if it was an interleaved transfer */ 645 if (imxdmac->enabled_2d) { 646 imxdma->slots_2d[imxdmac->slot_2d].count--; 647 imxdmac->enabled_2d = false; 648 } 649 650 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); 651 652 if (!list_empty(&imxdmac->ld_queue)) { 653 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, 654 node); 655 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); 656 if (imxdma_xfer_desc(desc) < 0) 657 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", 658 __func__, imxdmac->channel); 659 } 660 out: 661 spin_unlock_irqrestore(&imxdma->lock, flags); 662 663 if (desc->desc.callback) 664 desc->desc.callback(desc->desc.callback_param); 665 666 } 667 668 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 669 unsigned long arg) 670 { 671 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 672 struct dma_slave_config *dmaengine_cfg = (void *)arg; 673 struct imxdma_engine *imxdma = imxdmac->imxdma; 674 unsigned long flags; 675 unsigned int mode = 0; 676 677 switch (cmd) { 678 case DMA_TERMINATE_ALL: 679 imxdma_disable_hw(imxdmac); 680 681 spin_lock_irqsave(&imxdma->lock, flags); 682 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); 683 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); 684 spin_unlock_irqrestore(&imxdma->lock, flags); 685 return 0; 686 case DMA_SLAVE_CONFIG: 687 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 688 imxdmac->per_address = dmaengine_cfg->src_addr; 689 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 690 imxdmac->word_size = dmaengine_cfg->src_addr_width; 691 } else { 692 imxdmac->per_address = dmaengine_cfg->dst_addr; 693 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; 694 imxdmac->word_size = dmaengine_cfg->dst_addr_width; 695 } 696 697 switch (imxdmac->word_size) { 698 case DMA_SLAVE_BUSWIDTH_1_BYTE: 699 mode = IMX_DMA_MEMSIZE_8; 700 break; 701 case DMA_SLAVE_BUSWIDTH_2_BYTES: 702 mode = IMX_DMA_MEMSIZE_16; 703 break; 704 default: 705 case DMA_SLAVE_BUSWIDTH_4_BYTES: 706 mode = IMX_DMA_MEMSIZE_32; 707 break; 708 } 709 710 imxdmac->hw_chaining = 0; 711 712 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | 713 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | 714 CCR_REN; 715 imxdmac->ccr_to_device = 716 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | 717 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; 718 imx_dmav1_writel(imxdma, imxdmac->dma_request, 719 DMA_RSSR(imxdmac->channel)); 720 721 /* Set burst length */ 722 imx_dmav1_writel(imxdma, imxdmac->watermark_level * 723 imxdmac->word_size, DMA_BLR(imxdmac->channel)); 724 725 return 0; 726 default: 727 return -ENOSYS; 728 } 729 730 return -EINVAL; 731 } 732 733 static enum dma_status imxdma_tx_status(struct dma_chan *chan, 734 dma_cookie_t cookie, 735 struct dma_tx_state *txstate) 736 { 737 return dma_cookie_status(chan, cookie, txstate); 738 } 739 740 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) 741 { 742 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); 743 struct imxdma_engine *imxdma = imxdmac->imxdma; 744 dma_cookie_t cookie; 745 unsigned long flags; 746 747 spin_lock_irqsave(&imxdma->lock, flags); 748 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); 749 cookie = dma_cookie_assign(tx); 750 spin_unlock_irqrestore(&imxdma->lock, flags); 751 752 return cookie; 753 } 754 755 static int imxdma_alloc_chan_resources(struct dma_chan *chan) 756 { 757 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 758 struct imx_dma_data *data = chan->private; 759 760 if (data != NULL) 761 imxdmac->dma_request = data->dma_request; 762 763 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { 764 struct imxdma_desc *desc; 765 766 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 767 if (!desc) 768 break; 769 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); 770 dma_async_tx_descriptor_init(&desc->desc, chan); 771 desc->desc.tx_submit = imxdma_tx_submit; 772 /* txd.flags will be overwritten in prep funcs */ 773 desc->desc.flags = DMA_CTRL_ACK; 774 desc->status = DMA_SUCCESS; 775 776 list_add_tail(&desc->node, &imxdmac->ld_free); 777 imxdmac->descs_allocated++; 778 } 779 780 if (!imxdmac->descs_allocated) 781 return -ENOMEM; 782 783 return imxdmac->descs_allocated; 784 } 785 786 static void imxdma_free_chan_resources(struct dma_chan *chan) 787 { 788 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 789 struct imxdma_engine *imxdma = imxdmac->imxdma; 790 struct imxdma_desc *desc, *_desc; 791 unsigned long flags; 792 793 spin_lock_irqsave(&imxdma->lock, flags); 794 795 imxdma_disable_hw(imxdmac); 796 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); 797 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); 798 799 spin_unlock_irqrestore(&imxdma->lock, flags); 800 801 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { 802 kfree(desc); 803 imxdmac->descs_allocated--; 804 } 805 INIT_LIST_HEAD(&imxdmac->ld_free); 806 807 kfree(imxdmac->sg_list); 808 imxdmac->sg_list = NULL; 809 } 810 811 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 812 struct dma_chan *chan, struct scatterlist *sgl, 813 unsigned int sg_len, enum dma_transfer_direction direction, 814 unsigned long flags, void *context) 815 { 816 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 817 struct scatterlist *sg; 818 int i, dma_length = 0; 819 struct imxdma_desc *desc; 820 821 if (list_empty(&imxdmac->ld_free) || 822 imxdma_chan_is_doing_cyclic(imxdmac)) 823 return NULL; 824 825 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 826 827 for_each_sg(sgl, sg, sg_len, i) { 828 dma_length += sg_dma_len(sg); 829 } 830 831 switch (imxdmac->word_size) { 832 case DMA_SLAVE_BUSWIDTH_4_BYTES: 833 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) 834 return NULL; 835 break; 836 case DMA_SLAVE_BUSWIDTH_2_BYTES: 837 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) 838 return NULL; 839 break; 840 case DMA_SLAVE_BUSWIDTH_1_BYTE: 841 break; 842 default: 843 return NULL; 844 } 845 846 desc->type = IMXDMA_DESC_SLAVE_SG; 847 desc->sg = sgl; 848 desc->sgcount = sg_len; 849 desc->len = dma_length; 850 desc->direction = direction; 851 if (direction == DMA_DEV_TO_MEM) { 852 desc->src = imxdmac->per_address; 853 } else { 854 desc->dest = imxdmac->per_address; 855 } 856 desc->desc.callback = NULL; 857 desc->desc.callback_param = NULL; 858 859 return &desc->desc; 860 } 861 862 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 863 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 864 size_t period_len, enum dma_transfer_direction direction, 865 unsigned long flags, void *context) 866 { 867 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 868 struct imxdma_engine *imxdma = imxdmac->imxdma; 869 struct imxdma_desc *desc; 870 int i; 871 unsigned int periods = buf_len / period_len; 872 873 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", 874 __func__, imxdmac->channel, buf_len, period_len); 875 876 if (list_empty(&imxdmac->ld_free) || 877 imxdma_chan_is_doing_cyclic(imxdmac)) 878 return NULL; 879 880 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 881 882 kfree(imxdmac->sg_list); 883 884 imxdmac->sg_list = kcalloc(periods + 1, 885 sizeof(struct scatterlist), GFP_ATOMIC); 886 if (!imxdmac->sg_list) 887 return NULL; 888 889 sg_init_table(imxdmac->sg_list, periods); 890 891 for (i = 0; i < periods; i++) { 892 imxdmac->sg_list[i].page_link = 0; 893 imxdmac->sg_list[i].offset = 0; 894 imxdmac->sg_list[i].dma_address = dma_addr; 895 sg_dma_len(&imxdmac->sg_list[i]) = period_len; 896 dma_addr += period_len; 897 } 898 899 /* close the loop */ 900 imxdmac->sg_list[periods].offset = 0; 901 sg_dma_len(&imxdmac->sg_list[periods]) = 0; 902 imxdmac->sg_list[periods].page_link = 903 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 904 905 desc->type = IMXDMA_DESC_CYCLIC; 906 desc->sg = imxdmac->sg_list; 907 desc->sgcount = periods; 908 desc->len = IMX_DMA_LENGTH_LOOP; 909 desc->direction = direction; 910 if (direction == DMA_DEV_TO_MEM) { 911 desc->src = imxdmac->per_address; 912 } else { 913 desc->dest = imxdmac->per_address; 914 } 915 desc->desc.callback = NULL; 916 desc->desc.callback_param = NULL; 917 918 return &desc->desc; 919 } 920 921 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( 922 struct dma_chan *chan, dma_addr_t dest, 923 dma_addr_t src, size_t len, unsigned long flags) 924 { 925 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 926 struct imxdma_engine *imxdma = imxdmac->imxdma; 927 struct imxdma_desc *desc; 928 929 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", 930 __func__, imxdmac->channel, src, dest, len); 931 932 if (list_empty(&imxdmac->ld_free) || 933 imxdma_chan_is_doing_cyclic(imxdmac)) 934 return NULL; 935 936 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 937 938 desc->type = IMXDMA_DESC_MEMCPY; 939 desc->src = src; 940 desc->dest = dest; 941 desc->len = len; 942 desc->direction = DMA_MEM_TO_MEM; 943 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; 944 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; 945 desc->desc.callback = NULL; 946 desc->desc.callback_param = NULL; 947 948 return &desc->desc; 949 } 950 951 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( 952 struct dma_chan *chan, struct dma_interleaved_template *xt, 953 unsigned long flags) 954 { 955 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 956 struct imxdma_engine *imxdma = imxdmac->imxdma; 957 struct imxdma_desc *desc; 958 959 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n" 960 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__, 961 imxdmac->channel, xt->src_start, xt->dst_start, 962 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", 963 xt->numf, xt->frame_size); 964 965 if (list_empty(&imxdmac->ld_free) || 966 imxdma_chan_is_doing_cyclic(imxdmac)) 967 return NULL; 968 969 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) 970 return NULL; 971 972 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 973 974 desc->type = IMXDMA_DESC_INTERLEAVED; 975 desc->src = xt->src_start; 976 desc->dest = xt->dst_start; 977 desc->x = xt->sgl[0].size; 978 desc->y = xt->numf; 979 desc->w = xt->sgl[0].icg + desc->x; 980 desc->len = desc->x * desc->y; 981 desc->direction = DMA_MEM_TO_MEM; 982 desc->config_port = IMX_DMA_MEMSIZE_32; 983 desc->config_mem = IMX_DMA_MEMSIZE_32; 984 if (xt->src_sgl) 985 desc->config_mem |= IMX_DMA_TYPE_2D; 986 if (xt->dst_sgl) 987 desc->config_port |= IMX_DMA_TYPE_2D; 988 desc->desc.callback = NULL; 989 desc->desc.callback_param = NULL; 990 991 return &desc->desc; 992 } 993 994 static void imxdma_issue_pending(struct dma_chan *chan) 995 { 996 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 997 struct imxdma_engine *imxdma = imxdmac->imxdma; 998 struct imxdma_desc *desc; 999 unsigned long flags; 1000 1001 spin_lock_irqsave(&imxdma->lock, flags); 1002 if (list_empty(&imxdmac->ld_active) && 1003 !list_empty(&imxdmac->ld_queue)) { 1004 desc = list_first_entry(&imxdmac->ld_queue, 1005 struct imxdma_desc, node); 1006 1007 if (imxdma_xfer_desc(desc) < 0) { 1008 dev_warn(imxdma->dev, 1009 "%s: channel: %d couldn't issue DMA xfer\n", 1010 __func__, imxdmac->channel); 1011 } else { 1012 list_move_tail(imxdmac->ld_queue.next, 1013 &imxdmac->ld_active); 1014 } 1015 } 1016 spin_unlock_irqrestore(&imxdma->lock, flags); 1017 } 1018 1019 static bool imxdma_filter_fn(struct dma_chan *chan, void *param) 1020 { 1021 struct imxdma_filter_data *fdata = param; 1022 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); 1023 1024 if (chan->device->dev != fdata->imxdma->dev) 1025 return false; 1026 1027 imxdma_chan->dma_request = fdata->request; 1028 chan->private = NULL; 1029 1030 return true; 1031 } 1032 1033 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, 1034 struct of_dma *ofdma) 1035 { 1036 int count = dma_spec->args_count; 1037 struct imxdma_engine *imxdma = ofdma->of_dma_data; 1038 struct imxdma_filter_data fdata = { 1039 .imxdma = imxdma, 1040 }; 1041 1042 if (count != 1) 1043 return NULL; 1044 1045 fdata.request = dma_spec->args[0]; 1046 1047 return dma_request_channel(imxdma->dma_device.cap_mask, 1048 imxdma_filter_fn, &fdata); 1049 } 1050 1051 static int __init imxdma_probe(struct platform_device *pdev) 1052 { 1053 struct imxdma_engine *imxdma; 1054 struct resource *res; 1055 const struct of_device_id *of_id; 1056 int ret, i; 1057 int irq, irq_err; 1058 1059 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); 1060 if (of_id) 1061 pdev->id_entry = of_id->data; 1062 1063 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); 1064 if (!imxdma) 1065 return -ENOMEM; 1066 1067 imxdma->dev = &pdev->dev; 1068 imxdma->devtype = pdev->id_entry->driver_data; 1069 1070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1071 imxdma->base = devm_ioremap_resource(&pdev->dev, res); 1072 if (IS_ERR(imxdma->base)) 1073 return PTR_ERR(imxdma->base); 1074 1075 irq = platform_get_irq(pdev, 0); 1076 if (irq < 0) 1077 return irq; 1078 1079 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); 1080 if (IS_ERR(imxdma->dma_ipg)) 1081 return PTR_ERR(imxdma->dma_ipg); 1082 1083 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); 1084 if (IS_ERR(imxdma->dma_ahb)) 1085 return PTR_ERR(imxdma->dma_ahb); 1086 1087 clk_prepare_enable(imxdma->dma_ipg); 1088 clk_prepare_enable(imxdma->dma_ahb); 1089 1090 /* reset DMA module */ 1091 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); 1092 1093 if (is_imx1_dma(imxdma)) { 1094 ret = devm_request_irq(&pdev->dev, irq, 1095 dma_irq_handler, 0, "DMA", imxdma); 1096 if (ret) { 1097 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); 1098 goto err; 1099 } 1100 1101 irq_err = platform_get_irq(pdev, 1); 1102 if (irq_err < 0) { 1103 ret = irq_err; 1104 goto err; 1105 } 1106 1107 ret = devm_request_irq(&pdev->dev, irq_err, 1108 imxdma_err_handler, 0, "DMA", imxdma); 1109 if (ret) { 1110 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); 1111 goto err; 1112 } 1113 } 1114 1115 /* enable DMA module */ 1116 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); 1117 1118 /* clear all interrupts */ 1119 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); 1120 1121 /* disable interrupts */ 1122 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); 1123 1124 INIT_LIST_HEAD(&imxdma->dma_device.channels); 1125 1126 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 1127 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 1128 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); 1129 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); 1130 1131 /* Initialize 2D global parameters */ 1132 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) 1133 imxdma->slots_2d[i].count = 0; 1134 1135 spin_lock_init(&imxdma->lock); 1136 1137 /* Initialize channel parameters */ 1138 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 1139 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 1140 1141 if (!is_imx1_dma(imxdma)) { 1142 ret = devm_request_irq(&pdev->dev, irq + i, 1143 dma_irq_handler, 0, "DMA", imxdma); 1144 if (ret) { 1145 dev_warn(imxdma->dev, "Can't register IRQ %d " 1146 "for DMA channel %d\n", 1147 irq + i, i); 1148 goto err; 1149 } 1150 init_timer(&imxdmac->watchdog); 1151 imxdmac->watchdog.function = &imxdma_watchdog; 1152 imxdmac->watchdog.data = (unsigned long)imxdmac; 1153 } 1154 1155 imxdmac->imxdma = imxdma; 1156 1157 INIT_LIST_HEAD(&imxdmac->ld_queue); 1158 INIT_LIST_HEAD(&imxdmac->ld_free); 1159 INIT_LIST_HEAD(&imxdmac->ld_active); 1160 1161 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, 1162 (unsigned long)imxdmac); 1163 imxdmac->chan.device = &imxdma->dma_device; 1164 dma_cookie_init(&imxdmac->chan); 1165 imxdmac->channel = i; 1166 1167 /* Add the channel to the DMAC list */ 1168 list_add_tail(&imxdmac->chan.device_node, 1169 &imxdma->dma_device.channels); 1170 } 1171 1172 imxdma->dma_device.dev = &pdev->dev; 1173 1174 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; 1175 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; 1176 imxdma->dma_device.device_tx_status = imxdma_tx_status; 1177 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; 1178 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; 1179 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; 1180 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; 1181 imxdma->dma_device.device_control = imxdma_control; 1182 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 1183 1184 platform_set_drvdata(pdev, imxdma); 1185 1186 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ 1187 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; 1188 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); 1189 1190 ret = dma_async_device_register(&imxdma->dma_device); 1191 if (ret) { 1192 dev_err(&pdev->dev, "unable to register\n"); 1193 goto err; 1194 } 1195 1196 if (pdev->dev.of_node) { 1197 ret = of_dma_controller_register(pdev->dev.of_node, 1198 imxdma_xlate, imxdma); 1199 if (ret) { 1200 dev_err(&pdev->dev, "unable to register of_dma_controller\n"); 1201 goto err_of_dma_controller; 1202 } 1203 } 1204 1205 return 0; 1206 1207 err_of_dma_controller: 1208 dma_async_device_unregister(&imxdma->dma_device); 1209 err: 1210 clk_disable_unprepare(imxdma->dma_ipg); 1211 clk_disable_unprepare(imxdma->dma_ahb); 1212 return ret; 1213 } 1214 1215 static int imxdma_remove(struct platform_device *pdev) 1216 { 1217 struct imxdma_engine *imxdma = platform_get_drvdata(pdev); 1218 1219 dma_async_device_unregister(&imxdma->dma_device); 1220 1221 if (pdev->dev.of_node) 1222 of_dma_controller_free(pdev->dev.of_node); 1223 1224 clk_disable_unprepare(imxdma->dma_ipg); 1225 clk_disable_unprepare(imxdma->dma_ahb); 1226 1227 return 0; 1228 } 1229 1230 static struct platform_driver imxdma_driver = { 1231 .driver = { 1232 .name = "imx-dma", 1233 .of_match_table = imx_dma_of_dev_id, 1234 }, 1235 .id_table = imx_dma_devtype, 1236 .remove = imxdma_remove, 1237 }; 1238 1239 static int __init imxdma_module_init(void) 1240 { 1241 return platform_driver_probe(&imxdma_driver, imxdma_probe); 1242 } 1243 subsys_initcall(imxdma_module_init); 1244 1245 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1246 MODULE_DESCRIPTION("i.MX dma driver"); 1247 MODULE_LICENSE("GPL"); 1248