1 /* 2 * drivers/dma/imx-dma.c 3 * 4 * This file contains a driver for the Freescale i.MX DMA engine 5 * found on i.MX1/21/27 6 * 7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/mm.h> 19 #include <linux/interrupt.h> 20 #include <linux/spinlock.h> 21 #include <linux/device.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/slab.h> 24 #include <linux/platform_device.h> 25 #include <linux/dmaengine.h> 26 27 #include <asm/irq.h> 28 #include <mach/dma-v1.h> 29 #include <mach/hardware.h> 30 31 struct imxdma_channel { 32 struct imxdma_engine *imxdma; 33 unsigned int channel; 34 unsigned int imxdma_channel; 35 36 enum dma_slave_buswidth word_size; 37 dma_addr_t per_address; 38 u32 watermark_level; 39 struct dma_chan chan; 40 spinlock_t lock; 41 struct dma_async_tx_descriptor desc; 42 dma_cookie_t last_completed; 43 enum dma_status status; 44 int dma_request; 45 struct scatterlist *sg_list; 46 }; 47 48 #define MAX_DMA_CHANNELS 8 49 50 struct imxdma_engine { 51 struct device *dev; 52 struct device_dma_parameters dma_parms; 53 struct dma_device dma_device; 54 struct imxdma_channel channel[MAX_DMA_CHANNELS]; 55 }; 56 57 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) 58 { 59 return container_of(chan, struct imxdma_channel, chan); 60 } 61 62 static void imxdma_handle(struct imxdma_channel *imxdmac) 63 { 64 if (imxdmac->desc.callback) 65 imxdmac->desc.callback(imxdmac->desc.callback_param); 66 imxdmac->last_completed = imxdmac->desc.cookie; 67 } 68 69 static void imxdma_irq_handler(int channel, void *data) 70 { 71 struct imxdma_channel *imxdmac = data; 72 73 imxdmac->status = DMA_SUCCESS; 74 imxdma_handle(imxdmac); 75 } 76 77 static void imxdma_err_handler(int channel, void *data, int error) 78 { 79 struct imxdma_channel *imxdmac = data; 80 81 imxdmac->status = DMA_ERROR; 82 imxdma_handle(imxdmac); 83 } 84 85 static void imxdma_progression(int channel, void *data, 86 struct scatterlist *sg) 87 { 88 struct imxdma_channel *imxdmac = data; 89 90 imxdmac->status = DMA_SUCCESS; 91 imxdma_handle(imxdmac); 92 } 93 94 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 95 unsigned long arg) 96 { 97 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 98 struct dma_slave_config *dmaengine_cfg = (void *)arg; 99 int ret; 100 unsigned int mode = 0; 101 102 switch (cmd) { 103 case DMA_TERMINATE_ALL: 104 imxdmac->status = DMA_ERROR; 105 imx_dma_disable(imxdmac->imxdma_channel); 106 return 0; 107 case DMA_SLAVE_CONFIG: 108 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { 109 imxdmac->per_address = dmaengine_cfg->src_addr; 110 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 111 imxdmac->word_size = dmaengine_cfg->src_addr_width; 112 } else { 113 imxdmac->per_address = dmaengine_cfg->dst_addr; 114 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; 115 imxdmac->word_size = dmaengine_cfg->dst_addr_width; 116 } 117 118 switch (imxdmac->word_size) { 119 case DMA_SLAVE_BUSWIDTH_1_BYTE: 120 mode = IMX_DMA_MEMSIZE_8; 121 break; 122 case DMA_SLAVE_BUSWIDTH_2_BYTES: 123 mode = IMX_DMA_MEMSIZE_16; 124 break; 125 default: 126 case DMA_SLAVE_BUSWIDTH_4_BYTES: 127 mode = IMX_DMA_MEMSIZE_32; 128 break; 129 } 130 ret = imx_dma_config_channel(imxdmac->imxdma_channel, 131 mode | IMX_DMA_TYPE_FIFO, 132 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 133 imxdmac->dma_request, 1); 134 135 if (ret) 136 return ret; 137 138 imx_dma_config_burstlen(imxdmac->imxdma_channel, 139 imxdmac->watermark_level * imxdmac->word_size); 140 141 return 0; 142 default: 143 return -ENOSYS; 144 } 145 146 return -EINVAL; 147 } 148 149 static enum dma_status imxdma_tx_status(struct dma_chan *chan, 150 dma_cookie_t cookie, 151 struct dma_tx_state *txstate) 152 { 153 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 154 dma_cookie_t last_used; 155 enum dma_status ret; 156 157 last_used = chan->cookie; 158 159 ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used); 160 dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0); 161 162 return ret; 163 } 164 165 static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma) 166 { 167 dma_cookie_t cookie = imxdma->chan.cookie; 168 169 if (++cookie < 0) 170 cookie = 1; 171 172 imxdma->chan.cookie = cookie; 173 imxdma->desc.cookie = cookie; 174 175 return cookie; 176 } 177 178 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) 179 { 180 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); 181 dma_cookie_t cookie; 182 183 spin_lock_irq(&imxdmac->lock); 184 185 cookie = imxdma_assign_cookie(imxdmac); 186 187 imx_dma_enable(imxdmac->imxdma_channel); 188 189 spin_unlock_irq(&imxdmac->lock); 190 191 return cookie; 192 } 193 194 static int imxdma_alloc_chan_resources(struct dma_chan *chan) 195 { 196 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 197 struct imx_dma_data *data = chan->private; 198 199 imxdmac->dma_request = data->dma_request; 200 201 dma_async_tx_descriptor_init(&imxdmac->desc, chan); 202 imxdmac->desc.tx_submit = imxdma_tx_submit; 203 /* txd.flags will be overwritten in prep funcs */ 204 imxdmac->desc.flags = DMA_CTRL_ACK; 205 206 imxdmac->status = DMA_SUCCESS; 207 208 return 0; 209 } 210 211 static void imxdma_free_chan_resources(struct dma_chan *chan) 212 { 213 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 214 215 imx_dma_disable(imxdmac->imxdma_channel); 216 217 if (imxdmac->sg_list) { 218 kfree(imxdmac->sg_list); 219 imxdmac->sg_list = NULL; 220 } 221 } 222 223 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 224 struct dma_chan *chan, struct scatterlist *sgl, 225 unsigned int sg_len, enum dma_data_direction direction, 226 unsigned long flags) 227 { 228 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 229 struct scatterlist *sg; 230 int i, ret, dma_length = 0; 231 unsigned int dmamode; 232 233 if (imxdmac->status == DMA_IN_PROGRESS) 234 return NULL; 235 236 imxdmac->status = DMA_IN_PROGRESS; 237 238 for_each_sg(sgl, sg, sg_len, i) { 239 dma_length += sg->length; 240 } 241 242 if (direction == DMA_FROM_DEVICE) 243 dmamode = DMA_MODE_READ; 244 else 245 dmamode = DMA_MODE_WRITE; 246 247 switch (imxdmac->word_size) { 248 case DMA_SLAVE_BUSWIDTH_4_BYTES: 249 if (sgl->length & 3 || sgl->dma_address & 3) 250 return NULL; 251 break; 252 case DMA_SLAVE_BUSWIDTH_2_BYTES: 253 if (sgl->length & 1 || sgl->dma_address & 1) 254 return NULL; 255 break; 256 case DMA_SLAVE_BUSWIDTH_1_BYTE: 257 break; 258 default: 259 return NULL; 260 } 261 262 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len, 263 dma_length, imxdmac->per_address, dmamode); 264 if (ret) 265 return NULL; 266 267 return &imxdmac->desc; 268 } 269 270 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 271 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 272 size_t period_len, enum dma_data_direction direction) 273 { 274 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 275 struct imxdma_engine *imxdma = imxdmac->imxdma; 276 int i, ret; 277 unsigned int periods = buf_len / period_len; 278 unsigned int dmamode; 279 280 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", 281 __func__, imxdmac->channel, buf_len, period_len); 282 283 if (imxdmac->status == DMA_IN_PROGRESS) 284 return NULL; 285 imxdmac->status = DMA_IN_PROGRESS; 286 287 ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel, 288 imxdma_progression); 289 if (ret) { 290 dev_err(imxdma->dev, "Failed to setup the DMA handler\n"); 291 return NULL; 292 } 293 294 if (imxdmac->sg_list) 295 kfree(imxdmac->sg_list); 296 297 imxdmac->sg_list = kcalloc(periods + 1, 298 sizeof(struct scatterlist), GFP_KERNEL); 299 if (!imxdmac->sg_list) 300 return NULL; 301 302 sg_init_table(imxdmac->sg_list, periods); 303 304 for (i = 0; i < periods; i++) { 305 imxdmac->sg_list[i].page_link = 0; 306 imxdmac->sg_list[i].offset = 0; 307 imxdmac->sg_list[i].dma_address = dma_addr; 308 imxdmac->sg_list[i].length = period_len; 309 dma_addr += period_len; 310 } 311 312 /* close the loop */ 313 imxdmac->sg_list[periods].offset = 0; 314 imxdmac->sg_list[periods].length = 0; 315 imxdmac->sg_list[periods].page_link = 316 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 317 318 if (direction == DMA_FROM_DEVICE) 319 dmamode = DMA_MODE_READ; 320 else 321 dmamode = DMA_MODE_WRITE; 322 323 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods, 324 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode); 325 if (ret) 326 return NULL; 327 328 return &imxdmac->desc; 329 } 330 331 static void imxdma_issue_pending(struct dma_chan *chan) 332 { 333 /* 334 * Nothing to do. We only have a single descriptor 335 */ 336 } 337 338 static int __init imxdma_probe(struct platform_device *pdev) 339 { 340 struct imxdma_engine *imxdma; 341 int ret, i; 342 343 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); 344 if (!imxdma) 345 return -ENOMEM; 346 347 INIT_LIST_HEAD(&imxdma->dma_device.channels); 348 349 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 350 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 351 352 /* Initialize channel parameters */ 353 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 354 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 355 356 imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine", 357 DMA_PRIO_MEDIUM); 358 if ((int)imxdmac->channel < 0) { 359 ret = -ENODEV; 360 goto err_init; 361 } 362 363 imx_dma_setup_handlers(imxdmac->imxdma_channel, 364 imxdma_irq_handler, imxdma_err_handler, imxdmac); 365 366 imxdmac->imxdma = imxdma; 367 spin_lock_init(&imxdmac->lock); 368 369 imxdmac->chan.device = &imxdma->dma_device; 370 imxdmac->channel = i; 371 372 /* Add the channel to the DMAC list */ 373 list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels); 374 } 375 376 imxdma->dev = &pdev->dev; 377 imxdma->dma_device.dev = &pdev->dev; 378 379 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; 380 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; 381 imxdma->dma_device.device_tx_status = imxdma_tx_status; 382 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; 383 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; 384 imxdma->dma_device.device_control = imxdma_control; 385 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 386 387 platform_set_drvdata(pdev, imxdma); 388 389 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; 390 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); 391 392 ret = dma_async_device_register(&imxdma->dma_device); 393 if (ret) { 394 dev_err(&pdev->dev, "unable to register\n"); 395 goto err_init; 396 } 397 398 return 0; 399 400 err_init: 401 while (--i >= 0) { 402 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 403 imx_dma_free(imxdmac->imxdma_channel); 404 } 405 406 kfree(imxdma); 407 return ret; 408 } 409 410 static int __exit imxdma_remove(struct platform_device *pdev) 411 { 412 struct imxdma_engine *imxdma = platform_get_drvdata(pdev); 413 int i; 414 415 dma_async_device_unregister(&imxdma->dma_device); 416 417 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 418 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 419 420 imx_dma_free(imxdmac->imxdma_channel); 421 } 422 423 kfree(imxdma); 424 425 return 0; 426 } 427 428 static struct platform_driver imxdma_driver = { 429 .driver = { 430 .name = "imx-dma", 431 }, 432 .remove = __exit_p(imxdma_remove), 433 }; 434 435 static int __init imxdma_module_init(void) 436 { 437 return platform_driver_probe(&imxdma_driver, imxdma_probe); 438 } 439 subsys_initcall(imxdma_module_init); 440 441 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 442 MODULE_DESCRIPTION("i.MX dma driver"); 443 MODULE_LICENSE("GPL"); 444