1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // drivers/dma/imx-dma.c 4 // 5 // This file contains a driver for the Freescale i.MX DMA engine 6 // found on i.MX1/21/27 7 // 8 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 9 // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> 10 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/interrupt.h> 16 #include <linux/spinlock.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/slab.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/dmaengine.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of_dma.h> 26 27 #include <asm/irq.h> 28 #include <linux/platform_data/dma-imx.h> 29 30 #include "dmaengine.h" 31 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 32 #define IMX_DMA_CHANNELS 16 33 34 #define IMX_DMA_2D_SLOTS 2 35 #define IMX_DMA_2D_SLOT_A 0 36 #define IMX_DMA_2D_SLOT_B 1 37 38 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) 39 #define IMX_DMA_MEMSIZE_32 (0 << 4) 40 #define IMX_DMA_MEMSIZE_8 (1 << 4) 41 #define IMX_DMA_MEMSIZE_16 (2 << 4) 42 #define IMX_DMA_TYPE_LINEAR (0 << 10) 43 #define IMX_DMA_TYPE_2D (1 << 10) 44 #define IMX_DMA_TYPE_FIFO (2 << 10) 45 46 #define IMX_DMA_ERR_BURST (1 << 0) 47 #define IMX_DMA_ERR_REQUEST (1 << 1) 48 #define IMX_DMA_ERR_TRANSFER (1 << 2) 49 #define IMX_DMA_ERR_BUFFER (1 << 3) 50 #define IMX_DMA_ERR_TIMEOUT (1 << 4) 51 52 #define DMA_DCR 0x00 /* Control Register */ 53 #define DMA_DISR 0x04 /* Interrupt status Register */ 54 #define DMA_DIMR 0x08 /* Interrupt mask Register */ 55 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ 56 #define DMA_DRTOSR 0x10 /* Request timeout Register */ 57 #define DMA_DSESR 0x14 /* Transfer Error Status Register */ 58 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ 59 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ 60 #define DMA_WSRA 0x40 /* W-Size Register A */ 61 #define DMA_XSRA 0x44 /* X-Size Register A */ 62 #define DMA_YSRA 0x48 /* Y-Size Register A */ 63 #define DMA_WSRB 0x4c /* W-Size Register B */ 64 #define DMA_XSRB 0x50 /* X-Size Register B */ 65 #define DMA_YSRB 0x54 /* Y-Size Register B */ 66 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ 67 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ 68 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ 69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ 70 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ 71 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ 72 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ 73 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ 74 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ 75 76 #define DCR_DRST (1<<1) 77 #define DCR_DEN (1<<0) 78 #define DBTOCR_EN (1<<15) 79 #define DBTOCR_CNT(x) ((x) & 0x7fff) 80 #define CNTR_CNT(x) ((x) & 0xffffff) 81 #define CCR_ACRPT (1<<14) 82 #define CCR_DMOD_LINEAR (0x0 << 12) 83 #define CCR_DMOD_2D (0x1 << 12) 84 #define CCR_DMOD_FIFO (0x2 << 12) 85 #define CCR_DMOD_EOBFIFO (0x3 << 12) 86 #define CCR_SMOD_LINEAR (0x0 << 10) 87 #define CCR_SMOD_2D (0x1 << 10) 88 #define CCR_SMOD_FIFO (0x2 << 10) 89 #define CCR_SMOD_EOBFIFO (0x3 << 10) 90 #define CCR_MDIR_DEC (1<<9) 91 #define CCR_MSEL_B (1<<8) 92 #define CCR_DSIZ_32 (0x0 << 6) 93 #define CCR_DSIZ_8 (0x1 << 6) 94 #define CCR_DSIZ_16 (0x2 << 6) 95 #define CCR_SSIZ_32 (0x0 << 4) 96 #define CCR_SSIZ_8 (0x1 << 4) 97 #define CCR_SSIZ_16 (0x2 << 4) 98 #define CCR_REN (1<<3) 99 #define CCR_RPT (1<<2) 100 #define CCR_FRC (1<<1) 101 #define CCR_CEN (1<<0) 102 #define RTOR_EN (1<<15) 103 #define RTOR_CLK (1<<14) 104 #define RTOR_PSC (1<<13) 105 106 enum imxdma_prep_type { 107 IMXDMA_DESC_MEMCPY, 108 IMXDMA_DESC_INTERLEAVED, 109 IMXDMA_DESC_SLAVE_SG, 110 IMXDMA_DESC_CYCLIC, 111 }; 112 113 struct imx_dma_2d_config { 114 u16 xsr; 115 u16 ysr; 116 u16 wsr; 117 int count; 118 }; 119 120 struct imxdma_desc { 121 struct list_head node; 122 struct dma_async_tx_descriptor desc; 123 enum dma_status status; 124 dma_addr_t src; 125 dma_addr_t dest; 126 size_t len; 127 enum dma_transfer_direction direction; 128 enum imxdma_prep_type type; 129 /* For memcpy and interleaved */ 130 unsigned int config_port; 131 unsigned int config_mem; 132 /* For interleaved transfers */ 133 unsigned int x; 134 unsigned int y; 135 unsigned int w; 136 /* For slave sg and cyclic */ 137 struct scatterlist *sg; 138 unsigned int sgcount; 139 }; 140 141 struct imxdma_channel { 142 int hw_chaining; 143 struct timer_list watchdog; 144 struct imxdma_engine *imxdma; 145 unsigned int channel; 146 147 struct tasklet_struct dma_tasklet; 148 struct list_head ld_free; 149 struct list_head ld_queue; 150 struct list_head ld_active; 151 int descs_allocated; 152 enum dma_slave_buswidth word_size; 153 dma_addr_t per_address; 154 u32 watermark_level; 155 struct dma_chan chan; 156 struct dma_async_tx_descriptor desc; 157 enum dma_status status; 158 int dma_request; 159 struct scatterlist *sg_list; 160 u32 ccr_from_device; 161 u32 ccr_to_device; 162 bool enabled_2d; 163 int slot_2d; 164 unsigned int irq; 165 }; 166 167 enum imx_dma_type { 168 IMX1_DMA, 169 IMX21_DMA, 170 IMX27_DMA, 171 }; 172 173 struct imxdma_engine { 174 struct device *dev; 175 struct device_dma_parameters dma_parms; 176 struct dma_device dma_device; 177 void __iomem *base; 178 struct clk *dma_ahb; 179 struct clk *dma_ipg; 180 spinlock_t lock; 181 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; 182 struct imxdma_channel channel[IMX_DMA_CHANNELS]; 183 enum imx_dma_type devtype; 184 unsigned int irq; 185 unsigned int irq_err; 186 187 }; 188 189 struct imxdma_filter_data { 190 struct imxdma_engine *imxdma; 191 int request; 192 }; 193 194 static const struct platform_device_id imx_dma_devtype[] = { 195 { 196 .name = "imx1-dma", 197 .driver_data = IMX1_DMA, 198 }, { 199 .name = "imx21-dma", 200 .driver_data = IMX21_DMA, 201 }, { 202 .name = "imx27-dma", 203 .driver_data = IMX27_DMA, 204 }, { 205 /* sentinel */ 206 } 207 }; 208 MODULE_DEVICE_TABLE(platform, imx_dma_devtype); 209 210 static const struct of_device_id imx_dma_of_dev_id[] = { 211 { 212 .compatible = "fsl,imx1-dma", 213 .data = &imx_dma_devtype[IMX1_DMA], 214 }, { 215 .compatible = "fsl,imx21-dma", 216 .data = &imx_dma_devtype[IMX21_DMA], 217 }, { 218 .compatible = "fsl,imx27-dma", 219 .data = &imx_dma_devtype[IMX27_DMA], 220 }, { 221 /* sentinel */ 222 } 223 }; 224 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); 225 226 static inline int is_imx1_dma(struct imxdma_engine *imxdma) 227 { 228 return imxdma->devtype == IMX1_DMA; 229 } 230 231 static inline int is_imx27_dma(struct imxdma_engine *imxdma) 232 { 233 return imxdma->devtype == IMX27_DMA; 234 } 235 236 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) 237 { 238 return container_of(chan, struct imxdma_channel, chan); 239 } 240 241 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) 242 { 243 struct imxdma_desc *desc; 244 245 if (!list_empty(&imxdmac->ld_active)) { 246 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, 247 node); 248 if (desc->type == IMXDMA_DESC_CYCLIC) 249 return true; 250 } 251 return false; 252 } 253 254 255 256 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, 257 unsigned offset) 258 { 259 __raw_writel(val, imxdma->base + offset); 260 } 261 262 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) 263 { 264 return __raw_readl(imxdma->base + offset); 265 } 266 267 static int imxdma_hw_chain(struct imxdma_channel *imxdmac) 268 { 269 struct imxdma_engine *imxdma = imxdmac->imxdma; 270 271 if (is_imx27_dma(imxdma)) 272 return imxdmac->hw_chaining; 273 else 274 return 0; 275 } 276 277 /* 278 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation 279 */ 280 static inline int imxdma_sg_next(struct imxdma_desc *d) 281 { 282 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 283 struct imxdma_engine *imxdma = imxdmac->imxdma; 284 struct scatterlist *sg = d->sg; 285 unsigned long now; 286 287 now = min(d->len, sg_dma_len(sg)); 288 if (d->len != IMX_DMA_LENGTH_LOOP) 289 d->len -= now; 290 291 if (d->direction == DMA_DEV_TO_MEM) 292 imx_dmav1_writel(imxdma, sg->dma_address, 293 DMA_DAR(imxdmac->channel)); 294 else 295 imx_dmav1_writel(imxdma, sg->dma_address, 296 DMA_SAR(imxdmac->channel)); 297 298 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); 299 300 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " 301 "size 0x%08x\n", __func__, imxdmac->channel, 302 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), 303 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), 304 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); 305 306 return now; 307 } 308 309 static void imxdma_enable_hw(struct imxdma_desc *d) 310 { 311 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 312 struct imxdma_engine *imxdma = imxdmac->imxdma; 313 int channel = imxdmac->channel; 314 unsigned long flags; 315 316 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); 317 318 local_irq_save(flags); 319 320 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); 321 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & 322 ~(1 << channel), DMA_DIMR); 323 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | 324 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); 325 326 if (!is_imx1_dma(imxdma) && 327 d->sg && imxdma_hw_chain(imxdmac)) { 328 d->sg = sg_next(d->sg); 329 if (d->sg) { 330 u32 tmp; 331 imxdma_sg_next(d); 332 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); 333 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, 334 DMA_CCR(channel)); 335 } 336 } 337 338 local_irq_restore(flags); 339 } 340 341 static void imxdma_disable_hw(struct imxdma_channel *imxdmac) 342 { 343 struct imxdma_engine *imxdma = imxdmac->imxdma; 344 int channel = imxdmac->channel; 345 unsigned long flags; 346 347 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); 348 349 if (imxdma_hw_chain(imxdmac)) 350 del_timer(&imxdmac->watchdog); 351 352 local_irq_save(flags); 353 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | 354 (1 << channel), DMA_DIMR); 355 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & 356 ~CCR_CEN, DMA_CCR(channel)); 357 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); 358 local_irq_restore(flags); 359 } 360 361 static void imxdma_watchdog(struct timer_list *t) 362 { 363 struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog); 364 struct imxdma_engine *imxdma = imxdmac->imxdma; 365 int channel = imxdmac->channel; 366 367 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); 368 369 /* Tasklet watchdog error handler */ 370 tasklet_schedule(&imxdmac->dma_tasklet); 371 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", 372 imxdmac->channel); 373 } 374 375 static irqreturn_t imxdma_err_handler(int irq, void *dev_id) 376 { 377 struct imxdma_engine *imxdma = dev_id; 378 unsigned int err_mask; 379 int i, disr; 380 int errcode; 381 382 disr = imx_dmav1_readl(imxdma, DMA_DISR); 383 384 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | 385 imx_dmav1_readl(imxdma, DMA_DRTOSR) | 386 imx_dmav1_readl(imxdma, DMA_DSESR) | 387 imx_dmav1_readl(imxdma, DMA_DBOSR); 388 389 if (!err_mask) 390 return IRQ_HANDLED; 391 392 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); 393 394 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 395 if (!(err_mask & (1 << i))) 396 continue; 397 errcode = 0; 398 399 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { 400 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); 401 errcode |= IMX_DMA_ERR_BURST; 402 } 403 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { 404 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); 405 errcode |= IMX_DMA_ERR_REQUEST; 406 } 407 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { 408 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); 409 errcode |= IMX_DMA_ERR_TRANSFER; 410 } 411 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { 412 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); 413 errcode |= IMX_DMA_ERR_BUFFER; 414 } 415 /* Tasklet error handler */ 416 tasklet_schedule(&imxdma->channel[i].dma_tasklet); 417 418 dev_warn(imxdma->dev, 419 "DMA timeout on channel %d -%s%s%s%s\n", i, 420 errcode & IMX_DMA_ERR_BURST ? " burst" : "", 421 errcode & IMX_DMA_ERR_REQUEST ? " request" : "", 422 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", 423 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); 424 } 425 return IRQ_HANDLED; 426 } 427 428 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) 429 { 430 struct imxdma_engine *imxdma = imxdmac->imxdma; 431 int chno = imxdmac->channel; 432 struct imxdma_desc *desc; 433 unsigned long flags; 434 435 spin_lock_irqsave(&imxdma->lock, flags); 436 if (list_empty(&imxdmac->ld_active)) { 437 spin_unlock_irqrestore(&imxdma->lock, flags); 438 goto out; 439 } 440 441 desc = list_first_entry(&imxdmac->ld_active, 442 struct imxdma_desc, 443 node); 444 spin_unlock_irqrestore(&imxdma->lock, flags); 445 446 if (desc->sg) { 447 u32 tmp; 448 desc->sg = sg_next(desc->sg); 449 450 if (desc->sg) { 451 imxdma_sg_next(desc); 452 453 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); 454 455 if (imxdma_hw_chain(imxdmac)) { 456 /* FIXME: The timeout should probably be 457 * configurable 458 */ 459 mod_timer(&imxdmac->watchdog, 460 jiffies + msecs_to_jiffies(500)); 461 462 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; 463 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); 464 } else { 465 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, 466 DMA_CCR(chno)); 467 tmp |= CCR_CEN; 468 } 469 470 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); 471 472 if (imxdma_chan_is_doing_cyclic(imxdmac)) 473 /* Tasklet progression */ 474 tasklet_schedule(&imxdmac->dma_tasklet); 475 476 return; 477 } 478 479 if (imxdma_hw_chain(imxdmac)) { 480 del_timer(&imxdmac->watchdog); 481 return; 482 } 483 } 484 485 out: 486 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); 487 /* Tasklet irq */ 488 tasklet_schedule(&imxdmac->dma_tasklet); 489 } 490 491 static irqreturn_t dma_irq_handler(int irq, void *dev_id) 492 { 493 struct imxdma_engine *imxdma = dev_id; 494 int i, disr; 495 496 if (!is_imx1_dma(imxdma)) 497 imxdma_err_handler(irq, dev_id); 498 499 disr = imx_dmav1_readl(imxdma, DMA_DISR); 500 501 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); 502 503 imx_dmav1_writel(imxdma, disr, DMA_DISR); 504 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 505 if (disr & (1 << i)) 506 dma_irq_handle_channel(&imxdma->channel[i]); 507 } 508 509 return IRQ_HANDLED; 510 } 511 512 static int imxdma_xfer_desc(struct imxdma_desc *d) 513 { 514 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); 515 struct imxdma_engine *imxdma = imxdmac->imxdma; 516 int slot = -1; 517 int i; 518 519 /* Configure and enable */ 520 switch (d->type) { 521 case IMXDMA_DESC_INTERLEAVED: 522 /* Try to get a free 2D slot */ 523 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { 524 if ((imxdma->slots_2d[i].count > 0) && 525 ((imxdma->slots_2d[i].xsr != d->x) || 526 (imxdma->slots_2d[i].ysr != d->y) || 527 (imxdma->slots_2d[i].wsr != d->w))) 528 continue; 529 slot = i; 530 break; 531 } 532 if (slot < 0) 533 return -EBUSY; 534 535 imxdma->slots_2d[slot].xsr = d->x; 536 imxdma->slots_2d[slot].ysr = d->y; 537 imxdma->slots_2d[slot].wsr = d->w; 538 imxdma->slots_2d[slot].count++; 539 540 imxdmac->slot_2d = slot; 541 imxdmac->enabled_2d = true; 542 543 if (slot == IMX_DMA_2D_SLOT_A) { 544 d->config_mem &= ~CCR_MSEL_B; 545 d->config_port &= ~CCR_MSEL_B; 546 imx_dmav1_writel(imxdma, d->x, DMA_XSRA); 547 imx_dmav1_writel(imxdma, d->y, DMA_YSRA); 548 imx_dmav1_writel(imxdma, d->w, DMA_WSRA); 549 } else { 550 d->config_mem |= CCR_MSEL_B; 551 d->config_port |= CCR_MSEL_B; 552 imx_dmav1_writel(imxdma, d->x, DMA_XSRB); 553 imx_dmav1_writel(imxdma, d->y, DMA_YSRB); 554 imx_dmav1_writel(imxdma, d->w, DMA_WSRB); 555 } 556 /* 557 * We fall-through here intentionally, since a 2D transfer is 558 * similar to MEMCPY just adding the 2D slot configuration. 559 */ 560 case IMXDMA_DESC_MEMCPY: 561 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); 562 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); 563 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), 564 DMA_CCR(imxdmac->channel)); 565 566 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); 567 568 dev_dbg(imxdma->dev, 569 "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n", 570 __func__, imxdmac->channel, 571 (unsigned long long)d->dest, 572 (unsigned long long)d->src, d->len); 573 574 break; 575 /* Cyclic transfer is the same as slave_sg with special sg configuration. */ 576 case IMXDMA_DESC_CYCLIC: 577 case IMXDMA_DESC_SLAVE_SG: 578 if (d->direction == DMA_DEV_TO_MEM) { 579 imx_dmav1_writel(imxdma, imxdmac->per_address, 580 DMA_SAR(imxdmac->channel)); 581 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, 582 DMA_CCR(imxdmac->channel)); 583 584 dev_dbg(imxdma->dev, 585 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n", 586 __func__, imxdmac->channel, 587 d->sg, d->sgcount, d->len, 588 (unsigned long long)imxdmac->per_address); 589 } else if (d->direction == DMA_MEM_TO_DEV) { 590 imx_dmav1_writel(imxdma, imxdmac->per_address, 591 DMA_DAR(imxdmac->channel)); 592 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, 593 DMA_CCR(imxdmac->channel)); 594 595 dev_dbg(imxdma->dev, 596 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n", 597 __func__, imxdmac->channel, 598 d->sg, d->sgcount, d->len, 599 (unsigned long long)imxdmac->per_address); 600 } else { 601 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", 602 __func__, imxdmac->channel); 603 return -EINVAL; 604 } 605 606 imxdma_sg_next(d); 607 608 break; 609 default: 610 return -EINVAL; 611 } 612 imxdma_enable_hw(d); 613 return 0; 614 } 615 616 static void imxdma_tasklet(unsigned long data) 617 { 618 struct imxdma_channel *imxdmac = (void *)data; 619 struct imxdma_engine *imxdma = imxdmac->imxdma; 620 struct imxdma_desc *desc; 621 unsigned long flags; 622 623 spin_lock_irqsave(&imxdma->lock, flags); 624 625 if (list_empty(&imxdmac->ld_active)) { 626 /* Someone might have called terminate all */ 627 spin_unlock_irqrestore(&imxdma->lock, flags); 628 return; 629 } 630 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); 631 632 /* If we are dealing with a cyclic descriptor, keep it on ld_active 633 * and dont mark the descriptor as complete. 634 * Only in non-cyclic cases it would be marked as complete 635 */ 636 if (imxdma_chan_is_doing_cyclic(imxdmac)) 637 goto out; 638 else 639 dma_cookie_complete(&desc->desc); 640 641 /* Free 2D slot if it was an interleaved transfer */ 642 if (imxdmac->enabled_2d) { 643 imxdma->slots_2d[imxdmac->slot_2d].count--; 644 imxdmac->enabled_2d = false; 645 } 646 647 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); 648 649 if (!list_empty(&imxdmac->ld_queue)) { 650 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, 651 node); 652 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); 653 if (imxdma_xfer_desc(desc) < 0) 654 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", 655 __func__, imxdmac->channel); 656 } 657 out: 658 spin_unlock_irqrestore(&imxdma->lock, flags); 659 660 dmaengine_desc_get_callback_invoke(&desc->desc, NULL); 661 } 662 663 static int imxdma_terminate_all(struct dma_chan *chan) 664 { 665 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 666 struct imxdma_engine *imxdma = imxdmac->imxdma; 667 unsigned long flags; 668 669 imxdma_disable_hw(imxdmac); 670 671 spin_lock_irqsave(&imxdma->lock, flags); 672 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); 673 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); 674 spin_unlock_irqrestore(&imxdma->lock, flags); 675 return 0; 676 } 677 678 static int imxdma_config(struct dma_chan *chan, 679 struct dma_slave_config *dmaengine_cfg) 680 { 681 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 682 struct imxdma_engine *imxdma = imxdmac->imxdma; 683 unsigned int mode = 0; 684 685 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 686 imxdmac->per_address = dmaengine_cfg->src_addr; 687 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 688 imxdmac->word_size = dmaengine_cfg->src_addr_width; 689 } else { 690 imxdmac->per_address = dmaengine_cfg->dst_addr; 691 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; 692 imxdmac->word_size = dmaengine_cfg->dst_addr_width; 693 } 694 695 switch (imxdmac->word_size) { 696 case DMA_SLAVE_BUSWIDTH_1_BYTE: 697 mode = IMX_DMA_MEMSIZE_8; 698 break; 699 case DMA_SLAVE_BUSWIDTH_2_BYTES: 700 mode = IMX_DMA_MEMSIZE_16; 701 break; 702 default: 703 case DMA_SLAVE_BUSWIDTH_4_BYTES: 704 mode = IMX_DMA_MEMSIZE_32; 705 break; 706 } 707 708 imxdmac->hw_chaining = 0; 709 710 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | 711 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | 712 CCR_REN; 713 imxdmac->ccr_to_device = 714 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | 715 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; 716 imx_dmav1_writel(imxdma, imxdmac->dma_request, 717 DMA_RSSR(imxdmac->channel)); 718 719 /* Set burst length */ 720 imx_dmav1_writel(imxdma, imxdmac->watermark_level * 721 imxdmac->word_size, DMA_BLR(imxdmac->channel)); 722 723 return 0; 724 } 725 726 static enum dma_status imxdma_tx_status(struct dma_chan *chan, 727 dma_cookie_t cookie, 728 struct dma_tx_state *txstate) 729 { 730 return dma_cookie_status(chan, cookie, txstate); 731 } 732 733 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) 734 { 735 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); 736 struct imxdma_engine *imxdma = imxdmac->imxdma; 737 dma_cookie_t cookie; 738 unsigned long flags; 739 740 spin_lock_irqsave(&imxdma->lock, flags); 741 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); 742 cookie = dma_cookie_assign(tx); 743 spin_unlock_irqrestore(&imxdma->lock, flags); 744 745 return cookie; 746 } 747 748 static int imxdma_alloc_chan_resources(struct dma_chan *chan) 749 { 750 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 751 struct imx_dma_data *data = chan->private; 752 753 if (data != NULL) 754 imxdmac->dma_request = data->dma_request; 755 756 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { 757 struct imxdma_desc *desc; 758 759 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 760 if (!desc) 761 break; 762 memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor)); 763 dma_async_tx_descriptor_init(&desc->desc, chan); 764 desc->desc.tx_submit = imxdma_tx_submit; 765 /* txd.flags will be overwritten in prep funcs */ 766 desc->desc.flags = DMA_CTRL_ACK; 767 desc->status = DMA_COMPLETE; 768 769 list_add_tail(&desc->node, &imxdmac->ld_free); 770 imxdmac->descs_allocated++; 771 } 772 773 if (!imxdmac->descs_allocated) 774 return -ENOMEM; 775 776 return imxdmac->descs_allocated; 777 } 778 779 static void imxdma_free_chan_resources(struct dma_chan *chan) 780 { 781 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 782 struct imxdma_engine *imxdma = imxdmac->imxdma; 783 struct imxdma_desc *desc, *_desc; 784 unsigned long flags; 785 786 spin_lock_irqsave(&imxdma->lock, flags); 787 788 imxdma_disable_hw(imxdmac); 789 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); 790 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); 791 792 spin_unlock_irqrestore(&imxdma->lock, flags); 793 794 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { 795 kfree(desc); 796 imxdmac->descs_allocated--; 797 } 798 INIT_LIST_HEAD(&imxdmac->ld_free); 799 800 kfree(imxdmac->sg_list); 801 imxdmac->sg_list = NULL; 802 } 803 804 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 805 struct dma_chan *chan, struct scatterlist *sgl, 806 unsigned int sg_len, enum dma_transfer_direction direction, 807 unsigned long flags, void *context) 808 { 809 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 810 struct scatterlist *sg; 811 int i, dma_length = 0; 812 struct imxdma_desc *desc; 813 814 if (list_empty(&imxdmac->ld_free) || 815 imxdma_chan_is_doing_cyclic(imxdmac)) 816 return NULL; 817 818 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 819 820 for_each_sg(sgl, sg, sg_len, i) { 821 dma_length += sg_dma_len(sg); 822 } 823 824 switch (imxdmac->word_size) { 825 case DMA_SLAVE_BUSWIDTH_4_BYTES: 826 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) 827 return NULL; 828 break; 829 case DMA_SLAVE_BUSWIDTH_2_BYTES: 830 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) 831 return NULL; 832 break; 833 case DMA_SLAVE_BUSWIDTH_1_BYTE: 834 break; 835 default: 836 return NULL; 837 } 838 839 desc->type = IMXDMA_DESC_SLAVE_SG; 840 desc->sg = sgl; 841 desc->sgcount = sg_len; 842 desc->len = dma_length; 843 desc->direction = direction; 844 if (direction == DMA_DEV_TO_MEM) { 845 desc->src = imxdmac->per_address; 846 } else { 847 desc->dest = imxdmac->per_address; 848 } 849 desc->desc.callback = NULL; 850 desc->desc.callback_param = NULL; 851 852 return &desc->desc; 853 } 854 855 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 856 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 857 size_t period_len, enum dma_transfer_direction direction, 858 unsigned long flags) 859 { 860 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 861 struct imxdma_engine *imxdma = imxdmac->imxdma; 862 struct imxdma_desc *desc; 863 int i; 864 unsigned int periods = buf_len / period_len; 865 866 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n", 867 __func__, imxdmac->channel, buf_len, period_len); 868 869 if (list_empty(&imxdmac->ld_free) || 870 imxdma_chan_is_doing_cyclic(imxdmac)) 871 return NULL; 872 873 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 874 875 kfree(imxdmac->sg_list); 876 877 imxdmac->sg_list = kcalloc(periods + 1, 878 sizeof(struct scatterlist), GFP_ATOMIC); 879 if (!imxdmac->sg_list) 880 return NULL; 881 882 sg_init_table(imxdmac->sg_list, periods); 883 884 for (i = 0; i < periods; i++) { 885 sg_assign_page(&imxdmac->sg_list[i], NULL); 886 imxdmac->sg_list[i].offset = 0; 887 imxdmac->sg_list[i].dma_address = dma_addr; 888 sg_dma_len(&imxdmac->sg_list[i]) = period_len; 889 dma_addr += period_len; 890 } 891 892 /* close the loop */ 893 sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list); 894 895 desc->type = IMXDMA_DESC_CYCLIC; 896 desc->sg = imxdmac->sg_list; 897 desc->sgcount = periods; 898 desc->len = IMX_DMA_LENGTH_LOOP; 899 desc->direction = direction; 900 if (direction == DMA_DEV_TO_MEM) { 901 desc->src = imxdmac->per_address; 902 } else { 903 desc->dest = imxdmac->per_address; 904 } 905 desc->desc.callback = NULL; 906 desc->desc.callback_param = NULL; 907 908 return &desc->desc; 909 } 910 911 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( 912 struct dma_chan *chan, dma_addr_t dest, 913 dma_addr_t src, size_t len, unsigned long flags) 914 { 915 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 916 struct imxdma_engine *imxdma = imxdmac->imxdma; 917 struct imxdma_desc *desc; 918 919 dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n", 920 __func__, imxdmac->channel, (unsigned long long)src, 921 (unsigned long long)dest, len); 922 923 if (list_empty(&imxdmac->ld_free) || 924 imxdma_chan_is_doing_cyclic(imxdmac)) 925 return NULL; 926 927 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 928 929 desc->type = IMXDMA_DESC_MEMCPY; 930 desc->src = src; 931 desc->dest = dest; 932 desc->len = len; 933 desc->direction = DMA_MEM_TO_MEM; 934 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; 935 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; 936 desc->desc.callback = NULL; 937 desc->desc.callback_param = NULL; 938 939 return &desc->desc; 940 } 941 942 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( 943 struct dma_chan *chan, struct dma_interleaved_template *xt, 944 unsigned long flags) 945 { 946 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 947 struct imxdma_engine *imxdma = imxdmac->imxdma; 948 struct imxdma_desc *desc; 949 950 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n" 951 " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__, 952 imxdmac->channel, (unsigned long long)xt->src_start, 953 (unsigned long long) xt->dst_start, 954 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", 955 xt->numf, xt->frame_size); 956 957 if (list_empty(&imxdmac->ld_free) || 958 imxdma_chan_is_doing_cyclic(imxdmac)) 959 return NULL; 960 961 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) 962 return NULL; 963 964 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 965 966 desc->type = IMXDMA_DESC_INTERLEAVED; 967 desc->src = xt->src_start; 968 desc->dest = xt->dst_start; 969 desc->x = xt->sgl[0].size; 970 desc->y = xt->numf; 971 desc->w = xt->sgl[0].icg + desc->x; 972 desc->len = desc->x * desc->y; 973 desc->direction = DMA_MEM_TO_MEM; 974 desc->config_port = IMX_DMA_MEMSIZE_32; 975 desc->config_mem = IMX_DMA_MEMSIZE_32; 976 if (xt->src_sgl) 977 desc->config_mem |= IMX_DMA_TYPE_2D; 978 if (xt->dst_sgl) 979 desc->config_port |= IMX_DMA_TYPE_2D; 980 desc->desc.callback = NULL; 981 desc->desc.callback_param = NULL; 982 983 return &desc->desc; 984 } 985 986 static void imxdma_issue_pending(struct dma_chan *chan) 987 { 988 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 989 struct imxdma_engine *imxdma = imxdmac->imxdma; 990 struct imxdma_desc *desc; 991 unsigned long flags; 992 993 spin_lock_irqsave(&imxdma->lock, flags); 994 if (list_empty(&imxdmac->ld_active) && 995 !list_empty(&imxdmac->ld_queue)) { 996 desc = list_first_entry(&imxdmac->ld_queue, 997 struct imxdma_desc, node); 998 999 if (imxdma_xfer_desc(desc) < 0) { 1000 dev_warn(imxdma->dev, 1001 "%s: channel: %d couldn't issue DMA xfer\n", 1002 __func__, imxdmac->channel); 1003 } else { 1004 list_move_tail(imxdmac->ld_queue.next, 1005 &imxdmac->ld_active); 1006 } 1007 } 1008 spin_unlock_irqrestore(&imxdma->lock, flags); 1009 } 1010 1011 static bool imxdma_filter_fn(struct dma_chan *chan, void *param) 1012 { 1013 struct imxdma_filter_data *fdata = param; 1014 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); 1015 1016 if (chan->device->dev != fdata->imxdma->dev) 1017 return false; 1018 1019 imxdma_chan->dma_request = fdata->request; 1020 chan->private = NULL; 1021 1022 return true; 1023 } 1024 1025 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, 1026 struct of_dma *ofdma) 1027 { 1028 int count = dma_spec->args_count; 1029 struct imxdma_engine *imxdma = ofdma->of_dma_data; 1030 struct imxdma_filter_data fdata = { 1031 .imxdma = imxdma, 1032 }; 1033 1034 if (count != 1) 1035 return NULL; 1036 1037 fdata.request = dma_spec->args[0]; 1038 1039 return dma_request_channel(imxdma->dma_device.cap_mask, 1040 imxdma_filter_fn, &fdata); 1041 } 1042 1043 static int __init imxdma_probe(struct platform_device *pdev) 1044 { 1045 struct imxdma_engine *imxdma; 1046 struct resource *res; 1047 const struct of_device_id *of_id; 1048 int ret, i; 1049 int irq, irq_err; 1050 1051 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); 1052 if (of_id) 1053 pdev->id_entry = of_id->data; 1054 1055 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); 1056 if (!imxdma) 1057 return -ENOMEM; 1058 1059 imxdma->dev = &pdev->dev; 1060 imxdma->devtype = pdev->id_entry->driver_data; 1061 1062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1063 imxdma->base = devm_ioremap_resource(&pdev->dev, res); 1064 if (IS_ERR(imxdma->base)) 1065 return PTR_ERR(imxdma->base); 1066 1067 irq = platform_get_irq(pdev, 0); 1068 if (irq < 0) 1069 return irq; 1070 1071 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); 1072 if (IS_ERR(imxdma->dma_ipg)) 1073 return PTR_ERR(imxdma->dma_ipg); 1074 1075 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); 1076 if (IS_ERR(imxdma->dma_ahb)) 1077 return PTR_ERR(imxdma->dma_ahb); 1078 1079 ret = clk_prepare_enable(imxdma->dma_ipg); 1080 if (ret) 1081 return ret; 1082 ret = clk_prepare_enable(imxdma->dma_ahb); 1083 if (ret) 1084 goto disable_dma_ipg_clk; 1085 1086 /* reset DMA module */ 1087 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); 1088 1089 if (is_imx1_dma(imxdma)) { 1090 ret = devm_request_irq(&pdev->dev, irq, 1091 dma_irq_handler, 0, "DMA", imxdma); 1092 if (ret) { 1093 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); 1094 goto disable_dma_ahb_clk; 1095 } 1096 imxdma->irq = irq; 1097 1098 irq_err = platform_get_irq(pdev, 1); 1099 if (irq_err < 0) { 1100 ret = irq_err; 1101 goto disable_dma_ahb_clk; 1102 } 1103 1104 ret = devm_request_irq(&pdev->dev, irq_err, 1105 imxdma_err_handler, 0, "DMA", imxdma); 1106 if (ret) { 1107 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); 1108 goto disable_dma_ahb_clk; 1109 } 1110 imxdma->irq_err = irq_err; 1111 } 1112 1113 /* enable DMA module */ 1114 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); 1115 1116 /* clear all interrupts */ 1117 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); 1118 1119 /* disable interrupts */ 1120 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); 1121 1122 INIT_LIST_HEAD(&imxdma->dma_device.channels); 1123 1124 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 1125 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 1126 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); 1127 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); 1128 1129 /* Initialize 2D global parameters */ 1130 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) 1131 imxdma->slots_2d[i].count = 0; 1132 1133 spin_lock_init(&imxdma->lock); 1134 1135 /* Initialize channel parameters */ 1136 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 1137 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 1138 1139 if (!is_imx1_dma(imxdma)) { 1140 ret = devm_request_irq(&pdev->dev, irq + i, 1141 dma_irq_handler, 0, "DMA", imxdma); 1142 if (ret) { 1143 dev_warn(imxdma->dev, "Can't register IRQ %d " 1144 "for DMA channel %d\n", 1145 irq + i, i); 1146 goto disable_dma_ahb_clk; 1147 } 1148 1149 imxdmac->irq = irq + i; 1150 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0); 1151 } 1152 1153 imxdmac->imxdma = imxdma; 1154 1155 INIT_LIST_HEAD(&imxdmac->ld_queue); 1156 INIT_LIST_HEAD(&imxdmac->ld_free); 1157 INIT_LIST_HEAD(&imxdmac->ld_active); 1158 1159 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, 1160 (unsigned long)imxdmac); 1161 imxdmac->chan.device = &imxdma->dma_device; 1162 dma_cookie_init(&imxdmac->chan); 1163 imxdmac->channel = i; 1164 1165 /* Add the channel to the DMAC list */ 1166 list_add_tail(&imxdmac->chan.device_node, 1167 &imxdma->dma_device.channels); 1168 } 1169 1170 imxdma->dma_device.dev = &pdev->dev; 1171 1172 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; 1173 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; 1174 imxdma->dma_device.device_tx_status = imxdma_tx_status; 1175 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; 1176 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; 1177 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; 1178 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; 1179 imxdma->dma_device.device_config = imxdma_config; 1180 imxdma->dma_device.device_terminate_all = imxdma_terminate_all; 1181 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 1182 1183 platform_set_drvdata(pdev, imxdma); 1184 1185 imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES; 1186 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; 1187 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); 1188 1189 ret = dma_async_device_register(&imxdma->dma_device); 1190 if (ret) { 1191 dev_err(&pdev->dev, "unable to register\n"); 1192 goto disable_dma_ahb_clk; 1193 } 1194 1195 if (pdev->dev.of_node) { 1196 ret = of_dma_controller_register(pdev->dev.of_node, 1197 imxdma_xlate, imxdma); 1198 if (ret) { 1199 dev_err(&pdev->dev, "unable to register of_dma_controller\n"); 1200 goto err_of_dma_controller; 1201 } 1202 } 1203 1204 return 0; 1205 1206 err_of_dma_controller: 1207 dma_async_device_unregister(&imxdma->dma_device); 1208 disable_dma_ahb_clk: 1209 clk_disable_unprepare(imxdma->dma_ahb); 1210 disable_dma_ipg_clk: 1211 clk_disable_unprepare(imxdma->dma_ipg); 1212 return ret; 1213 } 1214 1215 static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma) 1216 { 1217 int i; 1218 1219 if (is_imx1_dma(imxdma)) { 1220 disable_irq(imxdma->irq); 1221 disable_irq(imxdma->irq_err); 1222 } 1223 1224 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 1225 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 1226 1227 if (!is_imx1_dma(imxdma)) 1228 disable_irq(imxdmac->irq); 1229 1230 tasklet_kill(&imxdmac->dma_tasklet); 1231 } 1232 } 1233 1234 static int imxdma_remove(struct platform_device *pdev) 1235 { 1236 struct imxdma_engine *imxdma = platform_get_drvdata(pdev); 1237 1238 imxdma_free_irq(pdev, imxdma); 1239 1240 dma_async_device_unregister(&imxdma->dma_device); 1241 1242 if (pdev->dev.of_node) 1243 of_dma_controller_free(pdev->dev.of_node); 1244 1245 clk_disable_unprepare(imxdma->dma_ipg); 1246 clk_disable_unprepare(imxdma->dma_ahb); 1247 1248 return 0; 1249 } 1250 1251 static struct platform_driver imxdma_driver = { 1252 .driver = { 1253 .name = "imx-dma", 1254 .of_match_table = imx_dma_of_dev_id, 1255 }, 1256 .id_table = imx_dma_devtype, 1257 .remove = imxdma_remove, 1258 }; 1259 1260 static int __init imxdma_module_init(void) 1261 { 1262 return platform_driver_probe(&imxdma_driver, imxdma_probe); 1263 } 1264 subsys_initcall(imxdma_module_init); 1265 1266 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1267 MODULE_DESCRIPTION("i.MX dma driver"); 1268 MODULE_LICENSE("GPL"); 1269