1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_REGISTERS_H_ 4 #define _IDXD_REGISTERS_H_ 5 6 /* PCI Config */ 7 #define PCI_DEVICE_ID_INTEL_DSA_SPR0 0x0b25 8 9 #define IDXD_MMIO_BAR 0 10 #define IDXD_WQ_BAR 2 11 #define IDXD_PORTAL_SIZE 0x4000 12 13 /* MMIO Device BAR0 Registers */ 14 #define IDXD_VER_OFFSET 0x00 15 #define IDXD_VER_MAJOR_MASK 0xf0 16 #define IDXD_VER_MINOR_MASK 0x0f 17 #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4) 18 #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK) 19 20 union gen_cap_reg { 21 struct { 22 u64 block_on_fault:1; 23 u64 overlap_copy:1; 24 u64 cache_control_mem:1; 25 u64 cache_control_cache:1; 26 u64 rsvd:3; 27 u64 int_handle_req:1; 28 u64 dest_readback:1; 29 u64 drain_readback:1; 30 u64 rsvd2:6; 31 u64 max_xfer_shift:5; 32 u64 max_batch_shift:4; 33 u64 max_ims_mult:6; 34 u64 config_en:1; 35 u64 max_descs_per_engine:8; 36 u64 rsvd3:24; 37 }; 38 u64 bits; 39 } __packed; 40 #define IDXD_GENCAP_OFFSET 0x10 41 42 union wq_cap_reg { 43 struct { 44 u64 total_wq_size:16; 45 u64 num_wqs:8; 46 u64 rsvd:24; 47 u64 shared_mode:1; 48 u64 dedicated_mode:1; 49 u64 rsvd2:1; 50 u64 priority:1; 51 u64 occupancy:1; 52 u64 occupancy_int:1; 53 u64 rsvd3:10; 54 }; 55 u64 bits; 56 } __packed; 57 #define IDXD_WQCAP_OFFSET 0x20 58 59 union group_cap_reg { 60 struct { 61 u64 num_groups:8; 62 u64 total_tokens:8; 63 u64 token_en:1; 64 u64 token_limit:1; 65 u64 rsvd:46; 66 }; 67 u64 bits; 68 } __packed; 69 #define IDXD_GRPCAP_OFFSET 0x30 70 71 union engine_cap_reg { 72 struct { 73 u64 num_engines:8; 74 u64 rsvd:56; 75 }; 76 u64 bits; 77 } __packed; 78 79 #define IDXD_ENGCAP_OFFSET 0x38 80 81 #define IDXD_OPCAP_NOOP 0x0001 82 #define IDXD_OPCAP_BATCH 0x0002 83 #define IDXD_OPCAP_MEMMOVE 0x0008 84 struct opcap { 85 u64 bits[4]; 86 }; 87 88 #define IDXD_OPCAP_OFFSET 0x40 89 90 #define IDXD_TABLE_OFFSET 0x60 91 union offsets_reg { 92 struct { 93 u64 grpcfg:16; 94 u64 wqcfg:16; 95 u64 msix_perm:16; 96 u64 ims:16; 97 u64 perfmon:16; 98 u64 rsvd:48; 99 }; 100 u64 bits[2]; 101 } __packed; 102 103 #define IDXD_GENCFG_OFFSET 0x80 104 union gencfg_reg { 105 struct { 106 u32 token_limit:8; 107 u32 rsvd:4; 108 u32 user_int_en:1; 109 u32 rsvd2:19; 110 }; 111 u32 bits; 112 } __packed; 113 114 #define IDXD_GENCTRL_OFFSET 0x88 115 union genctrl_reg { 116 struct { 117 u32 softerr_int_en:1; 118 u32 rsvd:31; 119 }; 120 u32 bits; 121 } __packed; 122 123 #define IDXD_GENSTATS_OFFSET 0x90 124 union gensts_reg { 125 struct { 126 u32 state:2; 127 u32 reset_type:2; 128 u32 rsvd:28; 129 }; 130 u32 bits; 131 } __packed; 132 133 enum idxd_device_status_state { 134 IDXD_DEVICE_STATE_DISABLED = 0, 135 IDXD_DEVICE_STATE_ENABLED, 136 IDXD_DEVICE_STATE_DRAIN, 137 IDXD_DEVICE_STATE_HALT, 138 }; 139 140 enum idxd_device_reset_type { 141 IDXD_DEVICE_RESET_SOFTWARE = 0, 142 IDXD_DEVICE_RESET_FLR, 143 IDXD_DEVICE_RESET_WARM, 144 IDXD_DEVICE_RESET_COLD, 145 }; 146 147 #define IDXD_INTCAUSE_OFFSET 0x98 148 #define IDXD_INTC_ERR 0x01 149 #define IDXD_INTC_CMD 0x02 150 #define IDXD_INTC_OCCUPY 0x04 151 #define IDXD_INTC_PERFMON_OVFL 0x08 152 153 #define IDXD_CMD_OFFSET 0xa0 154 union idxd_command_reg { 155 struct { 156 u32 operand:20; 157 u32 cmd:5; 158 u32 rsvd:6; 159 u32 int_req:1; 160 }; 161 u32 bits; 162 } __packed; 163 164 enum idxd_cmd { 165 IDXD_CMD_ENABLE_DEVICE = 1, 166 IDXD_CMD_DISABLE_DEVICE, 167 IDXD_CMD_DRAIN_ALL, 168 IDXD_CMD_ABORT_ALL, 169 IDXD_CMD_RESET_DEVICE, 170 IDXD_CMD_ENABLE_WQ, 171 IDXD_CMD_DISABLE_WQ, 172 IDXD_CMD_DRAIN_WQ, 173 IDXD_CMD_ABORT_WQ, 174 IDXD_CMD_RESET_WQ, 175 IDXD_CMD_DRAIN_PASID, 176 IDXD_CMD_ABORT_PASID, 177 IDXD_CMD_REQUEST_INT_HANDLE, 178 }; 179 180 #define IDXD_CMDSTS_OFFSET 0xa8 181 union cmdsts_reg { 182 struct { 183 u8 err; 184 u16 result; 185 u8 rsvd:7; 186 u8 active:1; 187 }; 188 u32 bits; 189 } __packed; 190 #define IDXD_CMDSTS_ACTIVE 0x80000000 191 192 enum idxd_cmdsts_err { 193 IDXD_CMDSTS_SUCCESS = 0, 194 IDXD_CMDSTS_INVAL_CMD, 195 IDXD_CMDSTS_INVAL_WQIDX, 196 IDXD_CMDSTS_HW_ERR, 197 /* enable device errors */ 198 IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10, 199 IDXD_CMDSTS_ERR_CONFIG, 200 IDXD_CMDSTS_ERR_BUSMASTER_EN, 201 IDXD_CMDSTS_ERR_PASID_INVAL, 202 IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE, 203 IDXD_CMDSTS_ERR_GRP_CONFIG, 204 IDXD_CMDSTS_ERR_GRP_CONFIG2, 205 IDXD_CMDSTS_ERR_GRP_CONFIG3, 206 IDXD_CMDSTS_ERR_GRP_CONFIG4, 207 /* enable wq errors */ 208 IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20, 209 IDXD_CMDSTS_ERR_WQ_ENABLED, 210 IDXD_CMDSTS_ERR_WQ_SIZE, 211 IDXD_CMDSTS_ERR_WQ_PRIOR, 212 IDXD_CMDSTS_ERR_WQ_MODE, 213 IDXD_CMDSTS_ERR_BOF_EN, 214 IDXD_CMDSTS_ERR_PASID_EN, 215 IDXD_CMDSTS_ERR_MAX_BATCH_SIZE, 216 IDXD_CMDSTS_ERR_MAX_XFER_SIZE, 217 /* disable device errors */ 218 IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31, 219 /* disable WQ, drain WQ, abort WQ, reset WQ */ 220 IDXD_CMDSTS_ERR_DEV_NOT_EN, 221 /* request interrupt handle */ 222 IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41, 223 IDXD_CMDSTS_ERR_NO_HANDLE, 224 }; 225 226 #define IDXD_SWERR_OFFSET 0xc0 227 #define IDXD_SWERR_VALID 0x00000001 228 #define IDXD_SWERR_OVERFLOW 0x00000002 229 #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW) 230 union sw_err_reg { 231 struct { 232 u64 valid:1; 233 u64 overflow:1; 234 u64 desc_valid:1; 235 u64 wq_idx_valid:1; 236 u64 batch:1; 237 u64 fault_rw:1; 238 u64 priv:1; 239 u64 rsvd:1; 240 u64 error:8; 241 u64 wq_idx:8; 242 u64 rsvd2:8; 243 u64 operation:8; 244 u64 pasid:20; 245 u64 rsvd3:4; 246 247 u64 batch_idx:16; 248 u64 rsvd4:16; 249 u64 invalid_flags:32; 250 251 u64 fault_addr; 252 253 u64 rsvd5; 254 }; 255 u64 bits[4]; 256 } __packed; 257 258 union msix_perm { 259 struct { 260 u32 rsvd:2; 261 u32 ignore:1; 262 u32 pasid_en:1; 263 u32 rsvd2:8; 264 u32 pasid:20; 265 }; 266 u32 bits; 267 } __packed; 268 269 union group_flags { 270 struct { 271 u32 tc_a:3; 272 u32 tc_b:3; 273 u32 rsvd:1; 274 u32 use_token_limit:1; 275 u32 tokens_reserved:8; 276 u32 rsvd2:4; 277 u32 tokens_allowed:8; 278 u32 rsvd3:4; 279 }; 280 u32 bits; 281 } __packed; 282 283 struct grpcfg { 284 u64 wqs[4]; 285 u64 engines; 286 union group_flags flags; 287 } __packed; 288 289 union wqcfg { 290 struct { 291 /* bytes 0-3 */ 292 u16 wq_size; 293 u16 rsvd; 294 295 /* bytes 4-7 */ 296 u16 wq_thresh; 297 u16 rsvd1; 298 299 /* bytes 8-11 */ 300 u32 mode:1; /* shared or dedicated */ 301 u32 bof:1; /* block on fault */ 302 u32 rsvd2:2; 303 u32 priority:4; 304 u32 pasid:20; 305 u32 pasid_en:1; 306 u32 priv:1; 307 u32 rsvd3:2; 308 309 /* bytes 12-15 */ 310 u32 max_xfer_shift:5; 311 u32 max_batch_shift:4; 312 u32 rsvd4:23; 313 314 /* bytes 16-19 */ 315 u16 occupancy_inth; 316 u16 occupancy_table_sel:1; 317 u16 rsvd5:15; 318 319 /* bytes 20-23 */ 320 u16 occupancy_limit; 321 u16 occupancy_int_en:1; 322 u16 rsvd6:15; 323 324 /* bytes 24-27 */ 325 u16 occupancy; 326 u16 occupancy_int:1; 327 u16 rsvd7:12; 328 u16 mode_support:1; 329 u16 wq_state:2; 330 331 /* bytes 28-31 */ 332 u32 rsvd8; 333 }; 334 u32 bits[8]; 335 } __packed; 336 #endif 337