1bfe1d560SDave Jiang /* SPDX-License-Identifier: GPL-2.0 */ 2bfe1d560SDave Jiang /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3bfe1d560SDave Jiang #ifndef _IDXD_REGISTERS_H_ 4bfe1d560SDave Jiang #define _IDXD_REGISTERS_H_ 5bfe1d560SDave Jiang 6bfe1d560SDave Jiang /* PCI Config */ 7bfe1d560SDave Jiang #define PCI_DEVICE_ID_INTEL_DSA_SPR0 0x0b25 8*f25b4638SDave Jiang #define PCI_DEVICE_ID_INTEL_IAX_SPR0 0x0cfe 9bfe1d560SDave Jiang 10bfe1d560SDave Jiang #define IDXD_MMIO_BAR 0 11bfe1d560SDave Jiang #define IDXD_WQ_BAR 2 12c52ca478SDave Jiang #define IDXD_PORTAL_SIZE 0x4000 13bfe1d560SDave Jiang 14bfe1d560SDave Jiang /* MMIO Device BAR0 Registers */ 15bfe1d560SDave Jiang #define IDXD_VER_OFFSET 0x00 16bfe1d560SDave Jiang #define IDXD_VER_MAJOR_MASK 0xf0 17bfe1d560SDave Jiang #define IDXD_VER_MINOR_MASK 0x0f 18bfe1d560SDave Jiang #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4) 19bfe1d560SDave Jiang #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK) 20bfe1d560SDave Jiang 21bfe1d560SDave Jiang union gen_cap_reg { 22bfe1d560SDave Jiang struct { 23bfe1d560SDave Jiang u64 block_on_fault:1; 24bfe1d560SDave Jiang u64 overlap_copy:1; 25bfe1d560SDave Jiang u64 cache_control_mem:1; 26bfe1d560SDave Jiang u64 cache_control_cache:1; 27bfe1d560SDave Jiang u64 rsvd:3; 28bfe1d560SDave Jiang u64 int_handle_req:1; 29bfe1d560SDave Jiang u64 dest_readback:1; 30bfe1d560SDave Jiang u64 drain_readback:1; 31bfe1d560SDave Jiang u64 rsvd2:6; 32bfe1d560SDave Jiang u64 max_xfer_shift:5; 33bfe1d560SDave Jiang u64 max_batch_shift:4; 34bfe1d560SDave Jiang u64 max_ims_mult:6; 35bfe1d560SDave Jiang u64 config_en:1; 36bfe1d560SDave Jiang u64 max_descs_per_engine:8; 37bfe1d560SDave Jiang u64 rsvd3:24; 38bfe1d560SDave Jiang }; 39bfe1d560SDave Jiang u64 bits; 40bfe1d560SDave Jiang } __packed; 41bfe1d560SDave Jiang #define IDXD_GENCAP_OFFSET 0x10 42bfe1d560SDave Jiang 43bfe1d560SDave Jiang union wq_cap_reg { 44bfe1d560SDave Jiang struct { 45bfe1d560SDave Jiang u64 total_wq_size:16; 46bfe1d560SDave Jiang u64 num_wqs:8; 47d98793b5SDave Jiang u64 wqcfg_size:4; 48d98793b5SDave Jiang u64 rsvd:20; 49bfe1d560SDave Jiang u64 shared_mode:1; 50bfe1d560SDave Jiang u64 dedicated_mode:1; 5192de5fa2SDave Jiang u64 wq_ats_support:1; 52bfe1d560SDave Jiang u64 priority:1; 53bfe1d560SDave Jiang u64 occupancy:1; 54bfe1d560SDave Jiang u64 occupancy_int:1; 55bfe1d560SDave Jiang u64 rsvd3:10; 56bfe1d560SDave Jiang }; 57bfe1d560SDave Jiang u64 bits; 58bfe1d560SDave Jiang } __packed; 59bfe1d560SDave Jiang #define IDXD_WQCAP_OFFSET 0x20 60d98793b5SDave Jiang #define IDXD_WQCFG_MIN 5 61bfe1d560SDave Jiang 62bfe1d560SDave Jiang union group_cap_reg { 63bfe1d560SDave Jiang struct { 64bfe1d560SDave Jiang u64 num_groups:8; 65bfe1d560SDave Jiang u64 total_tokens:8; 66bfe1d560SDave Jiang u64 token_en:1; 67bfe1d560SDave Jiang u64 token_limit:1; 68bfe1d560SDave Jiang u64 rsvd:46; 69bfe1d560SDave Jiang }; 70bfe1d560SDave Jiang u64 bits; 71bfe1d560SDave Jiang } __packed; 72bfe1d560SDave Jiang #define IDXD_GRPCAP_OFFSET 0x30 73bfe1d560SDave Jiang 74bfe1d560SDave Jiang union engine_cap_reg { 75bfe1d560SDave Jiang struct { 76bfe1d560SDave Jiang u64 num_engines:8; 77bfe1d560SDave Jiang u64 rsvd:56; 78bfe1d560SDave Jiang }; 79bfe1d560SDave Jiang u64 bits; 80bfe1d560SDave Jiang } __packed; 81bfe1d560SDave Jiang 82bfe1d560SDave Jiang #define IDXD_ENGCAP_OFFSET 0x38 83bfe1d560SDave Jiang 84bfe1d560SDave Jiang #define IDXD_OPCAP_NOOP 0x0001 85bfe1d560SDave Jiang #define IDXD_OPCAP_BATCH 0x0002 86bfe1d560SDave Jiang #define IDXD_OPCAP_MEMMOVE 0x0008 87bfe1d560SDave Jiang struct opcap { 88bfe1d560SDave Jiang u64 bits[4]; 89bfe1d560SDave Jiang }; 90bfe1d560SDave Jiang 91bfe1d560SDave Jiang #define IDXD_OPCAP_OFFSET 0x40 92bfe1d560SDave Jiang 93bfe1d560SDave Jiang #define IDXD_TABLE_OFFSET 0x60 94bfe1d560SDave Jiang union offsets_reg { 95bfe1d560SDave Jiang struct { 96bfe1d560SDave Jiang u64 grpcfg:16; 97bfe1d560SDave Jiang u64 wqcfg:16; 98bfe1d560SDave Jiang u64 msix_perm:16; 99bfe1d560SDave Jiang u64 ims:16; 100bfe1d560SDave Jiang u64 perfmon:16; 101bfe1d560SDave Jiang u64 rsvd:48; 102bfe1d560SDave Jiang }; 103bfe1d560SDave Jiang u64 bits[2]; 104bfe1d560SDave Jiang } __packed; 105bfe1d560SDave Jiang 1062f8417a9SDave Jiang #define IDXD_TABLE_MULT 0x100 1072f8417a9SDave Jiang 108bfe1d560SDave Jiang #define IDXD_GENCFG_OFFSET 0x80 109bfe1d560SDave Jiang union gencfg_reg { 110bfe1d560SDave Jiang struct { 111bfe1d560SDave Jiang u32 token_limit:8; 112bfe1d560SDave Jiang u32 rsvd:4; 113bfe1d560SDave Jiang u32 user_int_en:1; 114bfe1d560SDave Jiang u32 rsvd2:19; 115bfe1d560SDave Jiang }; 116bfe1d560SDave Jiang u32 bits; 117bfe1d560SDave Jiang } __packed; 118bfe1d560SDave Jiang 119bfe1d560SDave Jiang #define IDXD_GENCTRL_OFFSET 0x88 120bfe1d560SDave Jiang union genctrl_reg { 121bfe1d560SDave Jiang struct { 122bfe1d560SDave Jiang u32 softerr_int_en:1; 123bfe1d560SDave Jiang u32 rsvd:31; 124bfe1d560SDave Jiang }; 125bfe1d560SDave Jiang u32 bits; 126bfe1d560SDave Jiang } __packed; 127bfe1d560SDave Jiang 128bfe1d560SDave Jiang #define IDXD_GENSTATS_OFFSET 0x90 129bfe1d560SDave Jiang union gensts_reg { 130bfe1d560SDave Jiang struct { 131bfe1d560SDave Jiang u32 state:2; 132bfe1d560SDave Jiang u32 reset_type:2; 133bfe1d560SDave Jiang u32 rsvd:28; 134bfe1d560SDave Jiang }; 135bfe1d560SDave Jiang u32 bits; 136bfe1d560SDave Jiang } __packed; 137bfe1d560SDave Jiang 138bfe1d560SDave Jiang enum idxd_device_status_state { 139bfe1d560SDave Jiang IDXD_DEVICE_STATE_DISABLED = 0, 140bfe1d560SDave Jiang IDXD_DEVICE_STATE_ENABLED, 141bfe1d560SDave Jiang IDXD_DEVICE_STATE_DRAIN, 142bfe1d560SDave Jiang IDXD_DEVICE_STATE_HALT, 143bfe1d560SDave Jiang }; 144bfe1d560SDave Jiang 145bfe1d560SDave Jiang enum idxd_device_reset_type { 146bfe1d560SDave Jiang IDXD_DEVICE_RESET_SOFTWARE = 0, 147bfe1d560SDave Jiang IDXD_DEVICE_RESET_FLR, 148bfe1d560SDave Jiang IDXD_DEVICE_RESET_WARM, 149bfe1d560SDave Jiang IDXD_DEVICE_RESET_COLD, 150bfe1d560SDave Jiang }; 151bfe1d560SDave Jiang 152bfe1d560SDave Jiang #define IDXD_INTCAUSE_OFFSET 0x98 153bfe1d560SDave Jiang #define IDXD_INTC_ERR 0x01 154bfe1d560SDave Jiang #define IDXD_INTC_CMD 0x02 155bfe1d560SDave Jiang #define IDXD_INTC_OCCUPY 0x04 156bfe1d560SDave Jiang #define IDXD_INTC_PERFMON_OVFL 0x08 157bfe1d560SDave Jiang 158bfe1d560SDave Jiang #define IDXD_CMD_OFFSET 0xa0 159bfe1d560SDave Jiang union idxd_command_reg { 160bfe1d560SDave Jiang struct { 161bfe1d560SDave Jiang u32 operand:20; 162bfe1d560SDave Jiang u32 cmd:5; 163bfe1d560SDave Jiang u32 rsvd:6; 164bfe1d560SDave Jiang u32 int_req:1; 165bfe1d560SDave Jiang }; 166bfe1d560SDave Jiang u32 bits; 167bfe1d560SDave Jiang } __packed; 168bfe1d560SDave Jiang 169bfe1d560SDave Jiang enum idxd_cmd { 170bfe1d560SDave Jiang IDXD_CMD_ENABLE_DEVICE = 1, 171bfe1d560SDave Jiang IDXD_CMD_DISABLE_DEVICE, 172bfe1d560SDave Jiang IDXD_CMD_DRAIN_ALL, 173bfe1d560SDave Jiang IDXD_CMD_ABORT_ALL, 174bfe1d560SDave Jiang IDXD_CMD_RESET_DEVICE, 175bfe1d560SDave Jiang IDXD_CMD_ENABLE_WQ, 176bfe1d560SDave Jiang IDXD_CMD_DISABLE_WQ, 177bfe1d560SDave Jiang IDXD_CMD_DRAIN_WQ, 178bfe1d560SDave Jiang IDXD_CMD_ABORT_WQ, 179bfe1d560SDave Jiang IDXD_CMD_RESET_WQ, 180bfe1d560SDave Jiang IDXD_CMD_DRAIN_PASID, 181bfe1d560SDave Jiang IDXD_CMD_ABORT_PASID, 182bfe1d560SDave Jiang IDXD_CMD_REQUEST_INT_HANDLE, 183bfe1d560SDave Jiang }; 184bfe1d560SDave Jiang 185bfe1d560SDave Jiang #define IDXD_CMDSTS_OFFSET 0xa8 186bfe1d560SDave Jiang union cmdsts_reg { 187bfe1d560SDave Jiang struct { 188bfe1d560SDave Jiang u8 err; 189bfe1d560SDave Jiang u16 result; 190bfe1d560SDave Jiang u8 rsvd:7; 191bfe1d560SDave Jiang u8 active:1; 192bfe1d560SDave Jiang }; 193bfe1d560SDave Jiang u32 bits; 194bfe1d560SDave Jiang } __packed; 195bfe1d560SDave Jiang #define IDXD_CMDSTS_ACTIVE 0x80000000 196bfe1d560SDave Jiang 197bfe1d560SDave Jiang enum idxd_cmdsts_err { 198bfe1d560SDave Jiang IDXD_CMDSTS_SUCCESS = 0, 199bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_CMD, 200bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_WQIDX, 201bfe1d560SDave Jiang IDXD_CMDSTS_HW_ERR, 202bfe1d560SDave Jiang /* enable device errors */ 203bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10, 204bfe1d560SDave Jiang IDXD_CMDSTS_ERR_CONFIG, 205bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BUSMASTER_EN, 206bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_INVAL, 207bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE, 208bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG, 209bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG2, 210bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG3, 211bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG4, 212bfe1d560SDave Jiang /* enable wq errors */ 213bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20, 214bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_ENABLED, 215bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE, 216bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_PRIOR, 217bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_MODE, 218bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BOF_EN, 219bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_EN, 220bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_BATCH_SIZE, 221bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_XFER_SIZE, 222bfe1d560SDave Jiang /* disable device errors */ 223bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31, 224bfe1d560SDave Jiang /* disable WQ, drain WQ, abort WQ, reset WQ */ 225bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOT_EN, 226bfe1d560SDave Jiang /* request interrupt handle */ 227bfe1d560SDave Jiang IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41, 228bfe1d560SDave Jiang IDXD_CMDSTS_ERR_NO_HANDLE, 229bfe1d560SDave Jiang }; 230bfe1d560SDave Jiang 231bfe1d560SDave Jiang #define IDXD_SWERR_OFFSET 0xc0 232bfe1d560SDave Jiang #define IDXD_SWERR_VALID 0x00000001 233bfe1d560SDave Jiang #define IDXD_SWERR_OVERFLOW 0x00000002 234bfe1d560SDave Jiang #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW) 235bfe1d560SDave Jiang union sw_err_reg { 236bfe1d560SDave Jiang struct { 237bfe1d560SDave Jiang u64 valid:1; 238bfe1d560SDave Jiang u64 overflow:1; 239bfe1d560SDave Jiang u64 desc_valid:1; 240bfe1d560SDave Jiang u64 wq_idx_valid:1; 241bfe1d560SDave Jiang u64 batch:1; 242bfe1d560SDave Jiang u64 fault_rw:1; 243bfe1d560SDave Jiang u64 priv:1; 244bfe1d560SDave Jiang u64 rsvd:1; 245bfe1d560SDave Jiang u64 error:8; 246bfe1d560SDave Jiang u64 wq_idx:8; 247bfe1d560SDave Jiang u64 rsvd2:8; 248bfe1d560SDave Jiang u64 operation:8; 249bfe1d560SDave Jiang u64 pasid:20; 250bfe1d560SDave Jiang u64 rsvd3:4; 251bfe1d560SDave Jiang 252bfe1d560SDave Jiang u64 batch_idx:16; 253bfe1d560SDave Jiang u64 rsvd4:16; 254bfe1d560SDave Jiang u64 invalid_flags:32; 255bfe1d560SDave Jiang 256bfe1d560SDave Jiang u64 fault_addr; 257bfe1d560SDave Jiang 258bfe1d560SDave Jiang u64 rsvd5; 259bfe1d560SDave Jiang }; 260bfe1d560SDave Jiang u64 bits[4]; 261bfe1d560SDave Jiang } __packed; 262bfe1d560SDave Jiang 263bfe1d560SDave Jiang union msix_perm { 264bfe1d560SDave Jiang struct { 265bfe1d560SDave Jiang u32 rsvd:2; 266bfe1d560SDave Jiang u32 ignore:1; 267bfe1d560SDave Jiang u32 pasid_en:1; 268bfe1d560SDave Jiang u32 rsvd2:8; 269bfe1d560SDave Jiang u32 pasid:20; 270bfe1d560SDave Jiang }; 271bfe1d560SDave Jiang u32 bits; 272bfe1d560SDave Jiang } __packed; 273bfe1d560SDave Jiang 274bfe1d560SDave Jiang union group_flags { 275bfe1d560SDave Jiang struct { 276bfe1d560SDave Jiang u32 tc_a:3; 277bfe1d560SDave Jiang u32 tc_b:3; 278bfe1d560SDave Jiang u32 rsvd:1; 279bfe1d560SDave Jiang u32 use_token_limit:1; 280bfe1d560SDave Jiang u32 tokens_reserved:8; 281bfe1d560SDave Jiang u32 rsvd2:4; 282bfe1d560SDave Jiang u32 tokens_allowed:8; 283bfe1d560SDave Jiang u32 rsvd3:4; 284bfe1d560SDave Jiang }; 285bfe1d560SDave Jiang u32 bits; 286bfe1d560SDave Jiang } __packed; 287bfe1d560SDave Jiang 288bfe1d560SDave Jiang struct grpcfg { 289bfe1d560SDave Jiang u64 wqs[4]; 290bfe1d560SDave Jiang u64 engines; 291bfe1d560SDave Jiang union group_flags flags; 292bfe1d560SDave Jiang } __packed; 293bfe1d560SDave Jiang 294bfe1d560SDave Jiang union wqcfg { 295bfe1d560SDave Jiang struct { 296bfe1d560SDave Jiang /* bytes 0-3 */ 297bfe1d560SDave Jiang u16 wq_size; 298bfe1d560SDave Jiang u16 rsvd; 299bfe1d560SDave Jiang 300bfe1d560SDave Jiang /* bytes 4-7 */ 301bfe1d560SDave Jiang u16 wq_thresh; 302bfe1d560SDave Jiang u16 rsvd1; 303bfe1d560SDave Jiang 304bfe1d560SDave Jiang /* bytes 8-11 */ 305bfe1d560SDave Jiang u32 mode:1; /* shared or dedicated */ 306bfe1d560SDave Jiang u32 bof:1; /* block on fault */ 30792de5fa2SDave Jiang u32 wq_ats_disable:1; 30892de5fa2SDave Jiang u32 rsvd2:1; 309bfe1d560SDave Jiang u32 priority:4; 310bfe1d560SDave Jiang u32 pasid:20; 311bfe1d560SDave Jiang u32 pasid_en:1; 312bfe1d560SDave Jiang u32 priv:1; 313bfe1d560SDave Jiang u32 rsvd3:2; 314bfe1d560SDave Jiang 315bfe1d560SDave Jiang /* bytes 12-15 */ 316bfe1d560SDave Jiang u32 max_xfer_shift:5; 317bfe1d560SDave Jiang u32 max_batch_shift:4; 318bfe1d560SDave Jiang u32 rsvd4:23; 319bfe1d560SDave Jiang 320bfe1d560SDave Jiang /* bytes 16-19 */ 321bfe1d560SDave Jiang u16 occupancy_inth; 322bfe1d560SDave Jiang u16 occupancy_table_sel:1; 323bfe1d560SDave Jiang u16 rsvd5:15; 324bfe1d560SDave Jiang 325bfe1d560SDave Jiang /* bytes 20-23 */ 326bfe1d560SDave Jiang u16 occupancy_limit; 327bfe1d560SDave Jiang u16 occupancy_int_en:1; 328bfe1d560SDave Jiang u16 rsvd6:15; 329bfe1d560SDave Jiang 330bfe1d560SDave Jiang /* bytes 24-27 */ 331bfe1d560SDave Jiang u16 occupancy; 332bfe1d560SDave Jiang u16 occupancy_int:1; 333bfe1d560SDave Jiang u16 rsvd7:12; 334bfe1d560SDave Jiang u16 mode_support:1; 335bfe1d560SDave Jiang u16 wq_state:2; 336bfe1d560SDave Jiang 337bfe1d560SDave Jiang /* bytes 28-31 */ 338bfe1d560SDave Jiang u32 rsvd8; 339bfe1d560SDave Jiang }; 340bfe1d560SDave Jiang u32 bits[8]; 341bfe1d560SDave Jiang } __packed; 342d98793b5SDave Jiang 3438e50d392SDave Jiang #define WQCFG_PASID_IDX 2 3448e50d392SDave Jiang 345d98793b5SDave Jiang /* 346d98793b5SDave Jiang * This macro calculates the offset into the WQCFG register 347d98793b5SDave Jiang * idxd - struct idxd * 348d98793b5SDave Jiang * n - wq id 349d98793b5SDave Jiang * ofs - the index of the 32b dword for the config register 350d98793b5SDave Jiang * 351d98793b5SDave Jiang * The WQCFG register block is divided into groups per each wq. The n index 352d98793b5SDave Jiang * allows us to move to the register group that's for that particular wq. 353d98793b5SDave Jiang * Each register is 32bits. The ofs gives us the number of register to access. 354d98793b5SDave Jiang */ 355d98793b5SDave Jiang #define WQCFG_OFFSET(_idxd_dev, n, ofs) \ 356d98793b5SDave Jiang ({\ 357d98793b5SDave Jiang typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \ 358d98793b5SDave Jiang (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \ 359d98793b5SDave Jiang }) 360d98793b5SDave Jiang 361d98793b5SDave Jiang #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32)) 362d98793b5SDave Jiang 3635a712701SDave Jiang #define GRPCFG_SIZE 64 3645a712701SDave Jiang #define GRPWQCFG_STRIDES 4 3655a712701SDave Jiang 3665a712701SDave Jiang /* 3675a712701SDave Jiang * This macro calculates the offset into the GRPCFG register 3685a712701SDave Jiang * idxd - struct idxd * 3695a712701SDave Jiang * n - wq id 3705a712701SDave Jiang * ofs - the index of the 32b dword for the config register 3715a712701SDave Jiang * 3725a712701SDave Jiang * The WQCFG register block is divided into groups per each wq. The n index 3735a712701SDave Jiang * allows us to move to the register group that's for that particular wq. 3745a712701SDave Jiang * Each register is 32bits. The ofs gives us the number of register to access. 3755a712701SDave Jiang */ 3765a712701SDave Jiang #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ 3775a712701SDave Jiang (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) 3785a712701SDave Jiang #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32) 3795a712701SDave Jiang #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40) 3805a712701SDave Jiang 381bfe1d560SDave Jiang #endif 382