1bfe1d560SDave Jiang /* SPDX-License-Identifier: GPL-2.0 */ 2bfe1d560SDave Jiang /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3bfe1d560SDave Jiang #ifndef _IDXD_REGISTERS_H_ 4bfe1d560SDave Jiang #define _IDXD_REGISTERS_H_ 5bfe1d560SDave Jiang 6*244da66cSDave Jiang #include <uapi/linux/idxd.h> 7*244da66cSDave Jiang 8bfe1d560SDave Jiang /* PCI Config */ 9bfe1d560SDave Jiang #define PCI_DEVICE_ID_INTEL_DSA_SPR0 0x0b25 10f25b4638SDave Jiang #define PCI_DEVICE_ID_INTEL_IAX_SPR0 0x0cfe 11bfe1d560SDave Jiang 12ade8a86bSDave Jiang #define DEVICE_VERSION_1 0x100 13ade8a86bSDave Jiang #define DEVICE_VERSION_2 0x200 14ade8a86bSDave Jiang 15bfe1d560SDave Jiang #define IDXD_MMIO_BAR 0 16bfe1d560SDave Jiang #define IDXD_WQ_BAR 2 178326be9fSDave Jiang #define IDXD_PORTAL_SIZE PAGE_SIZE 18bfe1d560SDave Jiang 19bfe1d560SDave Jiang /* MMIO Device BAR0 Registers */ 20bfe1d560SDave Jiang #define IDXD_VER_OFFSET 0x00 21bfe1d560SDave Jiang #define IDXD_VER_MAJOR_MASK 0xf0 22bfe1d560SDave Jiang #define IDXD_VER_MINOR_MASK 0x0f 23bfe1d560SDave Jiang #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4) 24bfe1d560SDave Jiang #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK) 25bfe1d560SDave Jiang 26bfe1d560SDave Jiang union gen_cap_reg { 27bfe1d560SDave Jiang struct { 28bfe1d560SDave Jiang u64 block_on_fault:1; 29bfe1d560SDave Jiang u64 overlap_copy:1; 30bfe1d560SDave Jiang u64 cache_control_mem:1; 31bfe1d560SDave Jiang u64 cache_control_cache:1; 32eb15e715SDave Jiang u64 cmd_cap:1; 33bfe1d560SDave Jiang u64 rsvd:3; 34bfe1d560SDave Jiang u64 dest_readback:1; 35bfe1d560SDave Jiang u64 drain_readback:1; 361649091fSDave Jiang u64 rsvd2:3; 371649091fSDave Jiang u64 evl_support:2; 381649091fSDave Jiang u64 rsvd4:1; 39bfe1d560SDave Jiang u64 max_xfer_shift:5; 40bfe1d560SDave Jiang u64 max_batch_shift:4; 41bfe1d560SDave Jiang u64 max_ims_mult:6; 42bfe1d560SDave Jiang u64 config_en:1; 43c5b64b68SDave Jiang u64 rsvd3:32; 44bfe1d560SDave Jiang }; 45bfe1d560SDave Jiang u64 bits; 46bfe1d560SDave Jiang } __packed; 47bfe1d560SDave Jiang #define IDXD_GENCAP_OFFSET 0x10 48bfe1d560SDave Jiang 49bfe1d560SDave Jiang union wq_cap_reg { 50bfe1d560SDave Jiang struct { 51bfe1d560SDave Jiang u64 total_wq_size:16; 52bfe1d560SDave Jiang u64 num_wqs:8; 53484f910eSDave Jiang u64 wqcfg_size:4; 54484f910eSDave Jiang u64 rsvd:20; 55bfe1d560SDave Jiang u64 shared_mode:1; 56bfe1d560SDave Jiang u64 dedicated_mode:1; 5792de5fa2SDave Jiang u64 wq_ats_support:1; 58bfe1d560SDave Jiang u64 priority:1; 59bfe1d560SDave Jiang u64 occupancy:1; 60bfe1d560SDave Jiang u64 occupancy_int:1; 61b0325aefSDave Jiang u64 op_config:1; 62b0325aefSDave Jiang u64 rsvd3:9; 63bfe1d560SDave Jiang }; 64bfe1d560SDave Jiang u64 bits; 65bfe1d560SDave Jiang } __packed; 66bfe1d560SDave Jiang #define IDXD_WQCAP_OFFSET 0x20 67484f910eSDave Jiang #define IDXD_WQCFG_MIN 5 68bfe1d560SDave Jiang 69bfe1d560SDave Jiang union group_cap_reg { 70bfe1d560SDave Jiang struct { 71bfe1d560SDave Jiang u64 num_groups:8; 727ed6f1b8SDave Jiang u64 total_rdbufs:8; /* formerly total_tokens */ 737ed6f1b8SDave Jiang u64 rdbuf_ctrl:1; /* formerly token_en */ 747ed6f1b8SDave Jiang u64 rdbuf_limit:1; /* formerly token_limit */ 751f273752SDave Jiang u64 progress_limit:1; /* descriptor and batch descriptor */ 761f273752SDave Jiang u64 rsvd:45; 77bfe1d560SDave Jiang }; 78bfe1d560SDave Jiang u64 bits; 79bfe1d560SDave Jiang } __packed; 80bfe1d560SDave Jiang #define IDXD_GRPCAP_OFFSET 0x30 81bfe1d560SDave Jiang 82bfe1d560SDave Jiang union engine_cap_reg { 83bfe1d560SDave Jiang struct { 84bfe1d560SDave Jiang u64 num_engines:8; 85bfe1d560SDave Jiang u64 rsvd:56; 86bfe1d560SDave Jiang }; 87bfe1d560SDave Jiang u64 bits; 88bfe1d560SDave Jiang } __packed; 89bfe1d560SDave Jiang 90bfe1d560SDave Jiang #define IDXD_ENGCAP_OFFSET 0x38 91bfe1d560SDave Jiang 92bfe1d560SDave Jiang #define IDXD_OPCAP_NOOP 0x0001 93bfe1d560SDave Jiang #define IDXD_OPCAP_BATCH 0x0002 94bfe1d560SDave Jiang #define IDXD_OPCAP_MEMMOVE 0x0008 95bfe1d560SDave Jiang struct opcap { 96bfe1d560SDave Jiang u64 bits[4]; 97bfe1d560SDave Jiang }; 98bfe1d560SDave Jiang 99a8563a33SDave Jiang #define IDXD_MAX_OPCAP_BITS 256U 100a8563a33SDave Jiang 101bfe1d560SDave Jiang #define IDXD_OPCAP_OFFSET 0x40 102bfe1d560SDave Jiang 103bfe1d560SDave Jiang #define IDXD_TABLE_OFFSET 0x60 104bfe1d560SDave Jiang union offsets_reg { 105bfe1d560SDave Jiang struct { 106bfe1d560SDave Jiang u64 grpcfg:16; 107bfe1d560SDave Jiang u64 wqcfg:16; 108bfe1d560SDave Jiang u64 msix_perm:16; 109bfe1d560SDave Jiang u64 ims:16; 110bfe1d560SDave Jiang u64 perfmon:16; 111bfe1d560SDave Jiang u64 rsvd:48; 112bfe1d560SDave Jiang }; 113bfe1d560SDave Jiang u64 bits[2]; 114bfe1d560SDave Jiang } __packed; 115bfe1d560SDave Jiang 1162f8417a9SDave Jiang #define IDXD_TABLE_MULT 0x100 1172f8417a9SDave Jiang 118bfe1d560SDave Jiang #define IDXD_GENCFG_OFFSET 0x80 119bfe1d560SDave Jiang union gencfg_reg { 120bfe1d560SDave Jiang struct { 1217ed6f1b8SDave Jiang u32 rdbuf_limit:8; 122bfe1d560SDave Jiang u32 rsvd:4; 123bfe1d560SDave Jiang u32 user_int_en:1; 124*244da66cSDave Jiang u32 evl_en:1; 125*244da66cSDave Jiang u32 rsvd2:18; 126bfe1d560SDave Jiang }; 127bfe1d560SDave Jiang u32 bits; 128bfe1d560SDave Jiang } __packed; 129bfe1d560SDave Jiang 130bfe1d560SDave Jiang #define IDXD_GENCTRL_OFFSET 0x88 131bfe1d560SDave Jiang union genctrl_reg { 132bfe1d560SDave Jiang struct { 133bfe1d560SDave Jiang u32 softerr_int_en:1; 1345b0c68c4SDave Jiang u32 halt_int_en:1; 135*244da66cSDave Jiang u32 evl_int_en:1; 136*244da66cSDave Jiang u32 rsvd:29; 137bfe1d560SDave Jiang }; 138bfe1d560SDave Jiang u32 bits; 139bfe1d560SDave Jiang } __packed; 140bfe1d560SDave Jiang 141bfe1d560SDave Jiang #define IDXD_GENSTATS_OFFSET 0x90 142bfe1d560SDave Jiang union gensts_reg { 143bfe1d560SDave Jiang struct { 144bfe1d560SDave Jiang u32 state:2; 145bfe1d560SDave Jiang u32 reset_type:2; 146bfe1d560SDave Jiang u32 rsvd:28; 147bfe1d560SDave Jiang }; 148bfe1d560SDave Jiang u32 bits; 149bfe1d560SDave Jiang } __packed; 150bfe1d560SDave Jiang 151bfe1d560SDave Jiang enum idxd_device_status_state { 152bfe1d560SDave Jiang IDXD_DEVICE_STATE_DISABLED = 0, 153bfe1d560SDave Jiang IDXD_DEVICE_STATE_ENABLED, 154bfe1d560SDave Jiang IDXD_DEVICE_STATE_DRAIN, 155bfe1d560SDave Jiang IDXD_DEVICE_STATE_HALT, 156bfe1d560SDave Jiang }; 157bfe1d560SDave Jiang 158bfe1d560SDave Jiang enum idxd_device_reset_type { 159bfe1d560SDave Jiang IDXD_DEVICE_RESET_SOFTWARE = 0, 160bfe1d560SDave Jiang IDXD_DEVICE_RESET_FLR, 161bfe1d560SDave Jiang IDXD_DEVICE_RESET_WARM, 162bfe1d560SDave Jiang IDXD_DEVICE_RESET_COLD, 163bfe1d560SDave Jiang }; 164bfe1d560SDave Jiang 165bfe1d560SDave Jiang #define IDXD_INTCAUSE_OFFSET 0x98 166bfe1d560SDave Jiang #define IDXD_INTC_ERR 0x01 167bfe1d560SDave Jiang #define IDXD_INTC_CMD 0x02 168bfe1d560SDave Jiang #define IDXD_INTC_OCCUPY 0x04 169bfe1d560SDave Jiang #define IDXD_INTC_PERFMON_OVFL 0x08 17088d97ea8SDave Jiang #define IDXD_INTC_HALT_STATE 0x10 17156fc39f5SDave Jiang #define IDXD_INTC_INT_HANDLE_REVOKED 0x80000000 172bfe1d560SDave Jiang 173bfe1d560SDave Jiang #define IDXD_CMD_OFFSET 0xa0 174bfe1d560SDave Jiang union idxd_command_reg { 175bfe1d560SDave Jiang struct { 176bfe1d560SDave Jiang u32 operand:20; 177bfe1d560SDave Jiang u32 cmd:5; 178bfe1d560SDave Jiang u32 rsvd:6; 179bfe1d560SDave Jiang u32 int_req:1; 180bfe1d560SDave Jiang }; 181bfe1d560SDave Jiang u32 bits; 182bfe1d560SDave Jiang } __packed; 183bfe1d560SDave Jiang 184bfe1d560SDave Jiang enum idxd_cmd { 185bfe1d560SDave Jiang IDXD_CMD_ENABLE_DEVICE = 1, 186bfe1d560SDave Jiang IDXD_CMD_DISABLE_DEVICE, 187bfe1d560SDave Jiang IDXD_CMD_DRAIN_ALL, 188bfe1d560SDave Jiang IDXD_CMD_ABORT_ALL, 189bfe1d560SDave Jiang IDXD_CMD_RESET_DEVICE, 190bfe1d560SDave Jiang IDXD_CMD_ENABLE_WQ, 191bfe1d560SDave Jiang IDXD_CMD_DISABLE_WQ, 192bfe1d560SDave Jiang IDXD_CMD_DRAIN_WQ, 193bfe1d560SDave Jiang IDXD_CMD_ABORT_WQ, 194bfe1d560SDave Jiang IDXD_CMD_RESET_WQ, 195bfe1d560SDave Jiang IDXD_CMD_DRAIN_PASID, 196bfe1d560SDave Jiang IDXD_CMD_ABORT_PASID, 197bfe1d560SDave Jiang IDXD_CMD_REQUEST_INT_HANDLE, 198eb15e715SDave Jiang IDXD_CMD_RELEASE_INT_HANDLE, 199bfe1d560SDave Jiang }; 200bfe1d560SDave Jiang 201eb15e715SDave Jiang #define CMD_INT_HANDLE_IMS 0x10000 202eb15e715SDave Jiang 203bfe1d560SDave Jiang #define IDXD_CMDSTS_OFFSET 0xa8 204bfe1d560SDave Jiang union cmdsts_reg { 205bfe1d560SDave Jiang struct { 206bfe1d560SDave Jiang u8 err; 207bfe1d560SDave Jiang u16 result; 208bfe1d560SDave Jiang u8 rsvd:7; 209bfe1d560SDave Jiang u8 active:1; 210bfe1d560SDave Jiang }; 211bfe1d560SDave Jiang u32 bits; 212bfe1d560SDave Jiang } __packed; 213bfe1d560SDave Jiang #define IDXD_CMDSTS_ACTIVE 0x80000000 214eb15e715SDave Jiang #define IDXD_CMDSTS_ERR_MASK 0xff 215eb15e715SDave Jiang #define IDXD_CMDSTS_RES_SHIFT 8 216bfe1d560SDave Jiang 217bfe1d560SDave Jiang enum idxd_cmdsts_err { 218bfe1d560SDave Jiang IDXD_CMDSTS_SUCCESS = 0, 219bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_CMD, 220bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_WQIDX, 221bfe1d560SDave Jiang IDXD_CMDSTS_HW_ERR, 222bfe1d560SDave Jiang /* enable device errors */ 223bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10, 224bfe1d560SDave Jiang IDXD_CMDSTS_ERR_CONFIG, 225bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BUSMASTER_EN, 226bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_INVAL, 227bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE, 228bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG, 229bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG2, 230bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG3, 231bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG4, 232bfe1d560SDave Jiang /* enable wq errors */ 233bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20, 234bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_ENABLED, 235bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE, 236bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_PRIOR, 237bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_MODE, 238bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BOF_EN, 239bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_EN, 240bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_BATCH_SIZE, 241bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_XFER_SIZE, 242bfe1d560SDave Jiang /* disable device errors */ 243bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31, 244bfe1d560SDave Jiang /* disable WQ, drain WQ, abort WQ, reset WQ */ 245bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOT_EN, 246bfe1d560SDave Jiang /* request interrupt handle */ 247bfe1d560SDave Jiang IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41, 248bfe1d560SDave Jiang IDXD_CMDSTS_ERR_NO_HANDLE, 249bfe1d560SDave Jiang }; 250bfe1d560SDave Jiang 251eb15e715SDave Jiang #define IDXD_CMDCAP_OFFSET 0xb0 252eb15e715SDave Jiang 253bfe1d560SDave Jiang #define IDXD_SWERR_OFFSET 0xc0 254bfe1d560SDave Jiang #define IDXD_SWERR_VALID 0x00000001 255bfe1d560SDave Jiang #define IDXD_SWERR_OVERFLOW 0x00000002 256bfe1d560SDave Jiang #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW) 257bfe1d560SDave Jiang union sw_err_reg { 258bfe1d560SDave Jiang struct { 259bfe1d560SDave Jiang u64 valid:1; 260bfe1d560SDave Jiang u64 overflow:1; 261bfe1d560SDave Jiang u64 desc_valid:1; 262bfe1d560SDave Jiang u64 wq_idx_valid:1; 263bfe1d560SDave Jiang u64 batch:1; 264bfe1d560SDave Jiang u64 fault_rw:1; 265bfe1d560SDave Jiang u64 priv:1; 266bfe1d560SDave Jiang u64 rsvd:1; 267bfe1d560SDave Jiang u64 error:8; 268bfe1d560SDave Jiang u64 wq_idx:8; 269bfe1d560SDave Jiang u64 rsvd2:8; 270bfe1d560SDave Jiang u64 operation:8; 271bfe1d560SDave Jiang u64 pasid:20; 272bfe1d560SDave Jiang u64 rsvd3:4; 273bfe1d560SDave Jiang 274bfe1d560SDave Jiang u64 batch_idx:16; 275bfe1d560SDave Jiang u64 rsvd4:16; 276bfe1d560SDave Jiang u64 invalid_flags:32; 277bfe1d560SDave Jiang 278bfe1d560SDave Jiang u64 fault_addr; 279bfe1d560SDave Jiang 280bfe1d560SDave Jiang u64 rsvd5; 281bfe1d560SDave Jiang }; 282bfe1d560SDave Jiang u64 bits[4]; 283bfe1d560SDave Jiang } __packed; 284bfe1d560SDave Jiang 2859f0d99b3SDave Jiang union iaa_cap_reg { 2869f0d99b3SDave Jiang struct { 2879f0d99b3SDave Jiang u64 dec_aecs_format_ver:1; 2889f0d99b3SDave Jiang u64 drop_init_bits:1; 2899f0d99b3SDave Jiang u64 chaining:1; 2909f0d99b3SDave Jiang u64 force_array_output_mod:1; 2919f0d99b3SDave Jiang u64 load_part_aecs:1; 2929f0d99b3SDave Jiang u64 comp_early_abort:1; 2939f0d99b3SDave Jiang u64 nested_comp:1; 2949f0d99b3SDave Jiang u64 diction_comp:1; 2959f0d99b3SDave Jiang u64 header_gen:1; 2969f0d99b3SDave Jiang u64 crypto_gcm:1; 2979f0d99b3SDave Jiang u64 crypto_cfb:1; 2989f0d99b3SDave Jiang u64 crypto_xts:1; 2999f0d99b3SDave Jiang u64 rsvd:52; 3009f0d99b3SDave Jiang }; 3019f0d99b3SDave Jiang u64 bits; 3029f0d99b3SDave Jiang } __packed; 3039f0d99b3SDave Jiang 3049f0d99b3SDave Jiang #define IDXD_IAACAP_OFFSET 0x180 3059f0d99b3SDave Jiang 306*244da66cSDave Jiang #define IDXD_EVLCFG_OFFSET 0xe0 307*244da66cSDave Jiang union evlcfg_reg { 308*244da66cSDave Jiang struct { 309*244da66cSDave Jiang u64 pasid_en:1; 310*244da66cSDave Jiang u64 priv:1; 311*244da66cSDave Jiang u64 rsvd:10; 312*244da66cSDave Jiang u64 base_addr:52; 313*244da66cSDave Jiang 314*244da66cSDave Jiang u64 size:16; 315*244da66cSDave Jiang u64 pasid:20; 316*244da66cSDave Jiang u64 rsvd2:28; 317*244da66cSDave Jiang }; 318*244da66cSDave Jiang u64 bits[2]; 319*244da66cSDave Jiang } __packed; 320*244da66cSDave Jiang 3211649091fSDave Jiang #define IDXD_EVL_SIZE_MIN 0x0040 3221649091fSDave Jiang #define IDXD_EVL_SIZE_MAX 0xffff 3231649091fSDave Jiang 324bfe1d560SDave Jiang union msix_perm { 325bfe1d560SDave Jiang struct { 326bfe1d560SDave Jiang u32 rsvd:2; 327bfe1d560SDave Jiang u32 ignore:1; 328bfe1d560SDave Jiang u32 pasid_en:1; 329bfe1d560SDave Jiang u32 rsvd2:8; 330bfe1d560SDave Jiang u32 pasid:20; 331bfe1d560SDave Jiang }; 332bfe1d560SDave Jiang u32 bits; 333bfe1d560SDave Jiang } __packed; 334bfe1d560SDave Jiang 335bfe1d560SDave Jiang union group_flags { 336bfe1d560SDave Jiang struct { 3371f273752SDave Jiang u64 tc_a:3; 3381f273752SDave Jiang u64 tc_b:3; 3391f273752SDave Jiang u64 rsvd:1; 3401f273752SDave Jiang u64 use_rdbuf_limit:1; 3411f273752SDave Jiang u64 rdbufs_reserved:8; 3421f273752SDave Jiang u64 rsvd2:4; 3431f273752SDave Jiang u64 rdbufs_allowed:8; 3441f273752SDave Jiang u64 rsvd3:4; 3451f273752SDave Jiang u64 desc_progress_limit:2; 3467ca68fa3SDave Jiang u64 rsvd4:2; 3477ca68fa3SDave Jiang u64 batch_progress_limit:2; 3487ca68fa3SDave Jiang u64 rsvd5:26; 349bfe1d560SDave Jiang }; 3501f273752SDave Jiang u64 bits; 351bfe1d560SDave Jiang } __packed; 352bfe1d560SDave Jiang 353bfe1d560SDave Jiang struct grpcfg { 354bfe1d560SDave Jiang u64 wqs[4]; 355bfe1d560SDave Jiang u64 engines; 356bfe1d560SDave Jiang union group_flags flags; 357bfe1d560SDave Jiang } __packed; 358bfe1d560SDave Jiang 359bfe1d560SDave Jiang union wqcfg { 360bfe1d560SDave Jiang struct { 361bfe1d560SDave Jiang /* bytes 0-3 */ 362bfe1d560SDave Jiang u16 wq_size; 363bfe1d560SDave Jiang u16 rsvd; 364bfe1d560SDave Jiang 365bfe1d560SDave Jiang /* bytes 4-7 */ 366bfe1d560SDave Jiang u16 wq_thresh; 367bfe1d560SDave Jiang u16 rsvd1; 368bfe1d560SDave Jiang 369bfe1d560SDave Jiang /* bytes 8-11 */ 370bfe1d560SDave Jiang u32 mode:1; /* shared or dedicated */ 371bfe1d560SDave Jiang u32 bof:1; /* block on fault */ 37292de5fa2SDave Jiang u32 wq_ats_disable:1; 37392de5fa2SDave Jiang u32 rsvd2:1; 374bfe1d560SDave Jiang u32 priority:4; 375bfe1d560SDave Jiang u32 pasid:20; 376bfe1d560SDave Jiang u32 pasid_en:1; 377bfe1d560SDave Jiang u32 priv:1; 378bfe1d560SDave Jiang u32 rsvd3:2; 379bfe1d560SDave Jiang 380bfe1d560SDave Jiang /* bytes 12-15 */ 381bfe1d560SDave Jiang u32 max_xfer_shift:5; 382bfe1d560SDave Jiang u32 max_batch_shift:4; 383bfe1d560SDave Jiang u32 rsvd4:23; 384bfe1d560SDave Jiang 385bfe1d560SDave Jiang /* bytes 16-19 */ 386bfe1d560SDave Jiang u16 occupancy_inth; 387bfe1d560SDave Jiang u16 occupancy_table_sel:1; 388bfe1d560SDave Jiang u16 rsvd5:15; 389bfe1d560SDave Jiang 390bfe1d560SDave Jiang /* bytes 20-23 */ 391bfe1d560SDave Jiang u16 occupancy_limit; 392bfe1d560SDave Jiang u16 occupancy_int_en:1; 393bfe1d560SDave Jiang u16 rsvd6:15; 394bfe1d560SDave Jiang 395bfe1d560SDave Jiang /* bytes 24-27 */ 396bfe1d560SDave Jiang u16 occupancy; 397bfe1d560SDave Jiang u16 occupancy_int:1; 398bfe1d560SDave Jiang u16 rsvd7:12; 399bfe1d560SDave Jiang u16 mode_support:1; 400bfe1d560SDave Jiang u16 wq_state:2; 401bfe1d560SDave Jiang 402bfe1d560SDave Jiang /* bytes 28-31 */ 403bfe1d560SDave Jiang u32 rsvd8; 404b0325aefSDave Jiang 405b0325aefSDave Jiang /* bytes 32-63 */ 406b0325aefSDave Jiang u64 op_config[4]; 407bfe1d560SDave Jiang }; 408b0325aefSDave Jiang u32 bits[16]; 409bfe1d560SDave Jiang } __packed; 410484f910eSDave Jiang 4118e50d392SDave Jiang #define WQCFG_PASID_IDX 2 4123157dd0aSDave Jiang #define WQCFG_PRIVL_IDX 2 413e753a64bSDave Jiang #define WQCFG_OCCUP_IDX 6 414e753a64bSDave Jiang 415e753a64bSDave Jiang #define WQCFG_OCCUP_MASK 0xffff 4168e50d392SDave Jiang 417484f910eSDave Jiang /* 418484f910eSDave Jiang * This macro calculates the offset into the WQCFG register 419484f910eSDave Jiang * idxd - struct idxd * 420484f910eSDave Jiang * n - wq id 421484f910eSDave Jiang * ofs - the index of the 32b dword for the config register 422484f910eSDave Jiang * 423484f910eSDave Jiang * The WQCFG register block is divided into groups per each wq. The n index 424484f910eSDave Jiang * allows us to move to the register group that's for that particular wq. 425484f910eSDave Jiang * Each register is 32bits. The ofs gives us the number of register to access. 426484f910eSDave Jiang */ 427484f910eSDave Jiang #define WQCFG_OFFSET(_idxd_dev, n, ofs) \ 428484f910eSDave Jiang ({\ 429484f910eSDave Jiang typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \ 430484f910eSDave Jiang (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \ 431484f910eSDave Jiang }) 432484f910eSDave Jiang 433484f910eSDave Jiang #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32)) 434484f910eSDave Jiang 4355a712701SDave Jiang #define GRPCFG_SIZE 64 4365a712701SDave Jiang #define GRPWQCFG_STRIDES 4 4375a712701SDave Jiang 4385a712701SDave Jiang /* 4395a712701SDave Jiang * This macro calculates the offset into the GRPCFG register 4405a712701SDave Jiang * idxd - struct idxd * 4415a712701SDave Jiang * n - wq id 4425a712701SDave Jiang * ofs - the index of the 32b dword for the config register 4435a712701SDave Jiang * 4445a712701SDave Jiang * The WQCFG register block is divided into groups per each wq. The n index 4455a712701SDave Jiang * allows us to move to the register group that's for that particular wq. 4465a712701SDave Jiang * Each register is 32bits. The ofs gives us the number of register to access. 4475a712701SDave Jiang */ 4485a712701SDave Jiang #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ 4495a712701SDave Jiang (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) 4505a712701SDave Jiang #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32) 4515a712701SDave Jiang #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40) 4525a712701SDave Jiang 45381dd4d4dSTom Zanussi /* Following is performance monitor registers */ 45481dd4d4dSTom Zanussi #define IDXD_PERFCAP_OFFSET 0x0 45581dd4d4dSTom Zanussi union idxd_perfcap { 45681dd4d4dSTom Zanussi struct { 45781dd4d4dSTom Zanussi u64 num_perf_counter:6; 45881dd4d4dSTom Zanussi u64 rsvd1:2; 45981dd4d4dSTom Zanussi u64 counter_width:8; 46081dd4d4dSTom Zanussi u64 num_event_category:4; 46181dd4d4dSTom Zanussi u64 global_event_category:16; 46281dd4d4dSTom Zanussi u64 filter:8; 46381dd4d4dSTom Zanussi u64 rsvd2:8; 46481dd4d4dSTom Zanussi u64 cap_per_counter:1; 46581dd4d4dSTom Zanussi u64 writeable_counter:1; 46681dd4d4dSTom Zanussi u64 counter_freeze:1; 46781dd4d4dSTom Zanussi u64 overflow_interrupt:1; 46881dd4d4dSTom Zanussi u64 rsvd3:8; 46981dd4d4dSTom Zanussi }; 47081dd4d4dSTom Zanussi u64 bits; 47181dd4d4dSTom Zanussi } __packed; 47281dd4d4dSTom Zanussi 47381dd4d4dSTom Zanussi #define IDXD_EVNTCAP_OFFSET 0x80 47481dd4d4dSTom Zanussi union idxd_evntcap { 47581dd4d4dSTom Zanussi struct { 47681dd4d4dSTom Zanussi u64 events:28; 47781dd4d4dSTom Zanussi u64 rsvd:36; 47881dd4d4dSTom Zanussi }; 47981dd4d4dSTom Zanussi u64 bits; 48081dd4d4dSTom Zanussi } __packed; 48181dd4d4dSTom Zanussi 48281dd4d4dSTom Zanussi struct idxd_event { 48381dd4d4dSTom Zanussi union { 48481dd4d4dSTom Zanussi struct { 48581dd4d4dSTom Zanussi u32 event_category:4; 48681dd4d4dSTom Zanussi u32 events:28; 48781dd4d4dSTom Zanussi }; 48881dd4d4dSTom Zanussi u32 val; 48981dd4d4dSTom Zanussi }; 49081dd4d4dSTom Zanussi } __packed; 49181dd4d4dSTom Zanussi 49281dd4d4dSTom Zanussi #define IDXD_CNTRCAP_OFFSET 0x800 49381dd4d4dSTom Zanussi struct idxd_cntrcap { 49481dd4d4dSTom Zanussi union { 49581dd4d4dSTom Zanussi struct { 49681dd4d4dSTom Zanussi u32 counter_width:8; 49781dd4d4dSTom Zanussi u32 rsvd:20; 49881dd4d4dSTom Zanussi u32 num_events:4; 49981dd4d4dSTom Zanussi }; 50081dd4d4dSTom Zanussi u32 val; 50181dd4d4dSTom Zanussi }; 50281dd4d4dSTom Zanussi struct idxd_event events[]; 50381dd4d4dSTom Zanussi } __packed; 50481dd4d4dSTom Zanussi 50581dd4d4dSTom Zanussi #define IDXD_PERFRST_OFFSET 0x10 50681dd4d4dSTom Zanussi union idxd_perfrst { 50781dd4d4dSTom Zanussi struct { 50881dd4d4dSTom Zanussi u32 perfrst_config:1; 50981dd4d4dSTom Zanussi u32 perfrst_counter:1; 51081dd4d4dSTom Zanussi u32 rsvd:30; 51181dd4d4dSTom Zanussi }; 51281dd4d4dSTom Zanussi u32 val; 51381dd4d4dSTom Zanussi } __packed; 51481dd4d4dSTom Zanussi 51581dd4d4dSTom Zanussi #define IDXD_OVFSTATUS_OFFSET 0x30 51681dd4d4dSTom Zanussi #define IDXD_PERFFRZ_OFFSET 0x20 51781dd4d4dSTom Zanussi #define IDXD_CNTRCFG_OFFSET 0x100 51881dd4d4dSTom Zanussi union idxd_cntrcfg { 51981dd4d4dSTom Zanussi struct { 52081dd4d4dSTom Zanussi u64 enable:1; 52181dd4d4dSTom Zanussi u64 interrupt_ovf:1; 52281dd4d4dSTom Zanussi u64 global_freeze_ovf:1; 52381dd4d4dSTom Zanussi u64 rsvd1:5; 52481dd4d4dSTom Zanussi u64 event_category:4; 52581dd4d4dSTom Zanussi u64 rsvd2:20; 52681dd4d4dSTom Zanussi u64 events:28; 52781dd4d4dSTom Zanussi u64 rsvd3:4; 52881dd4d4dSTom Zanussi }; 52981dd4d4dSTom Zanussi u64 val; 53081dd4d4dSTom Zanussi } __packed; 53181dd4d4dSTom Zanussi 53281dd4d4dSTom Zanussi #define IDXD_FLTCFG_OFFSET 0x300 53381dd4d4dSTom Zanussi 53481dd4d4dSTom Zanussi #define IDXD_CNTRDATA_OFFSET 0x200 53581dd4d4dSTom Zanussi union idxd_cntrdata { 53681dd4d4dSTom Zanussi struct { 53781dd4d4dSTom Zanussi u64 event_count_value; 53881dd4d4dSTom Zanussi }; 53981dd4d4dSTom Zanussi u64 val; 54081dd4d4dSTom Zanussi } __packed; 54181dd4d4dSTom Zanussi 54281dd4d4dSTom Zanussi union event_cfg { 54381dd4d4dSTom Zanussi struct { 54481dd4d4dSTom Zanussi u64 event_cat:4; 54581dd4d4dSTom Zanussi u64 event_enc:28; 54681dd4d4dSTom Zanussi }; 54781dd4d4dSTom Zanussi u64 val; 54881dd4d4dSTom Zanussi } __packed; 54981dd4d4dSTom Zanussi 55081dd4d4dSTom Zanussi union filter_cfg { 55181dd4d4dSTom Zanussi struct { 55281dd4d4dSTom Zanussi u64 wq:32; 55381dd4d4dSTom Zanussi u64 tc:8; 55481dd4d4dSTom Zanussi u64 pg_sz:4; 55581dd4d4dSTom Zanussi u64 xfer_sz:8; 55681dd4d4dSTom Zanussi u64 eng:8; 55781dd4d4dSTom Zanussi }; 55881dd4d4dSTom Zanussi u64 val; 55981dd4d4dSTom Zanussi } __packed; 56081dd4d4dSTom Zanussi 561*244da66cSDave Jiang struct __evl_entry { 562*244da66cSDave Jiang u64 rsvd:2; 563*244da66cSDave Jiang u64 desc_valid:1; 564*244da66cSDave Jiang u64 wq_idx_valid:1; 565*244da66cSDave Jiang u64 batch:1; 566*244da66cSDave Jiang u64 fault_rw:1; 567*244da66cSDave Jiang u64 priv:1; 568*244da66cSDave Jiang u64 err_info_valid:1; 569*244da66cSDave Jiang u64 error:8; 570*244da66cSDave Jiang u64 wq_idx:8; 571*244da66cSDave Jiang u64 batch_id:8; 572*244da66cSDave Jiang u64 operation:8; 573*244da66cSDave Jiang u64 pasid:20; 574*244da66cSDave Jiang u64 rsvd2:4; 575*244da66cSDave Jiang 576*244da66cSDave Jiang u16 batch_idx; 577*244da66cSDave Jiang u16 rsvd3; 578*244da66cSDave Jiang union { 579*244da66cSDave Jiang /* Invalid Flags 0x11 */ 580*244da66cSDave Jiang u32 invalid_flags; 581*244da66cSDave Jiang /* Invalid Int Handle 0x19 */ 582*244da66cSDave Jiang /* Page fault 0x1a */ 583*244da66cSDave Jiang /* Page fault 0x06, 0x1f, only operand_id */ 584*244da66cSDave Jiang /* Page fault before drain or in batch, 0x26, 0x27 */ 585*244da66cSDave Jiang struct { 586*244da66cSDave Jiang u16 int_handle; 587*244da66cSDave Jiang u16 rci:1; 588*244da66cSDave Jiang u16 ims:1; 589*244da66cSDave Jiang u16 rcr:1; 590*244da66cSDave Jiang u16 first_err_in_batch:1; 591*244da66cSDave Jiang u16 rsvd4_2:9; 592*244da66cSDave Jiang u16 operand_id:3; 593*244da66cSDave Jiang }; 594*244da66cSDave Jiang }; 595*244da66cSDave Jiang u64 fault_addr; 596*244da66cSDave Jiang u64 rsvd5; 597*244da66cSDave Jiang } __packed; 598*244da66cSDave Jiang 599*244da66cSDave Jiang struct dsa_evl_entry { 600*244da66cSDave Jiang struct __evl_entry e; 601*244da66cSDave Jiang struct dsa_completion_record cr; 602*244da66cSDave Jiang } __packed; 603*244da66cSDave Jiang 604*244da66cSDave Jiang struct iax_evl_entry { 605*244da66cSDave Jiang struct __evl_entry e; 606*244da66cSDave Jiang u64 rsvd[4]; 607*244da66cSDave Jiang struct iax_completion_record cr; 608*244da66cSDave Jiang } __packed; 609*244da66cSDave Jiang 610bfe1d560SDave Jiang #endif 611