1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <uapi/linux/idxd.h> 10 #include "../dmaengine.h" 11 #include "idxd.h" 12 #include "registers.h" 13 14 enum irq_work_type { 15 IRQ_WORK_NORMAL = 0, 16 IRQ_WORK_PROCESS_FAULT, 17 }; 18 19 struct idxd_fault { 20 struct work_struct work; 21 u64 addr; 22 struct idxd_device *idxd; 23 }; 24 25 static int irq_process_work_list(struct idxd_irq_entry *irq_entry, 26 enum irq_work_type wtype, 27 int *processed, u64 data); 28 static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, 29 enum irq_work_type wtype, 30 int *processed, u64 data); 31 32 static void idxd_device_reinit(struct work_struct *work) 33 { 34 struct idxd_device *idxd = container_of(work, struct idxd_device, work); 35 struct device *dev = &idxd->pdev->dev; 36 int rc, i; 37 38 idxd_device_reset(idxd); 39 rc = idxd_device_config(idxd); 40 if (rc < 0) 41 goto out; 42 43 rc = idxd_device_enable(idxd); 44 if (rc < 0) 45 goto out; 46 47 for (i = 0; i < idxd->max_wqs; i++) { 48 struct idxd_wq *wq = &idxd->wqs[i]; 49 50 if (wq->state == IDXD_WQ_ENABLED) { 51 rc = idxd_wq_enable(wq); 52 if (rc < 0) { 53 dev_warn(dev, "Unable to re-enable wq %s\n", 54 dev_name(&wq->conf_dev)); 55 } 56 } 57 } 58 59 return; 60 61 out: 62 idxd_device_wqs_clear_state(idxd); 63 } 64 65 static void idxd_device_fault_work(struct work_struct *work) 66 { 67 struct idxd_fault *fault = container_of(work, struct idxd_fault, work); 68 struct idxd_irq_entry *ie; 69 int i; 70 int processed; 71 int irqcnt = fault->idxd->num_wq_irqs + 1; 72 73 for (i = 1; i < irqcnt; i++) { 74 ie = &fault->idxd->irq_entries[i]; 75 irq_process_work_list(ie, IRQ_WORK_PROCESS_FAULT, 76 &processed, fault->addr); 77 if (processed) 78 break; 79 80 irq_process_pending_llist(ie, IRQ_WORK_PROCESS_FAULT, 81 &processed, fault->addr); 82 if (processed) 83 break; 84 } 85 86 kfree(fault); 87 } 88 89 static int idxd_device_schedule_fault_process(struct idxd_device *idxd, 90 u64 fault_addr) 91 { 92 struct idxd_fault *fault; 93 94 fault = kmalloc(sizeof(*fault), GFP_ATOMIC); 95 if (!fault) 96 return -ENOMEM; 97 98 fault->addr = fault_addr; 99 fault->idxd = idxd; 100 INIT_WORK(&fault->work, idxd_device_fault_work); 101 queue_work(idxd->wq, &fault->work); 102 return 0; 103 } 104 105 irqreturn_t idxd_irq_handler(int vec, void *data) 106 { 107 struct idxd_irq_entry *irq_entry = data; 108 struct idxd_device *idxd = irq_entry->idxd; 109 110 idxd_mask_msix_vector(idxd, irq_entry->id); 111 return IRQ_WAKE_THREAD; 112 } 113 114 static int process_misc_interrupts(struct idxd_device *idxd, u32 cause) 115 { 116 struct device *dev = &idxd->pdev->dev; 117 union gensts_reg gensts; 118 u32 val = 0; 119 int i; 120 bool err = false; 121 122 if (cause & IDXD_INTC_ERR) { 123 spin_lock_bh(&idxd->dev_lock); 124 for (i = 0; i < 4; i++) 125 idxd->sw_err.bits[i] = ioread64(idxd->reg_base + 126 IDXD_SWERR_OFFSET + i * sizeof(u64)); 127 iowrite64(IDXD_SWERR_ACK, idxd->reg_base + IDXD_SWERR_OFFSET); 128 129 if (idxd->sw_err.valid && idxd->sw_err.wq_idx_valid) { 130 int id = idxd->sw_err.wq_idx; 131 struct idxd_wq *wq = &idxd->wqs[id]; 132 133 if (wq->type == IDXD_WQT_USER) 134 wake_up_interruptible(&wq->idxd_cdev.err_queue); 135 } else { 136 int i; 137 138 for (i = 0; i < idxd->max_wqs; i++) { 139 struct idxd_wq *wq = &idxd->wqs[i]; 140 141 if (wq->type == IDXD_WQT_USER) 142 wake_up_interruptible(&wq->idxd_cdev.err_queue); 143 } 144 } 145 146 spin_unlock_bh(&idxd->dev_lock); 147 val |= IDXD_INTC_ERR; 148 149 for (i = 0; i < 4; i++) 150 dev_warn(dev, "err[%d]: %#16.16llx\n", 151 i, idxd->sw_err.bits[i]); 152 err = true; 153 } 154 155 if (cause & IDXD_INTC_CMD) { 156 val |= IDXD_INTC_CMD; 157 complete(idxd->cmd_done); 158 } 159 160 if (cause & IDXD_INTC_OCCUPY) { 161 /* Driver does not utilize occupancy interrupt */ 162 val |= IDXD_INTC_OCCUPY; 163 } 164 165 if (cause & IDXD_INTC_PERFMON_OVFL) { 166 /* 167 * Driver does not utilize perfmon counter overflow interrupt 168 * yet. 169 */ 170 val |= IDXD_INTC_PERFMON_OVFL; 171 } 172 173 val ^= cause; 174 if (val) 175 dev_warn_once(dev, "Unexpected interrupt cause bits set: %#x\n", 176 val); 177 178 if (!err) 179 return 0; 180 181 /* 182 * This case should rarely happen and typically is due to software 183 * programming error by the driver. 184 */ 185 if (idxd->sw_err.valid && 186 idxd->sw_err.desc_valid && 187 idxd->sw_err.fault_addr) 188 idxd_device_schedule_fault_process(idxd, idxd->sw_err.fault_addr); 189 190 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 191 if (gensts.state == IDXD_DEVICE_STATE_HALT) { 192 idxd->state = IDXD_DEV_HALTED; 193 if (gensts.reset_type == IDXD_DEVICE_RESET_SOFTWARE) { 194 /* 195 * If we need a software reset, we will throw the work 196 * on a system workqueue in order to allow interrupts 197 * for the device command completions. 198 */ 199 INIT_WORK(&idxd->work, idxd_device_reinit); 200 queue_work(idxd->wq, &idxd->work); 201 } else { 202 spin_lock_bh(&idxd->dev_lock); 203 idxd_device_wqs_clear_state(idxd); 204 dev_err(&idxd->pdev->dev, 205 "idxd halted, need %s.\n", 206 gensts.reset_type == IDXD_DEVICE_RESET_FLR ? 207 "FLR" : "system reset"); 208 spin_unlock_bh(&idxd->dev_lock); 209 return -ENXIO; 210 } 211 } 212 213 return 0; 214 } 215 216 irqreturn_t idxd_misc_thread(int vec, void *data) 217 { 218 struct idxd_irq_entry *irq_entry = data; 219 struct idxd_device *idxd = irq_entry->idxd; 220 int rc; 221 u32 cause; 222 223 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET); 224 if (cause) 225 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); 226 227 while (cause) { 228 rc = process_misc_interrupts(idxd, cause); 229 if (rc < 0) 230 break; 231 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET); 232 if (cause) 233 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); 234 } 235 236 idxd_unmask_msix_vector(idxd, irq_entry->id); 237 return IRQ_HANDLED; 238 } 239 240 static inline bool match_fault(struct idxd_desc *desc, u64 fault_addr) 241 { 242 /* 243 * Completion address can be bad as well. Check fault address match for descriptor 244 * and completion address. 245 */ 246 if ((u64)desc->hw == fault_addr || (u64)desc->completion == fault_addr) { 247 struct idxd_device *idxd = desc->wq->idxd; 248 struct device *dev = &idxd->pdev->dev; 249 250 dev_warn(dev, "desc with fault address: %#llx\n", fault_addr); 251 return true; 252 } 253 254 return false; 255 } 256 257 static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason) 258 { 259 idxd_dma_complete_txd(desc, reason); 260 idxd_free_desc(desc->wq, desc); 261 } 262 263 static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, 264 enum irq_work_type wtype, 265 int *processed, u64 data) 266 { 267 struct idxd_desc *desc, *t; 268 struct llist_node *head; 269 int queued = 0; 270 unsigned long flags; 271 enum idxd_complete_type reason; 272 273 *processed = 0; 274 head = llist_del_all(&irq_entry->pending_llist); 275 if (!head) 276 goto out; 277 278 if (wtype == IRQ_WORK_NORMAL) 279 reason = IDXD_COMPLETE_NORMAL; 280 else 281 reason = IDXD_COMPLETE_DEV_FAIL; 282 283 llist_for_each_entry_safe(desc, t, head, llnode) { 284 if (desc->completion->status) { 285 if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS) 286 match_fault(desc, data); 287 complete_desc(desc, reason); 288 (*processed)++; 289 } else { 290 spin_lock_irqsave(&irq_entry->list_lock, flags); 291 list_add_tail(&desc->list, 292 &irq_entry->work_list); 293 spin_unlock_irqrestore(&irq_entry->list_lock, flags); 294 queued++; 295 } 296 } 297 298 out: 299 return queued; 300 } 301 302 static int irq_process_work_list(struct idxd_irq_entry *irq_entry, 303 enum irq_work_type wtype, 304 int *processed, u64 data) 305 { 306 int queued = 0; 307 unsigned long flags; 308 LIST_HEAD(flist); 309 struct idxd_desc *desc, *n; 310 enum idxd_complete_type reason; 311 312 *processed = 0; 313 if (wtype == IRQ_WORK_NORMAL) 314 reason = IDXD_COMPLETE_NORMAL; 315 else 316 reason = IDXD_COMPLETE_DEV_FAIL; 317 318 /* 319 * This lock protects list corruption from access of list outside of the irq handler 320 * thread. 321 */ 322 spin_lock_irqsave(&irq_entry->list_lock, flags); 323 if (list_empty(&irq_entry->work_list)) { 324 spin_unlock_irqrestore(&irq_entry->list_lock, flags); 325 return 0; 326 } 327 328 list_for_each_entry_safe(desc, n, &irq_entry->work_list, list) { 329 if (desc->completion->status) { 330 list_del(&desc->list); 331 (*processed)++; 332 list_add_tail(&desc->list, &flist); 333 } else { 334 queued++; 335 } 336 } 337 338 spin_unlock_irqrestore(&irq_entry->list_lock, flags); 339 340 list_for_each_entry(desc, &flist, list) { 341 if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS) 342 match_fault(desc, data); 343 complete_desc(desc, reason); 344 } 345 346 return queued; 347 } 348 349 static int idxd_desc_process(struct idxd_irq_entry *irq_entry) 350 { 351 int rc, processed, total = 0; 352 353 /* 354 * There are two lists we are processing. The pending_llist is where 355 * submmiter adds all the submitted descriptor after sending it to 356 * the workqueue. It's a lockless singly linked list. The work_list 357 * is the common linux double linked list. We are in a scenario of 358 * multiple producers and a single consumer. The producers are all 359 * the kernel submitters of descriptors, and the consumer is the 360 * kernel irq handler thread for the msix vector when using threaded 361 * irq. To work with the restrictions of llist to remain lockless, 362 * we are doing the following steps: 363 * 1. Iterate through the work_list and process any completed 364 * descriptor. Delete the completed entries during iteration. 365 * 2. llist_del_all() from the pending list. 366 * 3. Iterate through the llist that was deleted from the pending list 367 * and process the completed entries. 368 * 4. If the entry is still waiting on hardware, list_add_tail() to 369 * the work_list. 370 * 5. Repeat until no more descriptors. 371 */ 372 do { 373 rc = irq_process_work_list(irq_entry, IRQ_WORK_NORMAL, 374 &processed, 0); 375 total += processed; 376 if (rc != 0) 377 continue; 378 379 rc = irq_process_pending_llist(irq_entry, IRQ_WORK_NORMAL, 380 &processed, 0); 381 total += processed; 382 } while (rc != 0); 383 384 return total; 385 } 386 387 irqreturn_t idxd_wq_thread(int irq, void *data) 388 { 389 struct idxd_irq_entry *irq_entry = data; 390 int processed; 391 392 processed = idxd_desc_process(irq_entry); 393 idxd_unmask_msix_vector(irq_entry->idxd, irq_entry->id); 394 395 if (processed == 0) 396 return IRQ_NONE; 397 398 return IRQ_HANDLED; 399 } 400