1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/fs.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/device.h> 15 #include <linux/idr.h> 16 #include <linux/iommu.h> 17 #include <uapi/linux/idxd.h> 18 #include <linux/dmaengine.h> 19 #include "../dmaengine.h" 20 #include "registers.h" 21 #include "idxd.h" 22 #include "perfmon.h" 23 24 MODULE_VERSION(IDXD_DRIVER_VERSION); 25 MODULE_LICENSE("GPL v2"); 26 MODULE_AUTHOR("Intel Corporation"); 27 MODULE_IMPORT_NS(IDXD); 28 29 static bool sva = true; 30 module_param(sva, bool, 0644); 31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 32 33 bool tc_override; 34 module_param(tc_override, bool, 0644); 35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults"); 36 37 #define DRV_NAME "idxd" 38 39 bool support_enqcmd; 40 DEFINE_IDA(idxd_ida); 41 42 static struct idxd_driver_data idxd_driver_data[] = { 43 [IDXD_TYPE_DSA] = { 44 .name_prefix = "dsa", 45 .type = IDXD_TYPE_DSA, 46 .compl_size = sizeof(struct dsa_completion_record), 47 .align = 32, 48 .dev_type = &dsa_device_type, 49 }, 50 [IDXD_TYPE_IAX] = { 51 .name_prefix = "iax", 52 .type = IDXD_TYPE_IAX, 53 .compl_size = sizeof(struct iax_completion_record), 54 .align = 64, 55 .dev_type = &iax_device_type, 56 }, 57 }; 58 59 static struct pci_device_id idxd_pci_tbl[] = { 60 /* DSA ver 1.0 platforms */ 61 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) }, 62 63 /* IAX ver 1.0 platforms */ 64 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) }, 65 { 0, } 66 }; 67 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 68 69 static int idxd_setup_interrupts(struct idxd_device *idxd) 70 { 71 struct pci_dev *pdev = idxd->pdev; 72 struct device *dev = &pdev->dev; 73 struct idxd_irq_entry *ie; 74 int i, msixcnt; 75 int rc = 0; 76 77 msixcnt = pci_msix_vec_count(pdev); 78 if (msixcnt < 0) { 79 dev_err(dev, "Not MSI-X interrupt capable.\n"); 80 return -ENOSPC; 81 } 82 idxd->irq_cnt = msixcnt; 83 84 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX); 85 if (rc != msixcnt) { 86 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc); 87 return -ENOSPC; 88 } 89 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 90 91 92 ie = idxd_get_ie(idxd, 0); 93 ie->vector = pci_irq_vector(pdev, 0); 94 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie); 95 if (rc < 0) { 96 dev_err(dev, "Failed to allocate misc interrupt.\n"); 97 goto err_misc_irq; 98 } 99 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector); 100 101 for (i = 0; i < idxd->max_wqs; i++) { 102 int msix_idx = i + 1; 103 104 ie = idxd_get_ie(idxd, msix_idx); 105 ie->id = msix_idx; 106 ie->int_handle = INVALID_INT_HANDLE; 107 ie->pasid = INVALID_IOASID; 108 109 spin_lock_init(&ie->list_lock); 110 init_llist_head(&ie->pending_llist); 111 INIT_LIST_HEAD(&ie->work_list); 112 } 113 114 idxd_unmask_error_interrupts(idxd); 115 return 0; 116 117 err_misc_irq: 118 idxd_mask_error_interrupts(idxd); 119 pci_free_irq_vectors(pdev); 120 dev_err(dev, "No usable interrupts\n"); 121 return rc; 122 } 123 124 static void idxd_cleanup_interrupts(struct idxd_device *idxd) 125 { 126 struct pci_dev *pdev = idxd->pdev; 127 struct idxd_irq_entry *ie; 128 int msixcnt; 129 130 msixcnt = pci_msix_vec_count(pdev); 131 if (msixcnt <= 0) 132 return; 133 134 ie = idxd_get_ie(idxd, 0); 135 idxd_mask_error_interrupts(idxd); 136 free_irq(ie->vector, ie); 137 pci_free_irq_vectors(pdev); 138 } 139 140 static int idxd_setup_wqs(struct idxd_device *idxd) 141 { 142 struct device *dev = &idxd->pdev->dev; 143 struct idxd_wq *wq; 144 struct device *conf_dev; 145 int i, rc; 146 147 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *), 148 GFP_KERNEL, dev_to_node(dev)); 149 if (!idxd->wqs) 150 return -ENOMEM; 151 152 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev)); 153 if (!idxd->wq_enable_map) { 154 kfree(idxd->wqs); 155 return -ENOMEM; 156 } 157 158 for (i = 0; i < idxd->max_wqs; i++) { 159 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev)); 160 if (!wq) { 161 rc = -ENOMEM; 162 goto err; 163 } 164 165 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ); 166 conf_dev = wq_confdev(wq); 167 wq->id = i; 168 wq->idxd = idxd; 169 device_initialize(wq_confdev(wq)); 170 conf_dev->parent = idxd_confdev(idxd); 171 conf_dev->bus = &dsa_bus_type; 172 conf_dev->type = &idxd_wq_device_type; 173 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id); 174 if (rc < 0) { 175 put_device(conf_dev); 176 goto err; 177 } 178 179 mutex_init(&wq->wq_lock); 180 init_waitqueue_head(&wq->err_queue); 181 init_completion(&wq->wq_dead); 182 init_completion(&wq->wq_resurrect); 183 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 184 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 185 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 186 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 187 if (!wq->wqcfg) { 188 put_device(conf_dev); 189 rc = -ENOMEM; 190 goto err; 191 } 192 193 if (idxd->hw.wq_cap.op_config) { 194 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL); 195 if (!wq->opcap_bmap) { 196 put_device(conf_dev); 197 rc = -ENOMEM; 198 goto err; 199 } 200 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 201 } 202 idxd->wqs[i] = wq; 203 } 204 205 return 0; 206 207 err: 208 while (--i >= 0) { 209 wq = idxd->wqs[i]; 210 conf_dev = wq_confdev(wq); 211 put_device(conf_dev); 212 } 213 return rc; 214 } 215 216 static int idxd_setup_engines(struct idxd_device *idxd) 217 { 218 struct idxd_engine *engine; 219 struct device *dev = &idxd->pdev->dev; 220 struct device *conf_dev; 221 int i, rc; 222 223 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 224 GFP_KERNEL, dev_to_node(dev)); 225 if (!idxd->engines) 226 return -ENOMEM; 227 228 for (i = 0; i < idxd->max_engines; i++) { 229 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev)); 230 if (!engine) { 231 rc = -ENOMEM; 232 goto err; 233 } 234 235 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE); 236 conf_dev = engine_confdev(engine); 237 engine->id = i; 238 engine->idxd = idxd; 239 device_initialize(conf_dev); 240 conf_dev->parent = idxd_confdev(idxd); 241 conf_dev->bus = &dsa_bus_type; 242 conf_dev->type = &idxd_engine_device_type; 243 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id); 244 if (rc < 0) { 245 put_device(conf_dev); 246 goto err; 247 } 248 249 idxd->engines[i] = engine; 250 } 251 252 return 0; 253 254 err: 255 while (--i >= 0) { 256 engine = idxd->engines[i]; 257 conf_dev = engine_confdev(engine); 258 put_device(conf_dev); 259 } 260 return rc; 261 } 262 263 static int idxd_setup_groups(struct idxd_device *idxd) 264 { 265 struct device *dev = &idxd->pdev->dev; 266 struct device *conf_dev; 267 struct idxd_group *group; 268 int i, rc; 269 270 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *), 271 GFP_KERNEL, dev_to_node(dev)); 272 if (!idxd->groups) 273 return -ENOMEM; 274 275 for (i = 0; i < idxd->max_groups; i++) { 276 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev)); 277 if (!group) { 278 rc = -ENOMEM; 279 goto err; 280 } 281 282 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP); 283 conf_dev = group_confdev(group); 284 group->id = i; 285 group->idxd = idxd; 286 device_initialize(conf_dev); 287 conf_dev->parent = idxd_confdev(idxd); 288 conf_dev->bus = &dsa_bus_type; 289 conf_dev->type = &idxd_group_device_type; 290 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id); 291 if (rc < 0) { 292 put_device(conf_dev); 293 goto err; 294 } 295 296 idxd->groups[i] = group; 297 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 298 group->tc_a = 1; 299 group->tc_b = 1; 300 } else { 301 group->tc_a = -1; 302 group->tc_b = -1; 303 } 304 /* 305 * The default value is the same as the value of 306 * total read buffers in GRPCAP. 307 */ 308 group->rdbufs_allowed = idxd->max_rdbufs; 309 } 310 311 return 0; 312 313 err: 314 while (--i >= 0) { 315 group = idxd->groups[i]; 316 put_device(group_confdev(group)); 317 } 318 return rc; 319 } 320 321 static void idxd_cleanup_internals(struct idxd_device *idxd) 322 { 323 int i; 324 325 for (i = 0; i < idxd->max_groups; i++) 326 put_device(group_confdev(idxd->groups[i])); 327 for (i = 0; i < idxd->max_engines; i++) 328 put_device(engine_confdev(idxd->engines[i])); 329 for (i = 0; i < idxd->max_wqs; i++) 330 put_device(wq_confdev(idxd->wqs[i])); 331 destroy_workqueue(idxd->wq); 332 } 333 334 static int idxd_setup_internals(struct idxd_device *idxd) 335 { 336 struct device *dev = &idxd->pdev->dev; 337 int rc, i; 338 339 init_waitqueue_head(&idxd->cmd_waitq); 340 341 rc = idxd_setup_wqs(idxd); 342 if (rc < 0) 343 goto err_wqs; 344 345 rc = idxd_setup_engines(idxd); 346 if (rc < 0) 347 goto err_engine; 348 349 rc = idxd_setup_groups(idxd); 350 if (rc < 0) 351 goto err_group; 352 353 idxd->wq = create_workqueue(dev_name(dev)); 354 if (!idxd->wq) { 355 rc = -ENOMEM; 356 goto err_wkq_create; 357 } 358 359 return 0; 360 361 err_wkq_create: 362 for (i = 0; i < idxd->max_groups; i++) 363 put_device(group_confdev(idxd->groups[i])); 364 err_group: 365 for (i = 0; i < idxd->max_engines; i++) 366 put_device(engine_confdev(idxd->engines[i])); 367 err_engine: 368 for (i = 0; i < idxd->max_wqs; i++) 369 put_device(wq_confdev(idxd->wqs[i])); 370 err_wqs: 371 return rc; 372 } 373 374 static void idxd_read_table_offsets(struct idxd_device *idxd) 375 { 376 union offsets_reg offsets; 377 struct device *dev = &idxd->pdev->dev; 378 379 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 380 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 381 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 382 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 383 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 384 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 385 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 386 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 387 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 388 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 389 } 390 391 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count) 392 { 393 int i, j, nr; 394 395 for (i = 0, nr = 0; i < count; i++) { 396 for (j = 0; j < BITS_PER_LONG_LONG; j++) { 397 if (val[i] & BIT(j)) 398 set_bit(nr, bmap); 399 nr++; 400 } 401 } 402 } 403 404 static void idxd_read_caps(struct idxd_device *idxd) 405 { 406 struct device *dev = &idxd->pdev->dev; 407 int i; 408 409 /* reading generic capabilities */ 410 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 411 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 412 413 if (idxd->hw.gen_cap.cmd_cap) { 414 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET); 415 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap); 416 } 417 418 /* reading command capabilities */ 419 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) 420 idxd->request_int_handles = true; 421 422 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 423 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 424 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift); 425 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 426 if (idxd->hw.gen_cap.config_en) 427 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 428 429 /* reading group capabilities */ 430 idxd->hw.group_cap.bits = 431 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 432 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 433 idxd->max_groups = idxd->hw.group_cap.num_groups; 434 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 435 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs; 436 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs); 437 idxd->nr_rdbufs = idxd->max_rdbufs; 438 439 /* read engine capabilities */ 440 idxd->hw.engine_cap.bits = 441 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 442 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 443 idxd->max_engines = idxd->hw.engine_cap.num_engines; 444 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 445 446 /* read workqueue capabilities */ 447 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 448 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 449 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 450 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 451 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 452 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 453 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 454 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 455 456 /* reading operation capabilities */ 457 for (i = 0; i < 4; i++) { 458 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 459 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 460 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 461 } 462 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); 463 464 /* read iaa cap */ 465 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2) 466 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET); 467 } 468 469 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data) 470 { 471 struct device *dev = &pdev->dev; 472 struct device *conf_dev; 473 struct idxd_device *idxd; 474 int rc; 475 476 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev)); 477 if (!idxd) 478 return NULL; 479 480 conf_dev = idxd_confdev(idxd); 481 idxd->pdev = pdev; 482 idxd->data = data; 483 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type); 484 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL); 485 if (idxd->id < 0) 486 return NULL; 487 488 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev)); 489 if (!idxd->opcap_bmap) { 490 ida_free(&idxd_ida, idxd->id); 491 return NULL; 492 } 493 494 device_initialize(conf_dev); 495 conf_dev->parent = dev; 496 conf_dev->bus = &dsa_bus_type; 497 conf_dev->type = idxd->data->dev_type; 498 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id); 499 if (rc < 0) { 500 put_device(conf_dev); 501 return NULL; 502 } 503 504 spin_lock_init(&idxd->dev_lock); 505 spin_lock_init(&idxd->cmd_lock); 506 507 return idxd; 508 } 509 510 static int idxd_enable_system_pasid(struct idxd_device *idxd) 511 { 512 return -EOPNOTSUPP; 513 } 514 515 static void idxd_disable_system_pasid(struct idxd_device *idxd) 516 { 517 518 iommu_sva_unbind_device(idxd->sva); 519 idxd->sva = NULL; 520 } 521 522 static int idxd_probe(struct idxd_device *idxd) 523 { 524 struct pci_dev *pdev = idxd->pdev; 525 struct device *dev = &pdev->dev; 526 int rc; 527 528 dev_dbg(dev, "%s entered and resetting device\n", __func__); 529 rc = idxd_device_init_reset(idxd); 530 if (rc < 0) 531 return rc; 532 533 dev_dbg(dev, "IDXD reset complete\n"); 534 535 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 536 if (iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA)) { 537 dev_warn(dev, "Unable to turn on user SVA feature.\n"); 538 } else { 539 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags); 540 541 if (idxd_enable_system_pasid(idxd)) 542 dev_warn(dev, "No in-kernel DMA with PASID.\n"); 543 else 544 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 545 } 546 } else if (!sva) { 547 dev_warn(dev, "User forced SVA off via module param.\n"); 548 } 549 550 idxd_read_caps(idxd); 551 idxd_read_table_offsets(idxd); 552 553 rc = idxd_setup_internals(idxd); 554 if (rc) 555 goto err; 556 557 /* If the configs are readonly, then load them from device */ 558 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 559 dev_dbg(dev, "Loading RO device config\n"); 560 rc = idxd_device_load_config(idxd); 561 if (rc < 0) 562 goto err_config; 563 } 564 565 rc = idxd_setup_interrupts(idxd); 566 if (rc) 567 goto err_config; 568 569 idxd->major = idxd_cdev_get_major(idxd); 570 571 rc = perfmon_pmu_init(idxd); 572 if (rc < 0) 573 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc); 574 575 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 576 return 0; 577 578 err_config: 579 idxd_cleanup_internals(idxd); 580 err: 581 if (device_pasid_enabled(idxd)) 582 idxd_disable_system_pasid(idxd); 583 if (device_user_pasid_enabled(idxd)) 584 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 585 return rc; 586 } 587 588 static void idxd_cleanup(struct idxd_device *idxd) 589 { 590 struct device *dev = &idxd->pdev->dev; 591 592 perfmon_pmu_remove(idxd); 593 idxd_cleanup_interrupts(idxd); 594 idxd_cleanup_internals(idxd); 595 if (device_pasid_enabled(idxd)) 596 idxd_disable_system_pasid(idxd); 597 if (device_user_pasid_enabled(idxd)) 598 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 599 } 600 601 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 602 { 603 struct device *dev = &pdev->dev; 604 struct idxd_device *idxd; 605 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data; 606 int rc; 607 608 rc = pci_enable_device(pdev); 609 if (rc) 610 return rc; 611 612 dev_dbg(dev, "Alloc IDXD context\n"); 613 idxd = idxd_alloc(pdev, data); 614 if (!idxd) { 615 rc = -ENOMEM; 616 goto err_idxd_alloc; 617 } 618 619 dev_dbg(dev, "Mapping BARs\n"); 620 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0); 621 if (!idxd->reg_base) { 622 rc = -ENOMEM; 623 goto err_iomap; 624 } 625 626 dev_dbg(dev, "Set DMA masks\n"); 627 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 628 if (rc) 629 goto err; 630 631 dev_dbg(dev, "Set PCI master\n"); 632 pci_set_master(pdev); 633 pci_set_drvdata(pdev, idxd); 634 635 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 636 rc = idxd_probe(idxd); 637 if (rc) { 638 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 639 goto err; 640 } 641 642 rc = idxd_register_devices(idxd); 643 if (rc) { 644 dev_err(dev, "IDXD sysfs setup failed\n"); 645 goto err_dev_register; 646 } 647 648 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 649 idxd->hw.version); 650 651 return 0; 652 653 err_dev_register: 654 idxd_cleanup(idxd); 655 err: 656 pci_iounmap(pdev, idxd->reg_base); 657 err_iomap: 658 put_device(idxd_confdev(idxd)); 659 err_idxd_alloc: 660 pci_disable_device(pdev); 661 return rc; 662 } 663 664 void idxd_wqs_quiesce(struct idxd_device *idxd) 665 { 666 struct idxd_wq *wq; 667 int i; 668 669 for (i = 0; i < idxd->max_wqs; i++) { 670 wq = idxd->wqs[i]; 671 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL) 672 idxd_wq_quiesce(wq); 673 } 674 } 675 676 static void idxd_shutdown(struct pci_dev *pdev) 677 { 678 struct idxd_device *idxd = pci_get_drvdata(pdev); 679 struct idxd_irq_entry *irq_entry; 680 int rc; 681 682 rc = idxd_device_disable(idxd); 683 if (rc) 684 dev_err(&pdev->dev, "Disabling device failed\n"); 685 686 irq_entry = &idxd->ie; 687 synchronize_irq(irq_entry->vector); 688 idxd_mask_error_interrupts(idxd); 689 flush_workqueue(idxd->wq); 690 } 691 692 static void idxd_remove(struct pci_dev *pdev) 693 { 694 struct idxd_device *idxd = pci_get_drvdata(pdev); 695 struct idxd_irq_entry *irq_entry; 696 697 idxd_unregister_devices(idxd); 698 /* 699 * When ->release() is called for the idxd->conf_dev, it frees all the memory related 700 * to the idxd context. The driver still needs those bits in order to do the rest of 701 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref 702 * on the device here to hold off the freeing while allowing the idxd sub-driver 703 * to unbind. 704 */ 705 get_device(idxd_confdev(idxd)); 706 device_unregister(idxd_confdev(idxd)); 707 idxd_shutdown(pdev); 708 if (device_pasid_enabled(idxd)) 709 idxd_disable_system_pasid(idxd); 710 711 irq_entry = idxd_get_ie(idxd, 0); 712 free_irq(irq_entry->vector, irq_entry); 713 pci_free_irq_vectors(pdev); 714 pci_iounmap(pdev, idxd->reg_base); 715 if (device_user_pasid_enabled(idxd)) 716 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 717 pci_disable_device(pdev); 718 destroy_workqueue(idxd->wq); 719 perfmon_pmu_remove(idxd); 720 put_device(idxd_confdev(idxd)); 721 } 722 723 static struct pci_driver idxd_pci_driver = { 724 .name = DRV_NAME, 725 .id_table = idxd_pci_tbl, 726 .probe = idxd_pci_probe, 727 .remove = idxd_remove, 728 .shutdown = idxd_shutdown, 729 }; 730 731 static int __init idxd_init_module(void) 732 { 733 int err; 734 735 /* 736 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 737 * enumerating the device. We can not utilize it. 738 */ 739 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) { 740 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 741 return -ENODEV; 742 } 743 744 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 745 pr_warn("Platform does not have ENQCMD(S) support.\n"); 746 else 747 support_enqcmd = true; 748 749 perfmon_init(); 750 751 err = idxd_driver_register(&idxd_drv); 752 if (err < 0) 753 goto err_idxd_driver_register; 754 755 err = idxd_driver_register(&idxd_dmaengine_drv); 756 if (err < 0) 757 goto err_idxd_dmaengine_driver_register; 758 759 err = idxd_driver_register(&idxd_user_drv); 760 if (err < 0) 761 goto err_idxd_user_driver_register; 762 763 err = idxd_cdev_register(); 764 if (err) 765 goto err_cdev_register; 766 767 err = pci_register_driver(&idxd_pci_driver); 768 if (err) 769 goto err_pci_register; 770 771 return 0; 772 773 err_pci_register: 774 idxd_cdev_remove(); 775 err_cdev_register: 776 idxd_driver_unregister(&idxd_user_drv); 777 err_idxd_user_driver_register: 778 idxd_driver_unregister(&idxd_dmaengine_drv); 779 err_idxd_dmaengine_driver_register: 780 idxd_driver_unregister(&idxd_drv); 781 err_idxd_driver_register: 782 return err; 783 } 784 module_init(idxd_init_module); 785 786 static void __exit idxd_exit_module(void) 787 { 788 idxd_driver_unregister(&idxd_user_drv); 789 idxd_driver_unregister(&idxd_dmaengine_drv); 790 idxd_driver_unregister(&idxd_drv); 791 pci_unregister_driver(&idxd_pci_driver); 792 idxd_cdev_remove(); 793 perfmon_exit(); 794 } 795 module_exit(idxd_exit_module); 796