1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/aer.h> 13 #include <linux/fs.h> 14 #include <linux/io-64-nonatomic-lo-hi.h> 15 #include <linux/device.h> 16 #include <linux/idr.h> 17 #include <linux/intel-svm.h> 18 #include <linux/iommu.h> 19 #include <uapi/linux/idxd.h> 20 #include <linux/dmaengine.h> 21 #include "../dmaengine.h" 22 #include "registers.h" 23 #include "idxd.h" 24 25 MODULE_VERSION(IDXD_DRIVER_VERSION); 26 MODULE_LICENSE("GPL v2"); 27 MODULE_AUTHOR("Intel Corporation"); 28 29 static bool sva = true; 30 module_param(sva, bool, 0644); 31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 32 33 #define DRV_NAME "idxd" 34 35 bool support_enqcmd; 36 37 static struct idr idxd_idrs[IDXD_TYPE_MAX]; 38 static DEFINE_MUTEX(idxd_idr_lock); 39 40 static struct pci_device_id idxd_pci_tbl[] = { 41 /* DSA ver 1.0 platforms */ 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_DSA_SPR0) }, 43 44 /* IAX ver 1.0 platforms */ 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IAX_SPR0) }, 46 { 0, } 47 }; 48 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 49 50 static char *idxd_name[] = { 51 "dsa", 52 "iax" 53 }; 54 55 const char *idxd_get_dev_name(struct idxd_device *idxd) 56 { 57 return idxd_name[idxd->type]; 58 } 59 60 static int idxd_setup_interrupts(struct idxd_device *idxd) 61 { 62 struct pci_dev *pdev = idxd->pdev; 63 struct device *dev = &pdev->dev; 64 struct msix_entry *msix; 65 struct idxd_irq_entry *irq_entry; 66 int i, msixcnt; 67 int rc = 0; 68 union msix_perm mperm; 69 70 msixcnt = pci_msix_vec_count(pdev); 71 if (msixcnt < 0) { 72 dev_err(dev, "Not MSI-X interrupt capable.\n"); 73 goto err_no_irq; 74 } 75 76 idxd->msix_entries = devm_kzalloc(dev, sizeof(struct msix_entry) * 77 msixcnt, GFP_KERNEL); 78 if (!idxd->msix_entries) { 79 rc = -ENOMEM; 80 goto err_no_irq; 81 } 82 83 for (i = 0; i < msixcnt; i++) 84 idxd->msix_entries[i].entry = i; 85 86 rc = pci_enable_msix_exact(pdev, idxd->msix_entries, msixcnt); 87 if (rc) { 88 dev_err(dev, "Failed enabling %d MSIX entries.\n", msixcnt); 89 goto err_no_irq; 90 } 91 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 92 93 /* 94 * We implement 1 completion list per MSI-X entry except for 95 * entry 0, which is for errors and others. 96 */ 97 idxd->irq_entries = devm_kcalloc(dev, msixcnt, 98 sizeof(struct idxd_irq_entry), 99 GFP_KERNEL); 100 if (!idxd->irq_entries) { 101 rc = -ENOMEM; 102 goto err_no_irq; 103 } 104 105 for (i = 0; i < msixcnt; i++) { 106 idxd->irq_entries[i].id = i; 107 idxd->irq_entries[i].idxd = idxd; 108 spin_lock_init(&idxd->irq_entries[i].list_lock); 109 } 110 111 msix = &idxd->msix_entries[0]; 112 irq_entry = &idxd->irq_entries[0]; 113 rc = devm_request_threaded_irq(dev, msix->vector, idxd_irq_handler, 114 idxd_misc_thread, 0, "idxd-misc", 115 irq_entry); 116 if (rc < 0) { 117 dev_err(dev, "Failed to allocate misc interrupt.\n"); 118 goto err_no_irq; 119 } 120 121 dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", 122 msix->vector); 123 124 /* first MSI-X entry is not for wq interrupts */ 125 idxd->num_wq_irqs = msixcnt - 1; 126 127 for (i = 1; i < msixcnt; i++) { 128 msix = &idxd->msix_entries[i]; 129 irq_entry = &idxd->irq_entries[i]; 130 131 init_llist_head(&idxd->irq_entries[i].pending_llist); 132 INIT_LIST_HEAD(&idxd->irq_entries[i].work_list); 133 rc = devm_request_threaded_irq(dev, msix->vector, 134 idxd_irq_handler, 135 idxd_wq_thread, 0, 136 "idxd-portal", irq_entry); 137 if (rc < 0) { 138 dev_err(dev, "Failed to allocate irq %d.\n", 139 msix->vector); 140 goto err_no_irq; 141 } 142 dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", 143 i, msix->vector); 144 } 145 146 idxd_unmask_error_interrupts(idxd); 147 148 /* Setup MSIX permission table */ 149 mperm.bits = 0; 150 mperm.pasid = idxd->pasid; 151 mperm.pasid_en = device_pasid_enabled(idxd); 152 for (i = 1; i < msixcnt; i++) 153 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 154 155 return 0; 156 157 err_no_irq: 158 /* Disable error interrupt generation */ 159 idxd_mask_error_interrupts(idxd); 160 pci_disable_msix(pdev); 161 dev_err(dev, "No usable interrupts\n"); 162 return rc; 163 } 164 165 static int idxd_setup_internals(struct idxd_device *idxd) 166 { 167 struct device *dev = &idxd->pdev->dev; 168 int i; 169 170 init_waitqueue_head(&idxd->cmd_waitq); 171 idxd->groups = devm_kcalloc(dev, idxd->max_groups, 172 sizeof(struct idxd_group), GFP_KERNEL); 173 if (!idxd->groups) 174 return -ENOMEM; 175 176 for (i = 0; i < idxd->max_groups; i++) { 177 idxd->groups[i].idxd = idxd; 178 idxd->groups[i].id = i; 179 idxd->groups[i].tc_a = -1; 180 idxd->groups[i].tc_b = -1; 181 } 182 183 idxd->wqs = devm_kcalloc(dev, idxd->max_wqs, sizeof(struct idxd_wq), 184 GFP_KERNEL); 185 if (!idxd->wqs) 186 return -ENOMEM; 187 188 idxd->engines = devm_kcalloc(dev, idxd->max_engines, 189 sizeof(struct idxd_engine), GFP_KERNEL); 190 if (!idxd->engines) 191 return -ENOMEM; 192 193 for (i = 0; i < idxd->max_wqs; i++) { 194 struct idxd_wq *wq = &idxd->wqs[i]; 195 196 wq->id = i; 197 wq->idxd = idxd; 198 mutex_init(&wq->wq_lock); 199 wq->idxd_cdev.minor = -1; 200 wq->max_xfer_bytes = idxd->max_xfer_bytes; 201 wq->max_batch_size = idxd->max_batch_size; 202 wq->wqcfg = devm_kzalloc(dev, idxd->wqcfg_size, GFP_KERNEL); 203 if (!wq->wqcfg) 204 return -ENOMEM; 205 } 206 207 for (i = 0; i < idxd->max_engines; i++) { 208 idxd->engines[i].idxd = idxd; 209 idxd->engines[i].id = i; 210 } 211 212 idxd->wq = create_workqueue(dev_name(dev)); 213 if (!idxd->wq) 214 return -ENOMEM; 215 216 return 0; 217 } 218 219 static void idxd_read_table_offsets(struct idxd_device *idxd) 220 { 221 union offsets_reg offsets; 222 struct device *dev = &idxd->pdev->dev; 223 224 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 225 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 226 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 227 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 228 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 229 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 230 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 231 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 232 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 233 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 234 } 235 236 static void idxd_read_caps(struct idxd_device *idxd) 237 { 238 struct device *dev = &idxd->pdev->dev; 239 int i; 240 241 /* reading generic capabilities */ 242 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 243 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 244 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 245 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 246 idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift; 247 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 248 if (idxd->hw.gen_cap.config_en) 249 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 250 251 /* reading group capabilities */ 252 idxd->hw.group_cap.bits = 253 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 254 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 255 idxd->max_groups = idxd->hw.group_cap.num_groups; 256 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 257 idxd->max_tokens = idxd->hw.group_cap.total_tokens; 258 dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens); 259 idxd->nr_tokens = idxd->max_tokens; 260 261 /* read engine capabilities */ 262 idxd->hw.engine_cap.bits = 263 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 264 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 265 idxd->max_engines = idxd->hw.engine_cap.num_engines; 266 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 267 268 /* read workqueue capabilities */ 269 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 270 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 271 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 272 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 273 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 274 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 275 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 276 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 277 278 /* reading operation capabilities */ 279 for (i = 0; i < 4; i++) { 280 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 281 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 282 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 283 } 284 } 285 286 static struct idxd_device *idxd_alloc(struct pci_dev *pdev) 287 { 288 struct device *dev = &pdev->dev; 289 struct idxd_device *idxd; 290 291 idxd = devm_kzalloc(dev, sizeof(struct idxd_device), GFP_KERNEL); 292 if (!idxd) 293 return NULL; 294 295 idxd->pdev = pdev; 296 spin_lock_init(&idxd->dev_lock); 297 298 return idxd; 299 } 300 301 static int idxd_enable_system_pasid(struct idxd_device *idxd) 302 { 303 int flags; 304 unsigned int pasid; 305 struct iommu_sva *sva; 306 307 flags = SVM_FLAG_SUPERVISOR_MODE; 308 309 sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags); 310 if (IS_ERR(sva)) { 311 dev_warn(&idxd->pdev->dev, 312 "iommu sva bind failed: %ld\n", PTR_ERR(sva)); 313 return PTR_ERR(sva); 314 } 315 316 pasid = iommu_sva_get_pasid(sva); 317 if (pasid == IOMMU_PASID_INVALID) { 318 iommu_sva_unbind_device(sva); 319 return -ENODEV; 320 } 321 322 idxd->sva = sva; 323 idxd->pasid = pasid; 324 dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid); 325 return 0; 326 } 327 328 static void idxd_disable_system_pasid(struct idxd_device *idxd) 329 { 330 331 iommu_sva_unbind_device(idxd->sva); 332 idxd->sva = NULL; 333 } 334 335 static int idxd_probe(struct idxd_device *idxd) 336 { 337 struct pci_dev *pdev = idxd->pdev; 338 struct device *dev = &pdev->dev; 339 int rc; 340 341 dev_dbg(dev, "%s entered and resetting device\n", __func__); 342 rc = idxd_device_init_reset(idxd); 343 if (rc < 0) 344 return rc; 345 346 dev_dbg(dev, "IDXD reset complete\n"); 347 348 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 349 rc = idxd_enable_system_pasid(idxd); 350 if (rc < 0) 351 dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc); 352 else 353 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 354 } else if (!sva) { 355 dev_warn(dev, "User forced SVA off via module param.\n"); 356 } 357 358 idxd_read_caps(idxd); 359 idxd_read_table_offsets(idxd); 360 361 rc = idxd_setup_internals(idxd); 362 if (rc) 363 goto err_setup; 364 365 rc = idxd_setup_interrupts(idxd); 366 if (rc) 367 goto err_setup; 368 369 dev_dbg(dev, "IDXD interrupt setup complete.\n"); 370 371 mutex_lock(&idxd_idr_lock); 372 idxd->id = idr_alloc(&idxd_idrs[idxd->type], idxd, 0, 0, GFP_KERNEL); 373 mutex_unlock(&idxd_idr_lock); 374 if (idxd->id < 0) { 375 rc = -ENOMEM; 376 goto err_idr_fail; 377 } 378 379 idxd->major = idxd_cdev_get_major(idxd); 380 381 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 382 return 0; 383 384 err_idr_fail: 385 idxd_mask_error_interrupts(idxd); 386 idxd_mask_msix_vectors(idxd); 387 err_setup: 388 if (device_pasid_enabled(idxd)) 389 idxd_disable_system_pasid(idxd); 390 return rc; 391 } 392 393 static void idxd_type_init(struct idxd_device *idxd) 394 { 395 if (idxd->type == IDXD_TYPE_DSA) 396 idxd->compl_size = sizeof(struct dsa_completion_record); 397 else if (idxd->type == IDXD_TYPE_IAX) 398 idxd->compl_size = sizeof(struct iax_completion_record); 399 } 400 401 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 402 { 403 struct device *dev = &pdev->dev; 404 struct idxd_device *idxd; 405 int rc; 406 407 rc = pcim_enable_device(pdev); 408 if (rc) 409 return rc; 410 411 dev_dbg(dev, "Alloc IDXD context\n"); 412 idxd = idxd_alloc(pdev); 413 if (!idxd) 414 return -ENOMEM; 415 416 dev_dbg(dev, "Mapping BARs\n"); 417 idxd->reg_base = pcim_iomap(pdev, IDXD_MMIO_BAR, 0); 418 if (!idxd->reg_base) 419 return -ENOMEM; 420 421 dev_dbg(dev, "Set DMA masks\n"); 422 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 423 if (rc) 424 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 425 if (rc) 426 return rc; 427 428 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 429 if (rc) 430 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 431 if (rc) 432 return rc; 433 434 idxd_set_type(idxd); 435 436 idxd_type_init(idxd); 437 438 dev_dbg(dev, "Set PCI master\n"); 439 pci_set_master(pdev); 440 pci_set_drvdata(pdev, idxd); 441 442 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 443 rc = idxd_probe(idxd); 444 if (rc) { 445 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 446 return -ENODEV; 447 } 448 449 rc = idxd_setup_sysfs(idxd); 450 if (rc) { 451 dev_err(dev, "IDXD sysfs setup failed\n"); 452 return -ENODEV; 453 } 454 455 idxd->state = IDXD_DEV_CONF_READY; 456 457 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 458 idxd->hw.version); 459 460 return 0; 461 } 462 463 static void idxd_flush_pending_llist(struct idxd_irq_entry *ie) 464 { 465 struct idxd_desc *desc, *itr; 466 struct llist_node *head; 467 468 head = llist_del_all(&ie->pending_llist); 469 if (!head) 470 return; 471 472 llist_for_each_entry_safe(desc, itr, head, llnode) { 473 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 474 idxd_free_desc(desc->wq, desc); 475 } 476 } 477 478 static void idxd_flush_work_list(struct idxd_irq_entry *ie) 479 { 480 struct idxd_desc *desc, *iter; 481 482 list_for_each_entry_safe(desc, iter, &ie->work_list, list) { 483 list_del(&desc->list); 484 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 485 idxd_free_desc(desc->wq, desc); 486 } 487 } 488 489 static void idxd_shutdown(struct pci_dev *pdev) 490 { 491 struct idxd_device *idxd = pci_get_drvdata(pdev); 492 int rc, i; 493 struct idxd_irq_entry *irq_entry; 494 int msixcnt = pci_msix_vec_count(pdev); 495 496 rc = idxd_device_disable(idxd); 497 if (rc) 498 dev_err(&pdev->dev, "Disabling device failed\n"); 499 500 dev_dbg(&pdev->dev, "%s called\n", __func__); 501 idxd_mask_msix_vectors(idxd); 502 idxd_mask_error_interrupts(idxd); 503 504 for (i = 0; i < msixcnt; i++) { 505 irq_entry = &idxd->irq_entries[i]; 506 synchronize_irq(idxd->msix_entries[i].vector); 507 if (i == 0) 508 continue; 509 idxd_flush_pending_llist(irq_entry); 510 idxd_flush_work_list(irq_entry); 511 } 512 513 destroy_workqueue(idxd->wq); 514 } 515 516 static void idxd_remove(struct pci_dev *pdev) 517 { 518 struct idxd_device *idxd = pci_get_drvdata(pdev); 519 520 dev_dbg(&pdev->dev, "%s called\n", __func__); 521 idxd_cleanup_sysfs(idxd); 522 idxd_shutdown(pdev); 523 if (device_pasid_enabled(idxd)) 524 idxd_disable_system_pasid(idxd); 525 mutex_lock(&idxd_idr_lock); 526 idr_remove(&idxd_idrs[idxd->type], idxd->id); 527 mutex_unlock(&idxd_idr_lock); 528 } 529 530 static struct pci_driver idxd_pci_driver = { 531 .name = DRV_NAME, 532 .id_table = idxd_pci_tbl, 533 .probe = idxd_pci_probe, 534 .remove = idxd_remove, 535 .shutdown = idxd_shutdown, 536 }; 537 538 static int __init idxd_init_module(void) 539 { 540 int err, i; 541 542 /* 543 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 544 * enumerating the device. We can not utilize it. 545 */ 546 if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) { 547 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 548 return -ENODEV; 549 } 550 551 if (!boot_cpu_has(X86_FEATURE_ENQCMD)) 552 pr_warn("Platform does not have ENQCMD(S) support.\n"); 553 else 554 support_enqcmd = true; 555 556 for (i = 0; i < IDXD_TYPE_MAX; i++) 557 idr_init(&idxd_idrs[i]); 558 559 err = idxd_register_bus_type(); 560 if (err < 0) 561 return err; 562 563 err = idxd_register_driver(); 564 if (err < 0) 565 goto err_idxd_driver_register; 566 567 err = idxd_cdev_register(); 568 if (err) 569 goto err_cdev_register; 570 571 err = pci_register_driver(&idxd_pci_driver); 572 if (err) 573 goto err_pci_register; 574 575 return 0; 576 577 err_pci_register: 578 idxd_cdev_remove(); 579 err_cdev_register: 580 idxd_unregister_driver(); 581 err_idxd_driver_register: 582 idxd_unregister_bus_type(); 583 return err; 584 } 585 module_init(idxd_init_module); 586 587 static void __exit idxd_exit_module(void) 588 { 589 pci_unregister_driver(&idxd_pci_driver); 590 idxd_cdev_remove(); 591 idxd_unregister_bus_type(); 592 } 593 module_exit(idxd_exit_module); 594