1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/aer.h> 13 #include <linux/fs.h> 14 #include <linux/io-64-nonatomic-lo-hi.h> 15 #include <linux/device.h> 16 #include <linux/idr.h> 17 #include <linux/intel-svm.h> 18 #include <linux/iommu.h> 19 #include <uapi/linux/idxd.h> 20 #include <linux/dmaengine.h> 21 #include "../dmaengine.h" 22 #include "registers.h" 23 #include "idxd.h" 24 25 MODULE_VERSION(IDXD_DRIVER_VERSION); 26 MODULE_LICENSE("GPL v2"); 27 MODULE_AUTHOR("Intel Corporation"); 28 29 #define DRV_NAME "idxd" 30 31 bool support_enqcmd; 32 33 static struct idr idxd_idrs[IDXD_TYPE_MAX]; 34 static struct mutex idxd_idr_lock; 35 36 static struct pci_device_id idxd_pci_tbl[] = { 37 /* DSA ver 1.0 platforms */ 38 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_DSA_SPR0) }, 39 { 0, } 40 }; 41 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 42 43 static char *idxd_name[] = { 44 "dsa", 45 }; 46 47 const char *idxd_get_dev_name(struct idxd_device *idxd) 48 { 49 return idxd_name[idxd->type]; 50 } 51 52 static int idxd_setup_interrupts(struct idxd_device *idxd) 53 { 54 struct pci_dev *pdev = idxd->pdev; 55 struct device *dev = &pdev->dev; 56 struct msix_entry *msix; 57 struct idxd_irq_entry *irq_entry; 58 int i, msixcnt; 59 int rc = 0; 60 union msix_perm mperm; 61 62 msixcnt = pci_msix_vec_count(pdev); 63 if (msixcnt < 0) { 64 dev_err(dev, "Not MSI-X interrupt capable.\n"); 65 goto err_no_irq; 66 } 67 68 idxd->msix_entries = devm_kzalloc(dev, sizeof(struct msix_entry) * 69 msixcnt, GFP_KERNEL); 70 if (!idxd->msix_entries) { 71 rc = -ENOMEM; 72 goto err_no_irq; 73 } 74 75 for (i = 0; i < msixcnt; i++) 76 idxd->msix_entries[i].entry = i; 77 78 rc = pci_enable_msix_exact(pdev, idxd->msix_entries, msixcnt); 79 if (rc) { 80 dev_err(dev, "Failed enabling %d MSIX entries.\n", msixcnt); 81 goto err_no_irq; 82 } 83 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 84 85 /* 86 * We implement 1 completion list per MSI-X entry except for 87 * entry 0, which is for errors and others. 88 */ 89 idxd->irq_entries = devm_kcalloc(dev, msixcnt, 90 sizeof(struct idxd_irq_entry), 91 GFP_KERNEL); 92 if (!idxd->irq_entries) { 93 rc = -ENOMEM; 94 goto err_no_irq; 95 } 96 97 for (i = 0; i < msixcnt; i++) { 98 idxd->irq_entries[i].id = i; 99 idxd->irq_entries[i].idxd = idxd; 100 spin_lock_init(&idxd->irq_entries[i].list_lock); 101 } 102 103 msix = &idxd->msix_entries[0]; 104 irq_entry = &idxd->irq_entries[0]; 105 rc = devm_request_threaded_irq(dev, msix->vector, idxd_irq_handler, 106 idxd_misc_thread, 0, "idxd-misc", 107 irq_entry); 108 if (rc < 0) { 109 dev_err(dev, "Failed to allocate misc interrupt.\n"); 110 goto err_no_irq; 111 } 112 113 dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", 114 msix->vector); 115 116 /* first MSI-X entry is not for wq interrupts */ 117 idxd->num_wq_irqs = msixcnt - 1; 118 119 for (i = 1; i < msixcnt; i++) { 120 msix = &idxd->msix_entries[i]; 121 irq_entry = &idxd->irq_entries[i]; 122 123 init_llist_head(&idxd->irq_entries[i].pending_llist); 124 INIT_LIST_HEAD(&idxd->irq_entries[i].work_list); 125 rc = devm_request_threaded_irq(dev, msix->vector, 126 idxd_irq_handler, 127 idxd_wq_thread, 0, 128 "idxd-portal", irq_entry); 129 if (rc < 0) { 130 dev_err(dev, "Failed to allocate irq %d.\n", 131 msix->vector); 132 goto err_no_irq; 133 } 134 dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", 135 i, msix->vector); 136 } 137 138 idxd_unmask_error_interrupts(idxd); 139 140 /* Setup MSIX permission table */ 141 mperm.bits = 0; 142 mperm.pasid = idxd->pasid; 143 mperm.pasid_en = device_pasid_enabled(idxd); 144 for (i = 1; i < msixcnt; i++) 145 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 146 147 return 0; 148 149 err_no_irq: 150 /* Disable error interrupt generation */ 151 idxd_mask_error_interrupts(idxd); 152 pci_disable_msix(pdev); 153 dev_err(dev, "No usable interrupts\n"); 154 return rc; 155 } 156 157 static int idxd_setup_internals(struct idxd_device *idxd) 158 { 159 struct device *dev = &idxd->pdev->dev; 160 int i; 161 162 init_waitqueue_head(&idxd->cmd_waitq); 163 idxd->groups = devm_kcalloc(dev, idxd->max_groups, 164 sizeof(struct idxd_group), GFP_KERNEL); 165 if (!idxd->groups) 166 return -ENOMEM; 167 168 for (i = 0; i < idxd->max_groups; i++) { 169 idxd->groups[i].idxd = idxd; 170 idxd->groups[i].id = i; 171 idxd->groups[i].tc_a = -1; 172 idxd->groups[i].tc_b = -1; 173 } 174 175 idxd->wqs = devm_kcalloc(dev, idxd->max_wqs, sizeof(struct idxd_wq), 176 GFP_KERNEL); 177 if (!idxd->wqs) 178 return -ENOMEM; 179 180 idxd->engines = devm_kcalloc(dev, idxd->max_engines, 181 sizeof(struct idxd_engine), GFP_KERNEL); 182 if (!idxd->engines) 183 return -ENOMEM; 184 185 for (i = 0; i < idxd->max_wqs; i++) { 186 struct idxd_wq *wq = &idxd->wqs[i]; 187 188 wq->id = i; 189 wq->idxd = idxd; 190 mutex_init(&wq->wq_lock); 191 wq->idxd_cdev.minor = -1; 192 wq->max_xfer_bytes = idxd->max_xfer_bytes; 193 wq->max_batch_size = idxd->max_batch_size; 194 wq->wqcfg = devm_kzalloc(dev, idxd->wqcfg_size, GFP_KERNEL); 195 if (!wq->wqcfg) 196 return -ENOMEM; 197 } 198 199 for (i = 0; i < idxd->max_engines; i++) { 200 idxd->engines[i].idxd = idxd; 201 idxd->engines[i].id = i; 202 } 203 204 idxd->wq = create_workqueue(dev_name(dev)); 205 if (!idxd->wq) 206 return -ENOMEM; 207 208 return 0; 209 } 210 211 static void idxd_read_table_offsets(struct idxd_device *idxd) 212 { 213 union offsets_reg offsets; 214 struct device *dev = &idxd->pdev->dev; 215 216 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 217 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 218 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 219 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 220 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 221 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 222 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 223 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 224 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 225 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 226 } 227 228 static void idxd_read_caps(struct idxd_device *idxd) 229 { 230 struct device *dev = &idxd->pdev->dev; 231 int i; 232 233 /* reading generic capabilities */ 234 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 235 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 236 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 237 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 238 idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift; 239 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 240 if (idxd->hw.gen_cap.config_en) 241 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 242 243 /* reading group capabilities */ 244 idxd->hw.group_cap.bits = 245 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 246 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 247 idxd->max_groups = idxd->hw.group_cap.num_groups; 248 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 249 idxd->max_tokens = idxd->hw.group_cap.total_tokens; 250 dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens); 251 idxd->nr_tokens = idxd->max_tokens; 252 253 /* read engine capabilities */ 254 idxd->hw.engine_cap.bits = 255 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 256 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 257 idxd->max_engines = idxd->hw.engine_cap.num_engines; 258 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 259 260 /* read workqueue capabilities */ 261 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 262 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 263 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 264 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 265 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 266 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 267 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 268 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 269 270 /* reading operation capabilities */ 271 for (i = 0; i < 4; i++) { 272 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 273 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 274 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 275 } 276 } 277 278 static struct idxd_device *idxd_alloc(struct pci_dev *pdev) 279 { 280 struct device *dev = &pdev->dev; 281 struct idxd_device *idxd; 282 283 idxd = devm_kzalloc(dev, sizeof(struct idxd_device), GFP_KERNEL); 284 if (!idxd) 285 return NULL; 286 287 idxd->pdev = pdev; 288 spin_lock_init(&idxd->dev_lock); 289 290 return idxd; 291 } 292 293 static int idxd_enable_system_pasid(struct idxd_device *idxd) 294 { 295 int flags; 296 unsigned int pasid; 297 struct iommu_sva *sva; 298 299 flags = SVM_FLAG_SUPERVISOR_MODE; 300 301 sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags); 302 if (IS_ERR(sva)) { 303 dev_warn(&idxd->pdev->dev, 304 "iommu sva bind failed: %ld\n", PTR_ERR(sva)); 305 return PTR_ERR(sva); 306 } 307 308 pasid = iommu_sva_get_pasid(sva); 309 if (pasid == IOMMU_PASID_INVALID) { 310 iommu_sva_unbind_device(sva); 311 return -ENODEV; 312 } 313 314 idxd->sva = sva; 315 idxd->pasid = pasid; 316 dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid); 317 return 0; 318 } 319 320 static void idxd_disable_system_pasid(struct idxd_device *idxd) 321 { 322 323 iommu_sva_unbind_device(idxd->sva); 324 idxd->sva = NULL; 325 } 326 327 static int idxd_probe(struct idxd_device *idxd) 328 { 329 struct pci_dev *pdev = idxd->pdev; 330 struct device *dev = &pdev->dev; 331 int rc; 332 333 dev_dbg(dev, "%s entered and resetting device\n", __func__); 334 idxd_device_init_reset(idxd); 335 dev_dbg(dev, "IDXD reset complete\n"); 336 337 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM)) { 338 rc = idxd_enable_system_pasid(idxd); 339 if (rc < 0) 340 dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc); 341 else 342 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 343 } 344 345 idxd_read_caps(idxd); 346 idxd_read_table_offsets(idxd); 347 348 rc = idxd_setup_internals(idxd); 349 if (rc) 350 goto err_setup; 351 352 rc = idxd_setup_interrupts(idxd); 353 if (rc) 354 goto err_setup; 355 356 dev_dbg(dev, "IDXD interrupt setup complete.\n"); 357 358 mutex_lock(&idxd_idr_lock); 359 idxd->id = idr_alloc(&idxd_idrs[idxd->type], idxd, 0, 0, GFP_KERNEL); 360 mutex_unlock(&idxd_idr_lock); 361 if (idxd->id < 0) { 362 rc = -ENOMEM; 363 goto err_idr_fail; 364 } 365 366 idxd->major = idxd_cdev_get_major(idxd); 367 368 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 369 return 0; 370 371 err_idr_fail: 372 idxd_mask_error_interrupts(idxd); 373 idxd_mask_msix_vectors(idxd); 374 err_setup: 375 if (device_pasid_enabled(idxd)) 376 idxd_disable_system_pasid(idxd); 377 return rc; 378 } 379 380 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 381 { 382 struct device *dev = &pdev->dev; 383 struct idxd_device *idxd; 384 int rc; 385 386 rc = pcim_enable_device(pdev); 387 if (rc) 388 return rc; 389 390 dev_dbg(dev, "Alloc IDXD context\n"); 391 idxd = idxd_alloc(pdev); 392 if (!idxd) 393 return -ENOMEM; 394 395 dev_dbg(dev, "Mapping BARs\n"); 396 idxd->reg_base = pcim_iomap(pdev, IDXD_MMIO_BAR, 0); 397 if (!idxd->reg_base) 398 return -ENOMEM; 399 400 dev_dbg(dev, "Set DMA masks\n"); 401 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 402 if (rc) 403 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 404 if (rc) 405 return rc; 406 407 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 408 if (rc) 409 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 410 if (rc) 411 return rc; 412 413 idxd_set_type(idxd); 414 415 dev_dbg(dev, "Set PCI master\n"); 416 pci_set_master(pdev); 417 pci_set_drvdata(pdev, idxd); 418 419 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 420 rc = idxd_probe(idxd); 421 if (rc) { 422 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 423 return -ENODEV; 424 } 425 426 rc = idxd_setup_sysfs(idxd); 427 if (rc) { 428 dev_err(dev, "IDXD sysfs setup failed\n"); 429 return -ENODEV; 430 } 431 432 idxd->state = IDXD_DEV_CONF_READY; 433 434 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 435 idxd->hw.version); 436 437 return 0; 438 } 439 440 static void idxd_flush_pending_llist(struct idxd_irq_entry *ie) 441 { 442 struct idxd_desc *desc, *itr; 443 struct llist_node *head; 444 445 head = llist_del_all(&ie->pending_llist); 446 if (!head) 447 return; 448 449 llist_for_each_entry_safe(desc, itr, head, llnode) { 450 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 451 idxd_free_desc(desc->wq, desc); 452 } 453 } 454 455 static void idxd_flush_work_list(struct idxd_irq_entry *ie) 456 { 457 struct idxd_desc *desc, *iter; 458 459 list_for_each_entry_safe(desc, iter, &ie->work_list, list) { 460 list_del(&desc->list); 461 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 462 idxd_free_desc(desc->wq, desc); 463 } 464 } 465 466 static void idxd_shutdown(struct pci_dev *pdev) 467 { 468 struct idxd_device *idxd = pci_get_drvdata(pdev); 469 int rc, i; 470 struct idxd_irq_entry *irq_entry; 471 int msixcnt = pci_msix_vec_count(pdev); 472 473 rc = idxd_device_disable(idxd); 474 if (rc) 475 dev_err(&pdev->dev, "Disabling device failed\n"); 476 477 dev_dbg(&pdev->dev, "%s called\n", __func__); 478 idxd_mask_msix_vectors(idxd); 479 idxd_mask_error_interrupts(idxd); 480 481 for (i = 0; i < msixcnt; i++) { 482 irq_entry = &idxd->irq_entries[i]; 483 synchronize_irq(idxd->msix_entries[i].vector); 484 if (i == 0) 485 continue; 486 idxd_flush_pending_llist(irq_entry); 487 idxd_flush_work_list(irq_entry); 488 } 489 490 destroy_workqueue(idxd->wq); 491 } 492 493 static void idxd_remove(struct pci_dev *pdev) 494 { 495 struct idxd_device *idxd = pci_get_drvdata(pdev); 496 497 dev_dbg(&pdev->dev, "%s called\n", __func__); 498 idxd_cleanup_sysfs(idxd); 499 idxd_shutdown(pdev); 500 if (device_pasid_enabled(idxd)) 501 idxd_disable_system_pasid(idxd); 502 mutex_lock(&idxd_idr_lock); 503 idr_remove(&idxd_idrs[idxd->type], idxd->id); 504 mutex_unlock(&idxd_idr_lock); 505 } 506 507 static struct pci_driver idxd_pci_driver = { 508 .name = DRV_NAME, 509 .id_table = idxd_pci_tbl, 510 .probe = idxd_pci_probe, 511 .remove = idxd_remove, 512 .shutdown = idxd_shutdown, 513 }; 514 515 static int __init idxd_init_module(void) 516 { 517 int err, i; 518 519 /* 520 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 521 * enumerating the device. We can not utilize it. 522 */ 523 if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) { 524 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 525 return -ENODEV; 526 } 527 528 if (!boot_cpu_has(X86_FEATURE_ENQCMD)) 529 pr_warn("Platform does not have ENQCMD(S) support.\n"); 530 else 531 support_enqcmd = true; 532 533 mutex_init(&idxd_idr_lock); 534 for (i = 0; i < IDXD_TYPE_MAX; i++) 535 idr_init(&idxd_idrs[i]); 536 537 err = idxd_register_bus_type(); 538 if (err < 0) 539 return err; 540 541 err = idxd_register_driver(); 542 if (err < 0) 543 goto err_idxd_driver_register; 544 545 err = idxd_cdev_register(); 546 if (err) 547 goto err_cdev_register; 548 549 err = pci_register_driver(&idxd_pci_driver); 550 if (err) 551 goto err_pci_register; 552 553 return 0; 554 555 err_pci_register: 556 idxd_cdev_remove(); 557 err_cdev_register: 558 idxd_unregister_driver(); 559 err_idxd_driver_register: 560 idxd_unregister_bus_type(); 561 return err; 562 } 563 module_init(idxd_init_module); 564 565 static void __exit idxd_exit_module(void) 566 { 567 pci_unregister_driver(&idxd_pci_driver); 568 idxd_cdev_remove(); 569 idxd_unregister_bus_type(); 570 } 571 module_exit(idxd_exit_module); 572